JPS6027118B2 - semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device improved to further improve read speed.

A semiconductor memory device is constructed using, for example, a nonvolatile semiconductor memory element having a floating gate.

As shown in FIGS. 1A to 1C, this floating gate type nonvolatile semiconductor memory element has a source 12 and a drain 13 formed of n+ regions on the surface of a P-type substrate 11.
A control gate 16 is provided between the source 12 and the drain 13 via an oxide film 15 so that a channel 14 is formed. A floating gate 17 is embedded in this oxide film 15. FIG. 3D shows the symbol of the floating gate type nonvolatile semiconductor memory element. In the floating gate type non-volatile semiconductor memory element configured in this way, the floating gate 17
By injecting electrons into the gate, the value voltage y ratio is set to increase, and in this state, a normal gate voltage signal applied to the control gate 16 will not turn it on. In addition, when electrons are not injected, by applying a gate voltage signal to the control gate 16, the connection between the source 12 and the drain 13 is turned on, and depending on the gate voltage signal, it becomes "1" or "1". This constitutes a memory element 18 from which output information of "0" can be obtained. However, in such a memory element 18, the floating gate 17
In order to improve the efficiency of electron injection into the memory element and to increase the current flowing through the memory element when reading data, the potential of the floating gate 17, which is an effective gate, is sufficiently raised when the potential of the control gate 16 rises. It becomes necessary.

As is clear from the figure, in this memory element,
Between the control gate 16 and the floating gate 17, between the floating 17 in the field part and the base 11,
Furthermore, between the floating gate 17 and the channel 14,
They have capacitances C and C3, respectively, and let the potentials of the control gate 16 and floating gate 17 be VcG and VF, respectively. This Vcc and V
p is expressed as the following formula.

C, VF=C, 10C20C3VcG As you can see from this formula, floating gate 1 7
In order to raise the potential of C, it is sufficient to increase the capacitance C compared to the capacitance C3. One method for this purpose is to thin the insulating film between the floating gate and the control gate. When the thickness is reduced, fleas in the floating gate tend to escape, which poses a reliability problem.

Another method is to make the floating gate larger. That is, the distance between the floating gate where the capacitance C2 is formed and the substrate is normally 7000A, and the distance between the substrate and the floating gate is usually 7000A. - The distance between the ting gate and the control gate is about 1000A, so if you compare them on a unit area basis,
C,>C2. Therefore, if the floating gate is made larger while keeping the channel portion constant, C, will become larger than the increase in C2 + C3 since C, is much larger than C2. FIG. 2 is a plan view showing the configuration of a memory device composed of the memory elements 18 as described above, and includes a plurality of row lines 19, 192, . , this row line 19,,192
. . , a plurality of memory elements 18, . ，
18, 2, etc. are now arranged.

For example, for row line 19, memory elements 18, . ，
18, 2, . . . are arranged at equal intervals, and their respective gates 16 are connected and arranged in correspondence. Specifically, adjacent memory elements 18, . , 18, 2... each gate 1
6 are connected to form a row line 19. Similarly, for row line 192, memory elements 182, 18
22... are formed, in which case the opposing memory elements 18, . and 182., 18.2 and 1822,...
・Set the drain electrodes facing each other and make them common.
It has a configuration in which it is connected to column lines 20, 202, . . . .
The source is connected to the ground line GND.
That is, each memory element 18, . , 18, 2... are the horizontal lengths of floating gate 1 indicated by diagonal lines in the figure.
7 and W in the channel of the transistor.

However, in order to improve memory integration, it is required that the floating gate 17 and the inside of the channel be made as small as possible. Therefore, W in the channel is set to the minimum size allowed to perform the transistor function, for example, the control gate potential VcG
At present, the size of the floating gate 17 is determined so that the potential of the floating gate is about 3 V when is 5 V. Therefore, the conductance of the memory element does not rise to 9 m', and when Vcc is 5 V and the drain voltage is 5 V, an output current of only about 100 A can be obtained. As a result, the source and drain of this memory element are turned on, and it takes a long time to discharge the column line because the capacity of the column line is large and the current flowing through the memory element is small. The read speed of a memory device is limited by the column line discharge time of the memory element, and about half of the data read time is spent on this discharge time. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor memory device that can sufficiently improve the read speed of data stored in a memory element.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 shows the circuit configuration. A plurality of row lines 19, to 19n and column lines 201 to 20m are arranged in a matrix, and a floating gate type MOS as described above is installed at each intersection. Memory element 181, ~18, skin 182, ~182 consisting of a transistor
The skin... is arranged. The gates of the respective memory elements are connected to the corresponding row lines 19 to 19n, the drains are connected to the corresponding column lines 20 and 20m, and the sources are connected to ground. In a memory device configured in this manner, one memory element is selected and specified by specifying row lines and column lines.
Do it in 2. The row decoder 21 is supplied with row address data Ao to Ai from a CPU (not shown), etc., and receives a signal C.
, ~Cn, "
1'' level signal is generated to designate that row line. On the other hand, the column decoder 22 similarly receives column address data ~Am.
is supplied and generates one of the signals R, ~Rm, and the column line 20
, 20m is connected in series with the enhancement type MOS transistors 23, 23m. The drains of these transistors 231 to 23m are connected in common, and a power supply Vc is supplied to this common connection portion S via a depletion type MOS transistor 24 for load. Therefore, when a "1" level signal is supplied to the gate of one of the transistors 23, to 23m, and the source and drain are turned on, the column line connected to that transistor is designated, and the power supply Vc is It will be connected.
The logic potential level of the common connection portion S of the column lines 20, .about.20m is output from the output terminal 0 via the output circuit 25 as read digital information. On the other hand, the other end of each column line 20, to 20m is connected to the drain of each enhancement type MOS transistor 261 to 26m.

The sources of each of the transistors 26 and 26m are grounded, and the output signal P from the pulse generating circuit 27 is supplied to the gate of each transistor. This pulse generating circuit 27 is set to an operating state by an address input signal, and the row and column decoders 2
When the address data ~Am supplied to the transistors 1 and 22 changes as shown by A in FIG. 4, a signal P is generated as shown in B in FIG.
is turned on. In other words, the column line 20.~20m is
0” level. Then, as shown in FIG. 4C, when the designated row line is charged and reaches the "1" level, the signal P
is at the "0" level. Therefore, pulse generation circuit 2
Reference numeral 7 generates a pulse that sets the signal P to the "1" level from the time the address data changes until the row line is specified (for example, 8 seconds). In a thin semiconductor memory device configured in this way, the pulse generation circuit 2
When the content of the address data supplied to 7 changes, the output signal P goes to the "1" level.

Therefore, transistors 26, .about.26m are turned on, and column lines 20, .about.20m are discharged. On the other hand, address data is also supplied to row and column decoders 21, 22, and for example, row line 19 and column line 20 are specified, and memory elements 18, . Suppose that is selected. At this time, if no electrons are injected into the floating gate of transistor 1811, transistor 18. is turned on, discharging the column line 20, and a "0" level signal is outputted via the output circuit 25. In this case, since the column line 20 has already been discharged and is at the "0" level, the output becomes the "0" level very quickly. Also, transistors 18, . When electrons are injected into the floating gates of transistors 18, . is kept off even if it is selected, and "
A signal of level “1” is supplied to the output circuit 25, and the signal “1” level is supplied to the output circuit 25.
" is output. In this case, the column line 20 is charged by the transistor 24;
If the conductance gm of the column line 4 is set sufficiently large, the charging speed of the column line 20 can be sufficiently increased. In other words, the data read speed becomes faster. In addition, recent semiconductor memory LSIs (large scale film integrated circuits) have a power-down mode, which has a function that reduces current consumption by not operating the internal circuitry when the LSI is not selected. For such devices, a pulse may be output when the power down signal changes in the same way as when the address changes.

(This is because such a power-down signal and address are often changed and used at the same time.)
Further, circuits such as a decoder and an address buffer for 1 having such a mode are well known and will therefore be omitted. Furthermore, the operation and non-operation of the pulse generation circuit may be controlled by a power down signal.

Note that the signal P remains “1” for a long time even after a new row line is designated.
``Conversely, being at this level prevents column line charging and slows down the read speed of memory cells whose floating gates are injected with a box.

Therefore, after a new row line is specified, immediately “
It is desirable that the signal P becomes "0". Rather, it is optimal to set the signal P to "0" during charging of the row line. Good too.

In this case, if the output from the column decoder is made faster than the change in the row line, the column line will be discharged via whichever one of the transistors 23, . . . 23m is in a conducting state. A pulse may be generated when any one of all address inputs changes, but it is also possible to generate a pulse only when the input address of the row decoder changes.

In other words, the column lines are connected to transistors 23, -2 in FIG.
3m is in the unselected state and in the cutoff state, it is disconnected from the load transistor 24. Therefore, the non-selected column lines have already been discharged, and there is no need to specifically discharge them in place of the column decoder. Note that although a floating gate type MOS transistor is used as the memory element in the above embodiment, other memory elements may be used.

As described above, according to the present invention, it is possible to provide a semiconductor memory device in which the reading speed of data stored in a memory element is further improved.

[Brief explanation of drawings]

Figures 1A to 1C illustrate a floating gate MOB transistor used as a memory element, where A is a plan view, and B and C are lines bb and cc in Figure A, respectively. A cross-sectional configuration diagram, FIG. 1D is a diagram showing the symbols of the elements, FIG. 2 is a plan view showing a memory device composed of the above-mentioned memory elements, and FIG. 3 is a semiconductor memory device according to an embodiment of the present invention. FIG. 4 is a timing chart explaining the operation of the above device. 18,. ~18nm...Floating gate type M○S
Transistor, 2 1...Decoder, 2 2...
...Column decoder, 23.~23m...Enhancement type MOB transistor, 24...Depression type MOS transistor, 25...Output circuit, 26,~
26m...Enhancement type MOS transistor, 27...Pulse generation circuit. Figure 1 Figure 1 Figure 2 Figure 4 Figure 3

Claims (1)

[Claims] 1 row line, a row decoder that selects this row line based on input address data, a memory cell driven via this row decoder and the row line, a column line that receives data from this memory cell, and an address. A semiconductor memory device comprising: means for discharging the column line in the direction of the source side potential of the memory cell for a predetermined period of time from the time of data change.