JPH0143400B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a read-only semiconductor memory device in which data can be electrically rewritten.

A double gate type with two gate electrodes: a floating gate and a control gate.
Read-only semiconductor memory devices that use MOS transistors as memory cells, that is, read-only memories, are currently used in many electronic devices.

Figures 1 and 2 show the above double gate type.
Using MOS transistors as memory cells,
This shows the configuration of a conventional semiconductor memory device, and the first
The figure is a circuit diagram, and FIG. 2 is a plan view of the pattern. In the figure, 1 is each memory cell, 2 is a row line that also serves as a control gate of each memory cell, 3 is each floating gate, 4 is a column line, 5 is a drain, 6 is a source to which a ground potential is applied, and 7 is a drain This is a contact hole that connects the column line 5 and the column line 4. In a storage device having such a configuration, data is set in advance depending on whether or not electrons are injected into the floating gate 3. That is, in the memory cell 1 in which electrons are injected into the floating gate 3, the threshold voltage increases, and in the memory cell 1 in which no electrons are injected, the threshold voltage does not change. If , the memory cell 1 with a high threshold voltage is turned off, and the memory cell 1 with a low threshold voltage is turned on. Therefore, data of "1" or "0" is read out.

By the way, in the above conventional memory device, when injecting electrons into the floating gate 3 for data writing, the drain 5 of the memory cell 1 is
A high voltage is applied to both the control gate and the row line 2, and an ion bombardment current is generated near the drain 5 of the control gate. Therefore, it is necessary to decide whether or not to inject electrons for each memory cell 1, so it is necessary to apply a high potential and a ground potential to each memory cell. As a result, it is necessary to arrange the memory cells as shown in FIG. 1 and in a pattern as shown in FIG. There is a drawback.

This invention has been made in consideration of the above circumstances, and its purpose is to provide a semiconductor memory device that can reduce the chip size by reducing the area occupied by memory cells. be.

By the way, FIG. 3 is a sectional view showing the structure of a double gate type MOS transistor used as the memory cell. In the figure, 8 is the substrate, 6, 5
are the source and drain, 2 is the row line that also serves as the control gate, 3 is the floating gate,
The row lines 2 and floating gates 3 are usually made of polysilicon. Insulators such as silicon oxide are interposed between the row line 2 and the floating gate 3 and between the floating gate 3 and the substrate 8, respectively. Therefore, capacitances C 1 and C ₂ exist between the row line 2 and the floating gate 3 and between the floating gate 3 and the conductive channel or substrate 8 between the source ₆ and the drain 5. . In such a structure, when the electric field between the row line 2, which also serves as a control gate, and the floating gate 3 exceeds a certain value, a tunnel current flows between the two gates. In Figure 4, the horizontal axis represents the strength of the electric field,
The vertical axis represents the current density. As shown in FIG. 4, when the electric field strength between the row line 2 and the floating gate 3 exceeds Ec, a current flows between them. Further, if the potential of the row line 2 which also serves as a control gate is V _CG , the potential V _FG of the floating gate 3 at this time is given by the following equation.

V _FG = C ₁ /C ₁ +C ₂ V _CG (1) If C ₂ is twice C ₁ , the above equation (1) becomes the following equation.

V _FG = 1/3V _CG ...(2) In other words, if there is a potential relationship as shown in equation (2) above,
The electric field between the row line 2 and the floating gate 3 is greater than the electric field between the floating gate 3 and the conductive channel or substrate 8. Therefore, if the electric field strength Ec shown in FIG. 4 is set to an intermediate value between the above two electric fields, the floating gate 3
A flow of electrons occurs from the line 2 toward the row line 2. Therefore, electrons are emitted from the floating gate, holes remain there, and the floating gate becomes positively charged. If we lengthen the time during which this electron flow occurs, the threshold voltage of the MOS transistor changes from positive to negative, as shown in Figure 5.
Once the threshold voltage becomes negative, it will turn on even if the control gate potential is zero. This invention is a double gate type as mentioned above.
This takes advantage of the properties of MOS transistors.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 6 is a circuit diagram of a semiconductor memory device according to the present invention. In the figure, 11 is a column decoder that decodes column address signals a ₀ , ₀ , a ₁ , ₁ , . . . , 12 is a MOS transistor for column selection driven by the decoded output of this column decoder 11,
13 is a column line, 14 is a row address signal A ₀ , ₀ ,
A row decoder 15 decodes A ₁ , ₁ , . . . , and a row line 16 is a memory cell consisting of a double gate type MOS transistor having a control gate and a floating gate. Of these, the same number of memory cells 16 are connected in series to form a plurality of series circuits 17. One end of each series circuit 17 is connected to each column line 13, and the other end receives a gate input signal R/ for setting the storage device in either data read mode or data write mode. each
It is connected to a ground potential point, that is, a reference potential point, via a MOS transistor 18. In addition, memory cells 1 at corresponding positions in each series circuit 17 described above
Each of the 6 control gates is connected to the same row line 15. Further, the other ends of each of the column selection MOS transistors 12 are commonly connected, and between this common connection point S and the positive polarity power supply voltage VD application point, a load circuit whose gate input is the clock signal φ is connected. MOS transistor 19 is connected. Further, between the connection point S and the ground potential point, a gate input is a signal A which is set to "1" or "0" depending on the written data when writing data to each of the memory cells 16. MOS transistor 20 is connected. Furthermore, each of the column lines 13 and
A plurality of load MOS transistors 21 whose gates receive the clock signal φ are connected to the V _D application point.

Note that each memory cell 16 has its threshold voltage set to negative or It is assumed that this is set correctly.

Next, the operation of reading data from the storage device configured as described above will be explained using the timing chart shown in FIG. First, when reading data, the signal R/ is set to a data read mode, that is, "1", and the signal A is set to "0". When signal A is set to “0”, MOS
Transistor 20 is turned off and becomes irrelevant to the operation during data reading. Also, when signal R/ is set to “1”, each
The MOS transistor 18 is turned on, and one end of each series circuit 17 is connected to the ground potential point. Next, during the period when φ is "1", one memory cell 16 in one series circuit 17 is selected by the column decoder 11 and the row decoder 14.
Suppose that is selected. When φ becomes "1", the load MOS transistors 19 and 21 are turned on, and the connection point S and each column line 13 are charged and become "1". At this time, the row decoder 14 outputs a "0" signal to the selected row line and a "1" signal to the unselected row line. Therefore, a "1" signal is applied to the control gate of each unselected memory cell 16 in the series circuit 17, and all these memory cells 16 are turned on. On the other hand, in the series circuit 17, a "0" signal is applied to the control gate of the selected memory cell 16. If the threshold voltage of the selected memory cell 16 is set positive in advance, this memory cell is turned off. If the selected memory cell 16 is off during the period when φ is “1”, the column decoder 11 selects the MOS
The column line 13 charged to "1" by the transistors 19 and 21 is not discharged, so that the connection point S remains at "1" at this time. Further, if the threshold voltage of the selected memory cell 16 is previously set to a negative value, this memory cell is turned on. Therefore, the column line 13 and the connection point S, which are charged to "1" at this time, are discharged by the series circuit 17, and the connection point S becomes "0". That is, if the signal at the connection point S is detected during the period when φ is "1", the data written in advance in the selected memory cell can be obtained. Also, of course, φ is “1”
Alternatively, the column line 13 may be charged in advance, and then the unselected row line may be set to "1", and the signal at the connection point S at that time may be detected.

Next, the operation for writing data into each memory cell 16 will be explained using the timing chart shown in FIG. First, when writing data, the signal R/ is set to data write mode, that is, "0". When the signal R/ is set to "0", each MOS transistor 18 is turned off, and one end of each series circuit 17 is separated from the ground potential point. Next, suppose that one memory cell 16 in one series circuit 17 is selected by the column decoder 11 and the row decoder 14 during the period when φ is "1". When φ becomes "1", the load MOS transistors 19 and 21 are turned on in the same way as described above, and the connection point S and each column line 1 are turned on.
3 is charged and becomes "1". At this time, the row decoder 14 applies a positive high potential voltage V ₁ to the selected row line.
, the unselected row line has a voltage lower than this V ₁ .
V ₂ is output respectively (assuming that both V ₁ and V ₂ are higher in potential than the “1” signal potential).
Further, at this time, if the signal A applied to the gate of the MOS transistor 20 is set to "0" in accordance with the write data, the MOS transistor 20 is turned off. Also, since the control gates of all memory cells 16 in the series circuit 17 selected by the column decoder 11 are now supplied with a voltage V ₁ or V ₂ that is higher in potential than the "1" signal, All of these memory cells are in the on state. Furthermore, since the MOS transistor 20 is in the off state, the connection point S and the selected column line 1
3 is also at a potential corresponding to "1", and since all the memory cells 16 in the series circuit 17 are in the on state, the potential of each source and drain is also "1".
has risen to a potential corresponding to . In this state, a high potential voltage is applied to the control gate of the selected memory cell 16 in the series circuit 17.
V ₁ is given, the source of this memory cell,
Since the drain voltage has also increased, the electric field between the control gate and floating gate of this memory cell 16 does not exceed Ec in FIG. 4, and therefore no current flows between the two gates. First, since no electrons are emitted from the floating gate, the floating gate remains in a neutral state and its threshold voltage remains positive and does not change.

On the other hand, if the symbol A is set to "1" according to the write data, the MOS transistor 20 is turned on, and all the memory cells 16 in the series circuit 17 selected by the column decoder 11 are turned on. The source and drain voltages become zero. In this state, a high potential voltage is applied to the control gate.
In the selected memory cell 16 to which V ₁ is applied,
The electric field between the control gate and the floating gate becomes greater than Ec, electrons are emitted from the floating gate, and the threshold voltage changes from positive to negative.

That is, data is written by setting the threshold voltage of each memory cell 16 to be positive or negative in this manner.

9 and 10 are pattern plan views of the memory cell array portion of the semiconductor memory device shown in FIG. 6, respectively, and portions corresponding to those in FIG. 6 are given the same reference numerals. Further, in FIGS. 9 and 10, 31 is each floating gate, and 32 is a source or drain. Since a plurality of memory cells are connected in series, there is no need to apply a ground potential to the source of each memory cell as in the conventional case, and there is no need for a contact hole to connect each drain to a column line. Therefore, the area occupied by the memory cells can be reduced, and as a result, the chip size of the entire memory device can be reduced.

11 and 12 are circuit configuration diagrams specifically showing the row decoder 14, respectively. 1st
In Figure 1, in the data read mode, the signal /W, which has an opposite phase relationship with the signal R/, is "0".
It is. Therefore, the MOS transistor 41 is turned off.
The MOS transistor 42 is turned on, and points a and b
The points become "1" and "0", respectively. Therefore, one MOS transistor 4 connected to the row line 15
3 is off, the other MOS transistor 44 is on, and point c is connected to the row line 15. When the row line 15 is selected, the point d becomes "1", the point c becomes "0", and therefore a "0" signal is output to the row line 15.

On the other hand, the signal /W is "1" in the data write mode. Therefore, the MOS transistor 41 is turned on, the MOS transistor 42 is turned off, and the point b becomes "1". Furthermore, the MOS transistor 43 is turned on, and the MOS transistor 44 is turned off, so that the point e is connected to the row line 15. Now, when this row line 15 is selected, point d is "1" and point f is "0".
Therefore, the potential at point g is the positive high potential power supply voltage.
Threshold voltage of MOS transistor 45 than Vp
The potential is lower by Vth (Vp - Vth). Therefore, the subsequent depletion type MOS transistor 46 is turned on, and the potential at point e becomes Vp. Therefore, a potential (Vp-Vth) obtained by subtracting the threshold voltage Vth of the MOS transistor 43 from the potential Vp at point e is output to the row line 15. Note that this potential (Vp
-Vth) corresponds to the above-mentioned _V1 . Also, when this row line 15 is under the non-selection condition, the d point is "0", the f point is "1", and the g point is "0".
The MOS transistor 46 is turned off, and the potential at point e is
The potential is obtained by subtracting 2Vth, the sum of the threshold voltages of the two MOS transistors 47 and 48 connected in series, from Vp (Vp-2Vth). At this time, since the potential of the "1" signal at point b is Vp, the potential at point e (Vp-2Vth) is output to the row line 15 as is. Note that this potential (Vp-2Vth) is the same as above.
It is equivalent to _V2 . Furthermore, when the row line 15 changes from the selected state to the non-selected state, the MOS transistor 49, which is connected to the above point e and receives the signal /W as a gate input, converts the point e to (Vp-Vth).
This is for discharging from (Vp-2Vth).

In addition, in FIG. 12, in the data read mode, the signal /W is "0" and the signal R/ is "1", so the MOS transistor 51 is off and the MOS
Transistor 52 is turned on, and point i is on row line 15.
connected to. Now, when the row line 15 is selected, the j point becomes "0" and the k point becomes "1", so the i point becomes "0" and therefore the row line 15 becomes "0". A signal is output.

On the other hand, in data write mode, the signal /W
Since is "0", the MOS transistor 51 is turned on, the MOS transistor 52 is turned off, and one point is connected to the row line 15. At this time, the "1" level of this R/W is the potential of Vp'. Now, when the row line 15 is selected, point j becomes "0" and the potential at point m is lower than Vp' by the threshold voltage Vth of the MOS transistor 53 (Vp' - Vth). becomes. Therefore, the following depletion type MOS transistor 5
4 is turned on, and the potential at one point becomes Vp'. Therefore, a potential (Vp'-Vth) obtained by subtracting the threshold voltage Vth of the MOS transistor 51 from the potential Vp' at one point is output to the row line 15. Also, this potential is
It corresponds to V ₁ . Moreover, when this row line 15 is under the non-selection condition, the j point is "1" and the m
The point becomes "0", the MOS transistor 54 is turned off, and the potential at one point changes from Vp' to the two connected in series.
The potential is obtained by subtracting 2Vth, the sum of the threshold voltages of the MOS transistors 55 and 56 (Vp'-2Vth). Therefore, since the gate voltage of the MOS transistor 51 is Vp', the same potential as the one point (Vp'-2Vth) is output to the row line 15. Further, this potential corresponds to the above-mentioned V ₂ , and furthermore, the MOS transistor 57 connected to one point and having the signal /W as a gate input is connected to the above-mentioned eleventh potential.
Similar to the MOS transistor 49 in the figure, this is for discharging one point from (Vp'-Vth) to (Vp'-2Vth) when this row line 15 switches from a selected state to a non-selected state. be.

FIG. 13 is a cross-sectional view showing the structure of a double-gate type MOS transistor suitable for use in the memory ^cell 16 in FIG. is an N ⁺ type drain, 64 is a control gate, 65 is a floating gate, and 66 is an insulating layer. This MOS
In the transistor, the distance between the control gate 64 and the floating gate 65 is made smaller in some parts, and made larger in other parts, and by configuring it in this way, the distance shown in FIG. The relationship C ₁ <C ₂ in capacity can be easily realized. That is, in order to lower the potential V _FG of the floating gate given by the above equation (1) and increase the electric field between the control gate and the floating gate, the value of the capacitance C ₁ needs to be reduced. . Furthermore, in order to reduce the value of this capacitance _C1 , it is sufficient to increase the distance between the control gate and the floating gate. However, if the overall distance between the control gate and the floating gate is increased, the electric field between them becomes smaller. However, by reducing part of the distance between the control gate and the floating gate as shown in Figure 13, the electric field between the control gate and the floating gate can be reduced while keeping the value of capacitance _C1 small. can be made larger.
Furthermore, if part of the distance between the control gate 64 and the floating gate 65 is set to 800 Å as shown in FIG. It can be removed in time.

FIGS. 14 to 16 are for explaining other embodiments of the present invention, respectively. In each series circuit 17 in FIG. 6, if there are a large number of memory cells 16 connected in series, it is difficult to raise the source and drain of all memory cells to "1" in a short time. Therefore, as shown in FIG. 14, the clock signal φ', which has a period in which it is "1" prior to a period in which φ="1",
Alternatively, by using a clock signal that has a period of "0" preceding the period of φ = "1", a potential of V 2 is output to the selected row line during the period of φ', and the potential of V ₂ is output to the selected row line during this period. It is designed to output a potential of _V2 to the row line. and the first
The row decoder shown in FIG. 5 has such a function added to the row decoder shown in FIG.
A MOS transistor 50 whose gate input is . Moreover, the one shown in FIG. 16 is the row decoder shown in FIG. 12 with such a function added, and in order to realize this function, the address signals A ₀ , A _{1 .} . . are used as gate inputs. M.O.S.
A MOS transistor 58 whose gate input is a clock signal φ' is inserted in series with the transistor.

As explained above, in the semiconductor memory device according to the present invention, it is possible to reduce the chip size by reducing the area occupied by the memory cells.

[Brief explanation of drawings]

1 and 2 respectively show the configuration of a conventional semiconductor memory device, FIG. 1 is a circuit diagram thereof, FIG. 2 is a pattern plan view, and FIGS. 3 to 5 each illustrate the principle of the present invention. This is for the purpose of the third
The figure is a cross-sectional view, Figure 4 is a characteristic diagram, Figure 5 is a characteristic diagram,
FIG. 6 is a circuit configuration diagram of an embodiment of the present invention, and FIG.
9 and 8 are timing charts for explaining the operation of the above embodiment circuit, respectively, FIGS. 9 and 10 are pattern plan views of the memory cell array portion in the above embodiment circuit, and FIGS. 11 and 12, respectively. The figures are respectively circuit configuration diagrams of the row decoder part in the above embodiment circuit, FIG. 13 is a sectional view of the memory cell part in the above embodiment circuit, and FIGS. 14 to 16 show other embodiments of the present invention. Show, first
4 is a timing chart, FIG. 15 is a circuit configuration diagram, and FIG. 16 is a circuit configuration diagram. 11... Column decoder, 12, 18, 19, 20,
21...MOS transistor, 13...column line, 14...
Row decoder, 15...Row line, 16...Memory cell, 1
7...Series circuit, 31...Floating gate, 3
2...Source or drain.

Claims (1)

[Claims] 1. A floating gate and a control gate are provided, and by partially reducing the distance between the control gate and the floating gate, the electric field strength between the control gate and the floating gate is reduced. The electric field strength is set to be greater than the electric field strength between the floating gate and the conductive channel or substrate, and based on the written data, electrons are emitted from the floating gate or remain in a neutral state without being emitted. A series circuit consisting of a plurality of insulated gate field effect transistors connected in series, whose threshold voltage is set to be negative or positive by Select one transistor in the series circuit according to the address signal at the time, supply a low logic signal to the control gate of the selected transistor, and supply a high logic signal to the control gates of all the transistors not selected. A semiconductor memory device comprising: a decoder. 2. It has a floating gate and a control gate, and by partially reducing the distance between the control gate and the floating gate, the electric field strength between the control gate and the floating gate can be reduced between the floating gate and the conductive channel or The electric field strength is set to be greater than the electric field strength between the floating gate and the floating gate, and this is done by either emitting electrons from the floating gate based on the written data in advance, or by leaving the floating gate in a neutral state without emitting electrons. A series circuit consisting of a plurality of insulated gate field effect transistors connected in series whose threshold voltage is set to be negative or positive, and a series circuit inserted between one end of this series circuit and a power supply voltage application point. a load element that charges one end;
A switch element is inserted between a connection point between the series circuit and the load element and a reference potential point, and is switch-controlled according to the write data, and a switch element is inserted between the connection point of the series circuit and the load element and the reference potential point, and the switch element is controlled as a switch according to the write data. A semiconductor memory device comprising a decoder that selects a transistor and supplies a high potential to the control gate of the selected transistor and a low potential to the control gates of all unselected transistors.