JPS60136996A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To improve the read speed of a data by connecting a transistor (TR) between a column line and ground, applying a prescribed voltage to a gate so as to conduct the TR continuously during data read period and discharging the column line via the TR. CONSTITUTION:A TR31 is provided between the column line 20 and ground, the TR31 is turned on when the data is read from a memory element 18 so as to discharge the column line 20, then no overcharging takes place, the discharge of the line 20 is not required thereby quickening the data read speed for the share. In setting the capability of TRs 25, 29 so as to provide the same current capability as the case with no provision of the TR31, the charging speed is decreased. In setting the TRs 25, 29 to the capability to assist the discharge of the TR31, the charging is conducted in the same speed and the discharge is quickened for the share of no overcharging, thereby reading quickly the data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device that has been improved so that its read speed can be further improved.

[Technical background of the invention]

2. Description of the Related Art Among semiconductor memory devices, there is a nonvolatile semiconductor memory device configured using a nonvolatile semiconductor memory element having a floating gate as a memory cell.

This floating? -) type non-volatile semiconductor memory element consists of an n+ region on the surface of a p-type substrate 11 as shown in FIG.
A control field 16 is provided through an oxide film 15 so that a channel 14 is formed between the north 12 and the drain 13. A floating cell 17 is embedded in this oxide film 15. FIG. 6(6) shows a singel of the floating r-) type nonvolatile semiconductor memory element.

In the floating r-) type nonvolatile semiconductor memory element constructed in this way, by injecting electrons into the floating dirt 17, the threshold voltage vTh
In this state, the r-) voltage signal applied to the normal control r-) 16 will not turn it on. Also, if no electrons are injected, the threshold voltage remains as low as before! l), r
By applying a -1 voltage signal to the controller k)r'-) 16, an inversion channel is created between the source 12 and drain 13, resulting in an on state. i.e. r-)
The memory element 18 is configured to obtain output data of "1" or "0" in response to a voltage signal.

However, in such a memory element 18,
In order to improve the injection efficiency of i-sons into the floating dart 17 and to increase the current flowing through the memory element when reading data, the potential of the floating dart 17, which is the effective r-), is controlled by controlling r. -) 16
It is necessary to raise the potential sufficiently when the potential rises.

It is clear from the figure that the memory element with
Control r-volume 16 and floating f-rt, 17
between the floating dirt 17 and the base 11 in the field part, and between the floating dirt 17 and the channel 1.
4, each having a capacitance of C1-C5.
Control R-16 and Floating Dart 1
If the potentials of 7 are respectively VCQ I'VF, this V is expressed as the following equation.

As can be seen from this equation, in order to increase the potential of the floating group 17, it is sufficient to increase the capacitance C compared to the capacitor C3.
There is a method of forming an insulating film with a varying thickness between control r-) and control r-). When Niro thins the film thickness, it becomes 70
There is a problem with reliability because electrons in the P-Ting P-) tend to escape easily. Another method is to increase the size of the floating groove. That is, the distance between the substrate and the 70-chiing f- where the capacitor C2 is formed is normally 7000X.

Since the distance between t7'c70-taing dart, control, r, and g is about 1-1.1000X, when comparing in unit area, %C1>C:2. Therefore, if the channel part is kept constant and 70-chiing r-) is made thicker, C1
Since, is much larger than C, CI increases as much as C,+C, increases.

FIG. 2 is a four-turn plan view showing the configuration of a storage device using the memory element 18 as described above. A plurality of row lines 191 + 192 . . . extending in the horizontal direction at equal intervals are provided, and the row lines 19□.

19□...In each, a plurality of memory elements 18
11+1812... will be placed. For example, for row line 191, memory element 21! +11+
18t3... are arranged at equal intervals, and each r
- the volumes 16 are correspondingly connected and arranged; Specifically, the r-cells 16 of adjacent memory elements 1 & 11+ 18t2 . . . are connected to form a row line 191. Similarly, for row line 192, memory element 18
2B 18z*... are formed, in which case the opposing memory elements 1811 and 1821+1812 and 1
The drain electrodes 82 = . And the north is the ground wire (GND)
It is connected to the.

[Problems with background technology]

In FIG. 2, each memory element 1811+7812...
The lateral length of * is determined by the dimensions of the floating groove i7 indicated by diagonal lines in the figure and the channel width W of the transistor. However, me%! j In order to improve the concentration of 8 degrees, the dimensions of the floating groove 17 and the channel width are required to be as small as possible. Therefore, the channel width W is set to the minimum allowable size to perform the transistor function.For example, when the potential VCa of the control r-) is 5V, the floating ?
-) so that the potential of the floating f is about 3V.
- The current situation is to determine the dimensions of J7. Therefore, the conductance gm of the memory element increases by % v
When co is 5V and the drain voltage is 5V, only an output current of about iooμA can be obtained. As a result, the connection between the source and +4 lane of this memory element was in an on state, and it took a long time to discharge the column line because the column line had a large capacity and the current flowing through the memory element was small. . The data read speed of the memory device is limited by the column line discharge time of the memory element, and as a result, the data read time becomes slow and high-speed operation cannot be achieved. The present invention was developed in consideration of the above circumstances, and its purpose is to provide a semiconductor memory device that can realize high-speed operation by improving the reading speed of data stored in a memory element.

[Summary of the invention]

In the semiconductor memory device according to the present invention, a transistor is connected between a column line and ground, and when data is read from a memory cell, a constant voltage is supplied to the r- field of this transistor so that the transistor is connected during the data read period. The transistor is continuously turned on, and the column line is discharged through this transistor.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 3 shows the circuit configuration, in which a plurality of rows 1m19x to 9n and column lines 2o1 to 20n1 are arranged in a matrix, and each intersection has a floating tart type MO8 as described above. Memory elements 1811 to 181m+l8z made of Lanzostar
x~182m1... are arranged. The start of each memory element is connected to the corresponding row line 191 to 19n, and the drain is connected to the corresponding column line xo.
1-2QIn, and all sources are connected to ground. To select one memory element above,
Selecting one row line and one column line respectively is performed, and this selection of row lines and column lines is performed by selecting one row line and one column line.
- It is carried out at 21°22. The row decoder 21 receives row address data A (1-AI
is supplied to the row lines 191 to 191 by the output signal 01%Cn.
19n is generated to select the row line. On the other hand, the column decoder 22 is similarly supplied with column address data Ai+1 to Am, and the output signal R1
~ Set one of Rm to [1] level and set column line 201 to 20m
Enhancement 1M08) Any one of the transistors 231 to 23m connected in series to the line is turned on to select that column line. The above transistors 231 to 23
The drains of m are connected in common, and this common connection node S is connected to the power supply Vc via an installation type MO8) for load, and its r-) is
It is connected to the output node T of the inverter I. This inverter I is a depression WMO8) Lanzosta 26,
Enhancement type MO8) E consisting of transistor 27
It is of the 1D type, and f-) of the MOS transistor 27 serving as the input terminal is connected to the node S. The output of the input/output terminal I is further connected to the above node S and the data sense node U.
Enhancement gMO8) Lansostar 281) connected between? The data sense node U is connected to the power supply VC via another load transistor 29, and the data sense node U is also connected to the power supply VC. A data output circuit 30 is connected to node U, and data D stored in the memory element 18 is output from this data output circuit 30.

On the other hand, the other end of each column line 201-20n1 is connected to the drain of each enhancement type MO8) transistor 311-31m. This transistor 31. ~3
The source of each of the 1 m is connected to ground, and the output voltage of each f-) is supplied from the control circuit 32. This control circuit 32 includes the row decoder 21
is configured to continuously generate a constant DC voltage during a period in which the output C of any one of the memory elements 18 is set to "1" and one of the memory elements 18 is selectively driven to read data. ing.

In the semiconductor memory device configured in this manner, for example, one row 111191 and one column line 201 are selected by the row and column decoders 21 and 2jt, respectively, and
18 existing at this intersection! Suppose that l is selected. Now, electrons have been injected into the floating gate of this memory element 1811 in advance, and the threshold voltage is low →
If ' = q, this memory element 1811 is not in the on state, and the column line 201 is radiated via this memory element 1811 to the radiation path 30.
will be output from. The voltage waveforms at the nodes S, T, and H in FIG. 3 at this time are shown by solid lines in FIG. 4. This state in which the column line 201 is discharged is during the period T in FIG. When the column line 201 is discharged, the node S is also discharged, so that the output node T of the inverter I is not at the "1" level, the transistor 28 is sufficiently turned on, and the node U is also discharged and becomes the "0" level. It will be 4 hours. Incidentally, in this embodiment, a transistor 31 to which a constant voltage is applied to r-) is connected to the column line 18 in order to assist in discharging the column line. Each node S, T when this transistor 31 is not provided
, V are shown in dashed lines in FIG. When column line 201 is in a discharged state, transistor 32
-dfii The potential at the node 8U is higher and the potential at the node is lower than when it is not turned off. From this state, input address data A.

~Am changes, and the row decoder 21 inputs the row line 191K.
Assume that the row line 192 is selected instead, and the memory element 18 is selected. Also at this time, the transistor 1831
70-Chiing? It is assumed that electrons are injected into the transistor (-) in advance and the threshold voltage is increased so that the transistor does not turn on. After this, this column line 201 is charged. That is, this charging is performed by the transistors 29 and 25, but since the output of the inverter is initially at the [1] level, the transistor 25 is rapidly charged. When the output of the inverter I is inverted to the "0" level due to the rise in the potential at the node S, the transistors 28 and 25 are turned off. Thereafter, the node U is charged by the transistor 29, and the "1" level is read out by the data output circuit 30. This column line 201
and when node S is charged, in-? The transistor 28.25 is overcharged by a delay time of -/I. That is, the source side potential of the transistors 28 and 25 (the potential at the node S) is stabilized at a value obtained by subtracting the threshold voltage from the r-potential. However, in this case, due to the delay time caused by the inverter 2, the potential at the node S becomes higher than the r-potential of the transistors 28 and 25 minus their respective threshold voltages. Nodes S, T,
Let the potential of U be vs a vTl vU, respectively, and
yJxll;ttt,zs.

27 threshold voltages as Vth2a and Vth2i;
, Vrh27, in an ideal case without delay time due to inverter ■, -Vs = V'thzy *
Vy=vThz7+Vthzs, but inverter I
Due to the delay time caused by VB'), node S is overcharged.
VTh27. vT<vTh27+VTh25. However, in this embodiment, the transistor 31
exists, the overcharged portion is discharged by the transistor 31, leaving behind the peak portion at point
The potentials of the nodes S and U become stable at this point, and overcharging is eliminated. On the other hand, if No. 2 Inzostar 31 does not exist,
Node S and column line 20 remain overcharged, as shown by the dashed line in FIG. This is the full period in Figure 4.

Next, assume that the input address data changes, the row line 19n is selected by the row decoder 21, and the memory element 18n1 is selected. The layout of this memory element 18n1? -1 is a neutral state, that is, a state in which no electrons are injected. At this time, the column line 201 is connected to the memory element 18
It is discharged by n1. At this time, since overcharging has not occurred and the transistor 31 is present, the transistor 28 is slightly turned on. Therefore, potential changes on column line 20 and node S are quickly transmitted to node U. Further, since the column line 201 is discharged in parallel by the memory element 18n1 and the transistor 31, the column line 201 is discharged in parallel.
It is faster than when it is not set. Therefore, the inverter ■
The output of the transistor 28 also quickly rises to the "1" level, so that the transistor 28 is turned on, the node U is quickly discharged, and data is quickly read out by the data output circuit 3o. On the other hand, if transistor 31 is not present, node S and column line 20 are overcharged. Further, since many memory elements 18 are connected to the column line 2°, its parasitic capacitance is extremely large. Because of this, the overcharged column line 2
Because O must be discharged only from the memory element 18, it takes time to read data.

As described above, according to the above embodiment, the transistor 31 is provided between the column line 2o and the ground, and the transistor 31 is connected to the memory element 18 during the period when data is read from the memory element 18.
Since the column line 20 is discharged by turning on the column line 20, overcharging does not occur and there is no need to perform the corresponding discharge, so that the data read speed can be increased accordingly.

Note that in the above embodiment, the transistor 31 is always connected to the column line 2.
Since 0 is being discharged, if the capacity of transistors 25 and 29 as load transistors is set to have the same current capacity as when this transistor 31 is not provided, the charging speed will be slow. However, transistors ``-25 and 29'' do not have enough ability to sustain the discharge of transistor 31.

If the settings are made, charging can be done at the same calyx temperature, and discharging can be done faster due to the absence of overcharging, which has the advantage of being able to read data quickly.

The control circuit 3'2 in FIG. 3 may generate the power supply potential VC as an output voltage during the period when data is read from the memory chip 18, or the control circuit 3'2 in FIG. As shown in 4), it may be constructed of a desorption type MO transistor 41 and two enhancement type Mo transistors 42 and 43, and generate a constant voltage with low Vc, l:t). Furthermore, Figure 5 (
As shown in B), a signal Wt-1'-) which becomes the "1" level when programming data in the memory element is added to the enhancement type MO8) Lanzostar 44, and the output is set to the "o" level during programming. Alternatively, the transistor 31 may be turned off.

FIG. 6 shows another embodiment of the invention. In FIG. 3, the r-potential of the load transistor (transistor 25) is controlled by the output of an inverter to which the column line potential is input, but in FIG.
) A potential is obtained from a predetermined potential, for example, from the connection point of resistors 51 and 52 connected in series between the power supply VC and the ground. Further, the potential of the node S is fully amplified at the node U, and data is output from the data output circuit 30. Normally, a constant potential is applied to f-) and the drain is connected to the power supply in FIG. 7(4), that is, the transistor 25 in FIG.
The change in current ID with respect to the source potential V of a transistor with a circuit connection such as transistor 28 is shown in FIG. 7(B).
It will look like this. However, when the source potential is high, only a small amount of current flows, but as the source potential drops, the current suddenly flows. Therefore, in FIG. 6, the column line and node 8. When U discharges from a charged state, node U is discharged through a region where only a small amount of the d current of transistor 28 flows in the absence of transistor 31. In this region where only a small amount of current flows, the node U is hardly discharged. However, transistor 31
Therefore, even in the discharge state of the column line and nodes & and U, the column line is discharged with a small amount of current, and the source potential v1 is lowered to Vll in FIG. 7(B). Thus, transistor 28 operates close to a region where current flows rapidly. In this state, if a memory element whose floating dart is in a neutral state is selected, the column line is discharged. At this time, the transistor 28 turns on rapidly, so the node U
is quickly discharged, and data is quickly read out from the data output circuit 30.

In the above embodiment, a floating r-) type MO8) transistor was used as the memory element, but other memory elements may be used instead.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a semiconductor memory device that can realize high-speed operation by improving the reading speed of data stored in a memory element.

[Brief explanation of drawings]

Fig. 1 is a diagram showing a floating f-) type nonvolatile semiconductor memory element, Fig. 2 is a pattern plan view of a storage device using the memory element of Fig. 1, and Fig. 3 is an embodiment of the invention. 4 is a waveform diagram for explaining its operation, FIG. 5 is a circuit diagram specifically showing a part of the circuit of FIG. 3, and FIG. 6 is a diagram showing another embodiment of the present invention. FIG. 7 is a circuit diagram showing the configuration of an example. FIG. 7 is a circuit diagram and a characteristic diagram for explaining the circuit shown in FIG. 6. 18...Memory element, 19...Row line, 20...Column line, 21...Row decoder, 22...Column decoder, 2
3125.21.2B, 29.31... Enhancement type MO8) Lanzostar, 26... Desorption type MO3) Lanzostar, 30... Data output circuit,
32...Control circuit, 51.52...Resistance. Figure 2 Figure 3

Claims (1)

[Claims] A row line, a memory cell selectively driven by a signal on this row line, a column line to which data read from this memory cell is supplied, and a line connected between this column line and a base potential application point. A semiconductor memory device comprising: a transistor that is continuously rendered conductive at least during a period corresponding to a period during which data is being read from the memory cell.