JPS61186019A - Logic circuit - Google Patents

Abstract

PURPOSE:To invert the logical level of an output signal from a logic circuit section by applying exchange control to a power supply to be supplied to both power terminals of the logic circuit section depending on a control signal. CONSTITUTION:With a control signal of logical '1', a logical signal VA brought into a VCC level is fed to the 1st power terminal 27 of an inverter INV26 and a logical signal VB brought into a VSS level is fed to the 2nd power terminal 28 respectively. In this case, the INV26 is operated normally to invert a signal X1. In bringing the level of the control signal A to logical '0', an INV41 inverts the control signal A, the logical signal VB being the output signal goes to logical '1', i.e., the VCC level, and the logical signal VA being the output signal of an INV42 goes to logical '0', i.e., the VSS level. When the signal X1 of the circuit point 21 is at logical '1', the logical signal VA brought into the VSS is fed to the terminal 27 and the logical signal VA brought into the VCC is fed to the terminal 28, the signal X1 turns on a transistor 25, the output of an INV26 goes to logical '1' and a decode output X2 of an INV29 goes to logical '0'.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a logic circuit having a function of inverting the logic level of an output signal as necessary.

[Technical Background of the Invention 1] Fig. 3 is a circuit diagram showing the conventional configuration of one decoder of an address decoding circuit, which is a type of logic circuit used in semiconductor memories, etc., and Fig. 4 is a timing chart thereof. be. Among semiconductor memories, in particular, in the address decoding circuit of E2 PROM, in which data can be electrically programmed, the level of the decode signal when selecting a memory cell is different when reading and writing data due to its data writing method. There are some. That is, for example, the level is set to "1" when reading data, and the level is set to "0" when writing data. For this reason,
Address decoding circuits used for such applications have the following circuit features.

That is, in the decoder of FIG. 3, a depletion type (hereinafter referred to as "depression type") MOS transistor 12 as a load is inserted between the point where the positive polarity power supply voltage Vcc is applied and the circuit point 11. This Mo8 transistor 1
2 is an N-channel type, and is a MOS described below.
It is assumed that all transistors are also of N-channel type.

Roughly speaking, a plurality of enhancement type (hereinafter referred to as E type) driving MOS transistors 13 for decoding, each gate of which is supplied with a 1-bit address signal, are connected between the circuit point 11 and the ground voltage Vss application point. It has been inserted. Here, when an address signal of "1P level" is supplied to at least one gate of the drive MOS transistor 13, the signal x1 at the circuit point 11 is set to the OII level. When an "O" level address signal is supplied, the logic is established and the signal x1 at the circuit point 11 is set to 1" level.

The signal x1 at the circuit point 11 is supplied to the E/D type inverter 14, and also to another E/D type inverter 14 via the MOS transistor 15 whose gate is supplied with the control signal X.
It is supplied to a D-type inverter 16. Furthermore, the above E/
The output signal of the D-type inverter 14 is passed through the MOS transistor 17 whose gate is supplied with the control signal A.
/D type inverter 16. And above E
The signal x2 at the output terminal 18 of the /D type inverter 16 is supplied to a memory cell (not shown) as a decoded output.

By the way, in such a decoder, when the logic is established, it is necessary to set the decode output signal to the "O" level in the case of data writing, so the control signal ■ is set to the "1" level and the MOS transistor 15 is turned on. As a result, the signal X1 at the circuit point 11, which has been set to the "1" level, is supplied to the E/D type inverter 16 via this transistor 15, and is inverted by this inverter 16 to become a signal x2. This signal x2 is set to "O" level.

On the other hand, when the above logic is established, in the case of data reading, it is necessary to set the decode output signal to the "1' level, so the control signal A is set to the "1' level and the MOS transistor 17 is turned on. . As a result, the signal x1 at the circuit point 11, which is at the "1n" level, is sequentially inverted by the two E/D type inverters 14 and 16, so the signal x2 is set to the same "1" level as x1. . That is,
As a result, at the time of selection, the logic of the decode output signal x2 is reversed between data writing and data reading.

[Problems with the Background Art] In the conventional decoder shown in FIG. 3, two MOSs are switched and controlled by the control signal A or τ in order to reverse the logic level of the decoded output signal when writing and reading data. A transistor is provided. Since a memory address decoding circuit is provided with a large number of decoders having the configuration shown in FIG. 3, each decoder requires the two MOS transistors described above. E2 PR
In semiconductor memories other than OM such as mask ROM and RAM, the above two MOS transistors are not required, so E2P
The address decoding circuit in a ROM has a disadvantage in that it occupies a larger area than a mask ROM or the like.

This is true not only for address decoding circuits of semiconductor memories, but also for all logic circuits that need to invert the logic level of an output signal in response to a control signal.

[Objective of the Invention] This invention was made in consideration of the above circumstances, and its purpose is to have a function of inverting the logic level of an output signal according to a control signal, and to have a structure with a small number of elements. The purpose of this invention is to provide a logic circuit that can perform the following steps.

[Summary of the Invention] In order to achieve the above object, the logic circuit of the present invention includes a logic circuit that operates using power supplied to first and second power supply terminals and outputs a signal according to an input logic signal. In the circuit section, the logic level of the output signal from the logic circuit section is inverted by controlling the exchange of power supplies to be supplied to the first and second power supply terminals of the logic circuit section according to a control signal. ing.

[Embodiments of the Invention] Hereinafter, embodiments of a logic circuit according to the present invention will be described with reference to the drawings.

Figure 1 shows the logic circuit of this invention as well as the conventional circuit.
FIG. 2 is a circuit diagram of one decoder implemented in an address decoding circuit of a PROM. Positive polarity IIl source voltage Vc
A D-type M is connected between the c application point and the circuit point 21 as a load.
An OS transistor 22 is inserted, and the circuit point 2
A plurality of E-type driving MOS transistors 23 of decoding type, each gate of which is supplied with a 1-bit address signal, are inserted between the E-type driving MOS transistor 23 and the ground voltage Vss application point.

Further, the drain and gate of the D-type MOS transistor 24 are connected to the drain of the E-type MOS transistor 25. Both transistors 24 and 25 constitute an E/D type inverter 26, and a logic signal VA, which will be described later, is supplied as a power source to a first power supply terminal 27 to which the drain of the D type MOS transistor 24 is connected. . Further, a second power supply terminal 28 to which the source of the E-type MOS transistor 25 is connected is connected to a logic signal V, which will be described later, as a power supply.
B is supplied. Furthermore, the gate of the transistor 25 is supplied with the signal x1. The output signal of the E/D type inverter 26 is DFJ! It is supplied to an E/D type inverter 29 consisting of a MOS transistor and an E type MOS transistor, and this E/D type inverter 29
The signal @x2 at the output terminal 30 of is supplied to a memory cell (not shown) as a decode output.

The address decoding circuit of this embodiment is provided with a plurality of decoders having the above-mentioned configuration, and is also provided with a control circuit 40 that roughly generates the above-mentioned logic signals VA and VB.

This control circuit 40 has a power supply voltage Vcc and a ground voltage Vss.
, and inverts the control signal A to generate the logic signal V.
Same as the E/D type inverter 41 that outputs B<Vcc
and Vss, and an E/D type inverter 42 which inverts the logic signal VB and outputs the logic signal VA.

Note that the above-mentioned -Jllllllll signal is set to "0" level when data is written in a memory cell (not shown), and set to "1" when data is read.
The logical signals VA and VB are supplied in parallel to the first power terminal 27 and the second power terminal 28 in each of the plurality of decoders.

It is assumed that all the above-mentioned MOS transistors are of N-channel type.

Next, the operation of the circuit configured as described above will be explained using the timing chart shown in FIG. When data is to be read from a memory cell (not shown), the control signal A is set to the "1" level. At this time, in the control circuit 40, the inverter 41 inverts the control signal A, and the logic signal VB that is its output signal is set to the "OIt level, that is, Vss, and the logic signal VA that is the output signal of the inverter 42 that follows this is set to the 1" level. That is, it is set to Vcc. Now, suppose that an address signal of ``0'' level is supplied to all the gates of the MOS transistors 23 in a certain decoder, the logic is established, and the signal x1 at the circuit point 21 is set to ``1'' level. The first power supply terminal 21 of the inverter 26 to which the signals x and 7 are supplied is supplied with a logic signal VA set to Vcc, and the second power supply terminal 28 is supplied with a logic signal VB set to Vss. Therefore, this inverter 26 operates normally and inverts the signal x1.As a result, the output signal of this inverter 26 becomes 0.
This "0" level signal is inverted again by the inverter 29, so its output signal x 2
The decoded output signal is “1” at the same level as the signal @x1.
Become a rubel.

At this time, if an address signal of 1° level is supplied to at least one gate of the MOS transistor 23 and the signal x1 at the circuit point 21 is set to the 0' level, the signal x2 is also set to the OH level. .

Next, when data is written into a memory cell (not shown), the control signal A is set to the "0" level.

At this time, in the control circuit 40, the inverter 41 outputs the control signal A.
The logic signal VB, which is the output signal thereof, is set to the 1" level, that is, Vcc, and the logic signal VA, which is the output signal of the inverter 42 that follows this, is set to the "OII level, that is, Vss.

Let us now consider a case in which the address signal of the 0° level is supplied to all the gates of the MOS transistors 23 in the decoder, the logic is established, and the signal x1 at the circuit point 21 is set to the "1" level. Here, the first l source terminal 27 of the inverter 26 to which the above signal x1 is supplied has Vss.
The logic signal VA set to Vc is applied to the second power supply terminal 28.
Since the logic signal VB set to the level C is supplied, the transistor 25 is turned on by the signal x1, and the output signal of the inverter 26 is set to Vcc, that is, the "1" level. The decode output signal x 2 which is the output signal of the inverter 29 that follows is “OII
be leveled.

On the other hand, an address signal of "1" level is supplied to at least one gate of the MOS transistor 23, and the circuit point 2
When the signal x1 of 1 is set to the "0" level, the transistor 25 is turned off by the signal x1, and the output signal of the inverter 26 is set to the Vss, that is, the II OIT level. Therefore, the subsequent decode output signal x2, which is the output signal of the inverter 29, is set to the "1" level.

In this way, in this embodiment circuit as well, the level of the decode signal ×2 when selecting a memory cell is “0” when reading data.
"level", and "1" level when writing data.Moreover, the number of MOS transistors can be reduced by two in each decoder compared to the conventional method, and the control circuit 40 is common to multiple decoders. Therefore, the number of elements in the entire address decoding circuit can be significantly reduced compared to the conventional one.

Further, in the above embodiment, if the inverted signal A of the signal A is input to the inverter 41 in the control circuit 40, the inverter 29 can be omitted. At this time, the output of the inverter 26 is used as ×2. In this case, the threshold voltage of the transistor 25 is preferably OV.

It goes without saying that this invention is not limited to the above-described embodiments, and that various modifications can be made.

Further, in the above embodiment, the present invention is applied to a semiconductor memory, particularly an E2 memory.
Although the case where the present invention is implemented in a FROM address decoding circuit has been described, it goes without saying that this can be implemented in any logic circuit that needs to invert the logic level of an output signal in response to a control signal.

[Effects of the Invention] As explained above, according to the present invention, it is possible to provide a logic circuit that has a function of inverting the logic level of an output signal according to a control signal and can be configured with a small number of elements. I can do it.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, and FIG.
The figure is a timing chart thereof, FIG. 3 is a circuit diagram of a conventional circuit, and FIG. 4 is a timing chart thereof. 26, 29.41.42...E/D type inverter,
27...First power supply terminal, 28...Second power supply terminal, 4o...Control circuit. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2

Claims (3)

[Claims] (1) A logic circuit section that operates using power supplied to first and second power supply terminals and outputs a signal according to an input logic signal, and A logic circuit comprising: a control section that inverts the logic level of an output signal from the logic circuit section by mutually controlling the exchange of power supplies to be supplied to two power supply terminals. (2) The logic circuit according to claim 1, wherein the logic circuit section includes a load MOS transistor and a drive MOS transistor. (3) The control section includes a first inverting circuit to which the control signal is supplied, and a second inverting circuit to which the output signal of the first inverting circuit is supplied;
2. The logic circuit according to claim 1, wherein an output signal of the inverting circuit is supplied to the first and second power supply terminals as a power source.