JPS5913117B2 - semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory improved to further improve read speed.

A semiconductor memory is constructed using, for example, a nonvolatile semiconductor memory element having a floating gate.

This floating gate type non-volatile semiconductor memory element has a source 12 and a drain 13 made of an nf region formed on the surface of a P-type substrate 11, as shown in FIGS. 1A to 1C. Between 13 and 13,
A control gate 16 is provided through an oxide film 15 so that a channel 14 is formed. And 1
5 A floating gate 17 is embedded in this oxide film 15. FIG. 1D shows the symbol of the floating gate type nonvolatile semiconductor memory device. Floating Q type F0 configured like this
In the case of the non-volatile semiconductor memory device, the threshold voltage Vth is set to be raised by injecting electrons into the floating gate 17. In this state, the gate voltage signal applied to the normal control gate 16 Now, it must be turned on.

Further, when electrons are not injected, by applying a gate voltage signal to the control gate 15, the connection between the source 12 and the drain 13 is turned on, and the voltage is set to "1" or "1" depending on the gate voltage signal. This constitutes a memo 30 element 18 from which output information of "O" can be obtained. However, such a memory element 1
8, in order to improve the efficiency of electron injection into the floating gate 17 and to increase the current flowing through the memory element when reading data, the potential of the floating gate IT, which is an effective gate, must be adjusted. , it becomes necessary to raise the potential of the control gate 16 sufficiently. lr, , - As is clear from the figure, for this memory element,
Between the control gate 16 and the floating gate 17, the floating gate 17 in the field part and the base 1
1, and further floating gate 17 and channel 1
4, each having a capacity C1 to C3,
Control gate 16 and floating gate 1
Letting the potentials of 7 be CG and P, respectively, CG and F are expressed by the following equations.

As can be seen from this equation, in order to increase the potential of the floating gate 17, it is sufficient to increase the capacitance C compared to the capacitance C3. One way to do this is to There is a method of reducing the thickness of the insulating film, but reducing the film thickness makes it easier for electrons in the floating gate to escape, leading to reliability problems.

Another method is to make the floating gate larger. That is, the distance between the floating gate where the capacitor C2 is formed and the substrate is normally 7000λ, and the distance between the floating gate and the control gate is about 1000 people, so if you compare them on a unit area basis,
C,>C2. Therefore, if the floating gate is made larger while keeping the channel portion constant, C1 will be much larger than C, so C will become larger than the increase in C2+C3. FIG. 2 is a plan view showing the configuration of a memory device composed of the memory elements 18 as described above, and shows a plurality of row lines 19, 19, . . . extending in the horizontal direction at equal intervals. In preparation, this row line 191, 19
2... In each, a plurality of memory elements 1811
, 181, . . . are arranged.

For example, for row line 191, memory elements 1811,
18, . . . are arranged at regular intervals, and their respective gates 16 are connected and arranged in correspondence. Specifically, the gates 16 of adjacent memory elements 18, 1, 181, . . . are connected to form row lines 19. Similarly, for row line 19, memory element 18,
, 1822... are formed, in which case the opposing memory elements 181, 18, 1, 181, and 18,
, . . . have drain electrodes facing each other, and are commonly connected to the column lines 201, 202 . The source is connected to the ground line GND. That is, each memory element 1811, 18,
, . . . are determined by the floating gate 17 indicated by diagonal lines in the figure and the channel width W of the transistor.

However, in order to improve the memory density, it is required that the floating gate 17 and the channel width be made as small as possible. Therefore, the channel width W is set to the minimum size allowed to perform the transistor function, and for example, the control gate potential CG is 5V.
At present, the size of the floating gate 17 is determined so that the potential of the floating gate is about 3 when . Therefore, the conductance of the memory element, 9m, does not increase, and when CG is 5 and the drain voltage is 5V, an output current of only about 100 μA can be obtained. the result,
It takes a long time to turn on the source and drain of this memory element and discharge the column line because the column line has a large capacity and the current flowing through the memory element is small. The read speed of the memory is limited by the column line discharge time of the memory element, and about half of the data read time is spent on this discharge time. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor memory that can sufficiently improve the read speed of data stored in a memory element.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 3 shows the configuration of a semiconductor memory according to an embodiment of the present invention. In the figure, reference numeral 1 denotes a memory cell array, each having a plurality of row lines 190 to 19. and row line 2
00-? 01n is arranged in a matrix, and memory cells 1800 to 18 made of floating gate type MOS transistors as described above are arranged at each intersection thereof.
1m, 1810~181rn,... are arranged. The gates of the respective memory cells are connected to the corresponding row lines 190 to 190, the drains are connected to the corresponding row lines 200 to 20rr], and the sources are connected to ground. In a memory cell array configured as described above, one memory cell is selected and specified by specifying row lines and column lines. Let's do it.

For each of the row and column decoders 21 and 22,
Row address signal A from a CPU (not shown) or the like. -Ai and column address signal Aj-Arr], respectively, are supplied to address buffer circuits 230 to 231 and 23, to
231T1 is provided. For example, the address buffer circuit 230 includes an inverter 11 and buffer circuits B1 and B2, as shown in FIG. Signal 8 at the same logic level as . and a signal A'o of the opposite level is output. Other address buffer circuits 231 to 231n are similarly configured, and address buffer circuits 230 to 2
31 output signals A'0, A'0, A'1, 7V:, . ．．
．． 8,,λ'1 are supplied to the row decoder 21.
This row decoder 21 includes, for example, row lines 190 to 19, as shown in FIG. It is comprised of decoding circuits 210 to 210 provided correspondingly. These decoding circuits 210-21. are made up of similar circuits; for example, the decode circuit 210 is made up of a NOR circuit N1, an inverter 2, and a buffer circuit B3. The NOR circuit N1 receives eight of the output signals from the address buffer circuits 230-231. ,A'1,...A'i are input,
This signal eight. 、． /V'1...A'i are all "o"
, i.e., row address signal A. -A1 is all “0”
In this state, the output signal Q of the NOR circuit N1 becomes "1". Then, the output of the inverter 12 becomes "O", and the transistor B3l of the driver of the buffer circuit B3 turns off. Therefore, the potential of the row line 190, which is the output of the buffer circuit B3, becomes "1". That is, a signal having the same logic as the signal Q is output to the row line 190. Also, the NOR circuit N in the decoding circuit 21
The input of No. 2 to the anor circuit N1 in the decoding circuit 210 is the signal A.

The difference is that a signal A'o is input instead of . That is, row address signal A. is “1” and A1 to A
When i is "0", the column line 191 becomes "1". Thus, the row address signal A. - row lines 190-19 by changing the logic level of the signal on Ai. any one of
becomes the [1] level, and that row line becomes designated. On the other hand, the column decoder 22 is also configured similarly to the row decoder 21.

That is, depending on the logic level state of the column address signals A, ~Am, any one of the column designation lines 240~241T] is set to [1].
” Specify the column designation line as the level state. Column designation lines 240 to 24111 are connected to enhancement type transistors 250 to 25r11 forming column gate circuit 2.
connected to each gate of The sources of each of the enhancement transistors 250-25r11 are connected to one end of each of the column lines 200-20rT1. Further, the drains of these transistors 250 to 25rT1 are commonly connected at a connection node S, and this node S
is a depletion type MOS transistor 2 for load.
A power supply Vc is supplied through 6. Therefore, when any of the column designation lines 240 to 241T) is designated and any of the transistors 250 to 251n is turned on, the column line connected to that transistor is designated, and the power supply c is applied to that column line. will be connected. The logic potential level at the node S is output from the output terminal 0UT via the output circuit 27 as read information of this memory. On the other hand, each column line 200~
The other end of 20I11 is connected to the drains of enhancement type transistors 280 to 28rT1 for column line discharge. This transistor 280~28n1
The source of each is connected to ground, and the output signal D1 from the pulse control circuit 29 is supplied to each gate. This control circuit 29 receives an address signal A. ~A
A first pulse generation circuit 3 that generates a pulse when m changes.
The pulse signal P from 0 causes the signal D1 to become "
As the output signal a of the NOR circuit 31 becomes the "1" level, the signal D1 becomes the "O" level. The NOR circuit 31 has a control line R
A signal at the potential level of node Z at one end of control line B and one end of control line B is supplied.

The control line R1, like the row lines 190-190, is connected to the gates of floating gate transistors 320-32rT1. However, the drain is not connected to column lines 200-20rn and is connected to row line 190rn.
~19. It is designed to have a similar resistance value and capacitance. Moreover, the output signal from the second pulse generation circuit 33 is supplied to the other end of the control line R1. This second pulse generating circuit 33 is connected to address buffers 230 to 2.
3rr] output signal from La80,X0,...λMisaki,λ
゛.

This is the address signal A that is input. When -A[T] changes, a pulse signal is generated that brings the control line R1 to the "O" level. Also, the control line B is the column line 20
In order to make the same conditions as 0 to 20m, that is, the same capacitance and resistance value, the power supply c is connected through a depletion type transistor 34 for load and an entrainment type transistor 35 which is always on. supplying.

The capacitor 36 connects the column line 200 to 20rn.
It is designed to have a similar capacity. This control line B
One end of the node Z, which is input to the NOR circuit 31, is connected to the drain of the transistor 28m+. This transistor 28rr1+1 is a transistor for discharging the control line B, and this transistor 28rr1+1 is a transistor for discharging the control line B.
The output signal D1 from the pulse control circuit 29 is supplied to the gate of +. That is, the NOR circuit 31 is
The signal a is set to the "1-1" level in a state where both the control lines R1 and B are discharged to the "O" level. Next, a specific circuit example of the first pulse generating circuit 30 is shown in FIG.

Address signal A. is inverted by inverter 301 and supplied to inverter 302 as signal b. The output signal of the inverter 302 is transmitted through a resistor 303 and a capacitor 30.
4 and is supplied to the inverter 305 as a signal c. The output signal d of the inverter 305 is
06 gate. Also, the signal d is transmitted to the inverter 3
07 and is supplied to the gate of the transistor 308 as a signal e. The signal b is also inverted by an inverter 309 and supplied to the gate of a transistor 310 as a signal f. Furthermore, the signal f is inverted by an inverter 311 and supplied to the gate of a transistor 312 as a signal g. Transistors 306 and 312 are connected in series between power supply c and ground via depletion type transistors. Similarly, transistors 308 and 310 are connected in series between the power supply c and ground via the depletion type transistor,
The potential at the drain of transistor 308 is signal P. It is output as . In the pulse circuit 300 configured in this way, the address signal A is used as shown in FIG.

When is in the "O" state, the signals C, e, f, and PO are in the "0" state, and the signals B, d, and g are in the "1" state.
Next, address signal A. When the signal changes to "1", the signal b becomes "0", the signal f becomes "1", and the signal g becomes "O", as shown in FIG. At this time, the change in the signal c is delayed by the resistor 303 and capacitor 304. Therefore, when the signal f becomes "1" and the signal g becomes "O",
Signals D and e remain at "1" and "0", respectively. Therefore, transistors 308 and 312 are cut off and signal P is output. becomes "1". Then, after a certain time delay due to the resistor 303 and capacitor 304, the signal d becomes "0".
The signal e becomes "1". At this time, the transistor 308,
310 are both in the on state, and the signal P is output. It becomes "O". Also, address signal A. Similarly, when changes from "1" to "0", signals F and g change from "1" to "01," respectively.
Although the signals D and e change from "0" to "1", the resistor 303 and capacitor 304 keep the signals D and e in the "0" and "1" states, respectively. Therefore, transistor 306
, 310 are cut off, and the signal P is turned off. becomes "1". Furthermore, due to the resistor 303 and capacitor 304,
After a certain time delay, signals D and e become "1" and "0", respectively.
become. At this time, the transistors 306 and 312 are turned on, and the signal P is output. becomes "O". In this way, according to this pulse circuit 300, the address signal P. becomes "1". The pulse width that is “1” is the resistance 303
is determined by the capacitor 304. Although omitted in FIG. 6, such a pulse circuit generates the address signal A.
, ~Arr] changes, the same pulse signal p as above is generated.
1 to Prrl are generated. This pulse signal P. -Prn is supplied to the OR circuit 313, and the output signal of this OR circuit 313 is supplied to the first pulse generating circuit 3.
It is used as an output signal P of 0. FIG. 8 shows a specific circuit of the pulse control circuit 29, which includes a NOR circuit 291 to which the output signal P from the first pulse generation circuit 30 is input, and a NOR circuit 291 to which the output signal a of the NOR circuit 31 is input. A flip-flop 293 is formed from the NOR circuit 292 which is connected.

The output signal h of the flip-flop 293 is
94 and a buffer circuit 295, it is inverted and output as an output signal D1. In other words, this pulse control {
For wholesale circuit 29, address signal A. - When the pulse signal P becomes "1" due to a change in Arll, the signal h
becomes "O", and the signal D1 becomes "1". in this case,
The period during which the signal P is at "1" is long enough to allow the flip-flop 293 to detect the flip-flop 293.Then, when the control lines R1 and D1 are discharged and become at the "0" level, the signal P is a becomes "1" and the signal D1 becomes "0". At this time, since the pulse signal P is at the "0" level, the signal h becomes "1" and the signal D1 becomes "O".
That is, this control circuit 29 receives the address signal A. -A
A signal D that is kept at “1” level for a certain period of time when rrl changes.
This outputs 1. FIG. 9 shows a specific circuit of the second pulse generation circuit 33.

This pulse generation circuit 33 has address buffers 230 to
8 output signals from each of 23r11. A′0, A”,
A'1,...,,be. , -ArIl are inputted to pulse circuits 410 to 41rr1.

The output signals W of the pulse circuits 410 to 41rr]. -Wrn is the decoding circuit 2 shown in FIG.
The signal is input to a NOR circuit N in a decoding circuit 42 configured similarly to 10. The above pulse circuits 410 to 41
1n is composed of similar circuits, and will be explained by taking the pulse circuit 410 as an example. Signals A'0 and λ'o input to the pulse circuit 410 are supplied to the drains of transistors 43 and 44, respectively. Also signal eight. teeth,
It is inverted by an inverter 45, delayed by a resistor 46 and a capacitor 47, and supplied to an inverter 48 as a signal t. The output signal u of the inverter 48 is transmitted to the transistor 4
The signal is supplied to the gate of transistor 43, inverted by inverter 49, and supplied to the gate of transistor 43 as signal v. Then, the sources of the transistors 43 and 44 are connected in common, and the potential at the connection point is the signal W.
It is output as . In the pulse generating circuit 33 configured in this manner, the signal. If A'o is "o", the signals T and v are "1" and the signal u is "O".

Therefore, transistor 44 is cut off and transistor 43 is turned on, causing signal W. becomes "O". Even if the signal A'o changes from "O" to "1", the change does not immediately appear on the signals U and v due to the resistor 46 and capacitor 47, as shown in FIG. do not have. Therefore, the signal W. is the transistor 43
Since the signal A'o remains on, the change in the signal A'o is transmitted as is and changes to "1". Thereafter, after a certain time delay due to the resistor 46 and capacitor 47, the signals U and v become
They become "1" and "0", respectively, so that the transistor 43 is cut off and the transistor 44 is turned on. At this time, since AO is "O", the signal W is output.

becomes "o". Next, A'o changes from "1" to [O], and A'o changes from "1" to [O].
If 'o changes to ``o←``1'', the change does not appear immediately in the signals U and v due to the resistor 46 and capacitor 47, as shown in FIG. Therefore, the signal W. is the signal A since transistor 44 remains on. The change in is transmitted as is and changes to "1". Thereafter, after a certain time delay due to the resistor 46 and capacitor 47, the signals U and v become "O" and "1", respectively.
Then, the transistor 44 is cut off and the transistor 43 is turned on. Since the signal A'o is "0" at this time, the signal W. becomes "0". In this way, the pulse circuit 410 outputs the signal W for a certain period of time when the signal 8 changes. is set to "1". Further, the decoding circuit 42 receives the output signal W of the pulse circuits 410 to 41rr1.

- When WrTl is "0", the output signal x of the NOR circuit N is "1", and the inverter I inverts the signal x.
The output signal y is [0]. Therefore, the control line R1 is at the "1" level. and the output signal A' of the address buffers 230 to 231T]. A'
0, A'1A'1,...NrTlA cape changes, the output signal W of the pulse circuits 410 to 411n.
-W[T1 is “1”, so NOR circuit N
The output signal X becomes "O", and the control line R1 becomes "O" level. In this way, this second pulse generating circuit 33
In this case, address signal A. - As the AITl changes, the control line R1 is set to the "0" level for a certain period of time. Next, the overall operation of the semiconductor memory configured as described above will be explained.

In FIG. 3, address signal A. - Consider direct writing in which Arn changes. At this time, the control line R1 is "1" and the signal D1
is at the "0" level. And control line B
is charged to the "1" level similarly to the "1" level column line in the memory cell array 1. And the control line R1
The potential level of the signal D1 and the output of the NOR circuit 31 to which the signal D1 is input are "0". Now address signal A. - When Anl changes, the signal D1 becomes "1",
Transistors 280 to 28rn+ are turned on.
Therefore, column lines 200-20rT1 and control line B begin to be discharged. Then, the control line R1 begins to be discharged at the same timing as the row line is designated again. The control lines B and R1 are under the same conditions as the column lines 200 to 20n1 and the row lines 190 to 19n, respectively, so the control lines B and R1 are discharged to the "O" level because the respective columns Line 200~20rn 1 row Line 190~1
9. It can be considered that the voltage was discharged and reached the "O" level. When both control lines B and R1 become "o", the output signal a of the NOR circuit 31 becomes "1", and the pulse control circuit 29
The output signal D1 becomes "O". Normally, the control line B goes to the "0" level faster than the control line R1, so the NOR circuit 31 is in a state of waiting for the control line R1 to go to the "0" level. Then, when the signal DDl becomes "0", the transistors 280 to 28rr)+ are cut off. On the other hand, it is assumed that address signals are also supplied to the row and column decoders 21 and 22, and for example, the row line 191 and column line 211 are specified and the memory cell 1811 is selected. At this time, if electrons are not injected into the floating gate of the floating gate type transistor constituting this memory cell, the transistors 18 and 1
turns on, discharges the column line 20, and outputs a signal at level [0] via the output circuit 27. In this case, since the column line 20 has already been discharged and is at the "0" level, the output becomes the "O" level very quickly. Furthermore, when electrons are injected into the floating gate of memory cell 18, .
Even if 811 is selected, it is kept in the off state, the column line is charged by the transistor 26, and a "1" level signal is output to the output circuit 2.
7.

In this case, the column line 201 is charged by the transistor 26, but since the column line is already discharged, it is only necessary to consider charging.
If the conductance 9 m of the column line 201 is set sufficiently large, the charging speed of the column line 201 can be sufficiently increased. In other words, the data read speed becomes faster. The transistor 28
When m+1 enters the cut-off state, the control line B is charged to the "1" level, so the signal a becomes "0", and the second pulse generating circuit 33 outputs the address signal A.

- It enters a state of waiting for a change in Arrl. The control line R1 is charged to [1] after a certain period of time. This control line R1 only needs to return to "1" by the next change in the address signal. In this way, for this semiconductor memory,
Before a memory cell is selected, the column line is discharged, and further, the column line is set to a predetermined potential (for example, the output circuit 27 is set to a voltage of 0 or 1 at its input). Since the discharging operation is stopped by detecting that the column line has been discharged to a point close to 1000 Ω, there is no waste in the discharging time of the column line.

Furthermore, even if electrons are injected into the floating gate of a newly selected memory cell, this does not impede charging of that column line. Note that the transistors 280 to 28rr) in the above practical example may be provided on the node S side in FIG.

In this case row lines 190-19. If the output from the column decoder 22 is made faster than the change in the column lines 200-2,
0rr1 is the transistor 250-2 of the column gate circuit 2
5rr1 which is in the on state. Also, when generating a pulse when an address signal changes, all address signals A. -Although it may be the case that ArIl changes, the input address signal Aj of the row decoder 21
It is also possible to do this only when ~Arn changes. This is because the column lines 200-20m are connected to transistors 250-25, for example.
This is because when it is not selected by rn, it is in a cut-off state and is disconnected from the load transistor 26. Therefore, the unselected column lines have already been discharged to the "0" level and do not need to be specially discharged to switch the output signal of the column decoder 22. In addition, like the large-scale integrated circuit LSI used in recent semiconductor memories,
If the device has a power down mode, the LSI
When is not selected, each internal circuit is rendered inactive to reduce current consumption.

For devices with such a function, a pulse may be output when the device is in a non-operating state in the same way as when the address signal changes. This is because the switching signal and the address signal are often used while changing at the same time. Also,
The operation and non-operation of the pulse generation circuit may be controlled by a power-down mode switching signal. Furthermore, although floating gate transistors are used as memory cells in the above embodiments, other memory elements and circuits may be used instead. As described above, according to the present invention, it is possible to provide a semiconductor memory in which the reading speed of data stored in memory cells is further improved.

[Brief explanation of the drawing]

1A to 1D illustrate a floating gate transistor, in which FIG. 1A is a plan view, and FIGS. 1B and C are AO) b-b line and c-c line, respectively. 1D is a cross-sectional diagram showing the symbol of this transistor, FIG. 2 is a plan view showing a memory made up of the above-mentioned transistor, and FIG. 3 is an overall diagram of a semiconductor memory according to an example of the present invention. FIG. 4 and FIG. 5 are circuit diagrams of the address buffer and decoder in the semiconductor memory, FIG. 6 is a circuit diagram of the first pulse generation circuit in the semiconductor memory, and FIG. 7 is a circuit diagram of the first pulse generation circuit in the semiconductor memory. 1st
8 and 9 are circuit diagrams showing a pulse control circuit and a second pulse generation circuit in the semiconductor memory,
FIG. 10 is a timing chart illustrating the operation of the second pulse generating circuit. 1...Memory cell array, 2...Column gate circuit, 1800.~18.

Claims (1)

[Claims] 1. A row line, a row decoder that selects the row line in response to an input address signal, a memory cell driven via the row decoder and the row line, and a memory cell that receives data from the memory cell. a receiving column line and a first line for charging that column line.
A semiconductor memory comprising a transistor, means for generating a pulse signal when the address signal changes, and a second transistor whose conduction is controlled by the pulse signal to discharge the column line for a predetermined time. . 2. The semiconductor memory according to claim 1, wherein the predetermined time is a time during which the column line is discharged to a predetermined potential, and the semiconductor memory has means for detecting this potential and stopping the discharging operation. 3. The method according to claim 1 or 2, wherein the first transistor charges the column line or the memory cell holds the column line in a discharged state according to data in the memory cell. semiconductor memory.