JPS5726925A - Pulse generating circuit - Google Patents

Pulse generating circuit

Info

Publication number
JPS5726925A
JPS5726925A JP9298981A JP9298981A JPS5726925A JP S5726925 A JPS5726925 A JP S5726925A JP 9298981 A JP9298981 A JP 9298981A JP 9298981 A JP9298981 A JP 9298981A JP S5726925 A JPS5726925 A JP S5726925A
Authority
JP
Japan
Prior art keywords
input signal
inverted
generating circuit
pulse generating
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9298981A
Other languages
Japanese (ja)
Other versions
JPH0321997B2 (en
Inventor
Hiroshi Iwahashi
Masamichi Asano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP9298981A priority Critical patent/JPS5726925A/en
Publication of JPS5726925A publication Critical patent/JPS5726925A/en
Publication of JPH0321997B2 publication Critical patent/JPH0321997B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass

Abstract

PURPOSE:To decrease the number of elements and to make the response speed of an output signal to an input signal faster, by controlling the switching of 2 pairs of FETs with a delayed output of the input signal. CONSTITUTION:An inverting input signal inversion A'0 with different phase from an input signal A'0 is applied to the drain of enhancement type FETs 43, 44. The input signal A'0 is inverted and delayed at a resistor 46 and a capacitor 47, it is again inverted, it is applied to the gate of the FET44 and inverted and applied to the gate of a transistor 43. A pulse signal W0 is outputted from the connecting point of the sources of the transistors 43, 44.
JP9298981A 1981-06-18 1981-06-18 Pulse generating circuit Granted JPS5726925A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9298981A JPS5726925A (en) 1981-06-18 1981-06-18 Pulse generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9298981A JPS5726925A (en) 1981-06-18 1981-06-18 Pulse generating circuit

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP55066254A Division JPS5913117B2 (en) 1980-05-19 1980-05-19 semiconductor memory

Publications (2)

Publication Number Publication Date
JPS5726925A true JPS5726925A (en) 1982-02-13
JPH0321997B2 JPH0321997B2 (en) 1991-03-25

Family

ID=14069774

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9298981A Granted JPS5726925A (en) 1981-06-18 1981-06-18 Pulse generating circuit

Country Status (1)

Country Link
JP (1) JPS5726925A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0298212A (en) * 1988-10-05 1990-04-10 Nec Corp Clock signal generating circuit
JPH0285109U (en) * 1988-12-20 1990-07-03

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50140255A (en) * 1974-04-30 1975-11-10

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50140255A (en) * 1974-04-30 1975-11-10

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0298212A (en) * 1988-10-05 1990-04-10 Nec Corp Clock signal generating circuit
JPH0285109U (en) * 1988-12-20 1990-07-03

Also Published As

Publication number Publication date
JPH0321997B2 (en) 1991-03-25

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