JPS5834982B2 - clock driver circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock driver circuit, and more particularly to a clock driver circuit that generates complementary clock signals for driving switching elements such as transfer gates made of insulated gate field effect transistors.

The conventional clock driver circuit, as shown in Figure 1,
It includes an inverter 1 (hereinafter referred to as an inverter) that inverts the phase of a clock input signal 5, and an inverter 2 that further inverts the phase of its output 6, and outputs 6 and 7 of the inverters 1 and 2 are respectively connected to complementary clocks. These signals are transmitted to switch elements such as transfer gates in the next stage circuit.

In this circuit configuration, it is not possible to make the propagation delay time and rise and fall times of the outputs 6 and 7 equal to the input signal 5, so the switching time of the switch elements driven by the outputs 6 and 7 is as follows. It is determined by the phase of the output with a slow propagation delay time.

Furthermore, there is a drawback that the propagation delay time of the outputs 6 and 7 is affected by load fluctuations on the output side of the inverters 1 and 2.

An object of the present invention is to provide a clock driver circuit in which delay times and rise and fall times are equal between complementary output signals.

The clock driver circuit of the present invention includes inverting means for inverting the phase of an input clock signal, and non-inverting means for generating an output in phase with the input clock signal, and the outputs of the inverting means and the non-inverting means are respectively complementary clocks. The complementary clock signals are characterized in that the delay time and rise and fall times between these complementary clock signals are made equal.

The present invention will be explained below using the drawings.

FIG. 2 is a diagram for explaining the present invention in detail, and shows the input signal 5.
It includes an impark 1 which receives as an input, and a non-inverting circuit 4 consisting of a transfer gate.

The outputs 6 and 7 of the impark 1 and the transfer gate section 4 are used as complementary output signals to the input signal 5, respectively, to control and drive the next stage switch element.

If the loads on outputs 6 and 7 are equal in this X, then the insulated gate field effect transistor (
By appropriately setting the dimensions such as the channel length and channel width of the MO8) transistor (hereinafter referred to as a transistor) and the MOS transistor constituting the transfer gate 4, the propagation delay time of the outputs 6 and 7 can be adjusted with respect to the input signal 5. The finish and fall times can be made equal.

FIG. 3 is a diagram showing one embodiment of the present invention, in which imparks 2 and 3 are connected in cascade to each output of impark 1 and transfer gate 4 of the circuit shown in FIG.
In such a circuit configuration, the cascade connection circuit of inverters 1 and 2 is used as a non-inverting means, and the cascade connection circuit of a transfer gate and inverter 3 is used as a non-inverting means. It can be a reversing means.

In FIG. 3, when the output loads of each inverter 2 and 3 are equal, the dimensions of the MOS transistors of impark 2 and 3 are made equal, and the MOS transistor of impark 1 is
) By appropriately selecting the dimensions of the transistor and transfer gate, the input signal is engraved and the outputs 6, 7 are
The propagation time, rise, fall, etc. of , can be made equal.

Furthermore, since the channel lengths and channel widths of imparks 2 and 3 are equal, the propagation time difference between outputs 6 and 7 can be made equal even with respect to load fluctuations.

As described above, according to the present invention, since the delay time, rise and fall of the complementary clock output signal can be made equal, it is possible to speed up the switching time of a switch element such as a transfer gate controlled by the complementary clock output.

[Brief explanation of drawings]

Figure 1 shows an example of a conventional clock driver circuit.
FIG. 2 is a diagram showing the principle of the invention, and FIG. 3 is a diagram showing an embodiment of the invention. In the figure, 1 to 3 are inverters, 4 is a transfer gate, 5 is an input signal, and 6 and 1 are complementary output signals.

Claims (1)

[Claims] 1. A circuit configured with field effect transistors, a first inverting circuit that receives an input clock signal and outputs its inverted signal, a transfer gate circuit that receives the input clock signal and generates its in-phase signal, and a second inverting circuit cascade-connected to the first inverting circuit; and a third inverting circuit cascade-connected to the transfer gate circuit; A clock driver circuit characterized by obtaining complementary clock signals with no time difference.