JPH0457245B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit that constitutes a pulse generation circuit using MOS transistors.

[Conventional technology]

FIG. 3 shows a conventional pulse generating circuit disclosed in, for example, Japanese Patent Publication No. 58-56194. In the figure, the drains of 1 ₀ to 1 _o are commonly connected to node B,
The gates are connected to input terminals A ₀ ~A _o , respectively,
N-channel MOS with source connected to ground
Transistor 2 has its drain connected to node B, its gate connected to ground, and its source connected to the power supply.
P-channel MOS transistor connected to Vcc,
3 is an inverter whose input terminal is connected to node B and whose output terminal is connected to node C.

Next, the operation will be explained using the waveform diagram shown in FIG. When a pulse-like input signal as shown in Figure 4a is applied to the input terminal _A0 , the N-channel
MOS transistor ₁₀ is turned on and node B is discharged. Thereafter, node B is charged as shown in FIG. 4b according to a time constant determined by the load characteristics of P-channel MOS transistor 2 used as a load element. This waveform is shaped by the inverter 3, and a waveform as shown in FIG. 4c is obtained at the node C. The same operation occurs when input signals are applied to other input terminals, or when input signals are applied to a plurality of input terminals at the same time.

[Problem that the invention seeks to solve]

Since the conventional pulse generation circuit is configured as described above, in order to lengthen the pulse width output to node C, the current drive capability of the load element 2 is reduced, and in order to shorten the pulse width, it is necessary to It is necessary to increase current drive capability.

However, when the current drive capability of the load element 2 is increased in order to shorten the output pulse width, the P channel MOS transistor 2 used as the load element is always in the ON state, so in this case, as shown in Fig. 5b. As shown, the discharge of the node B by the N-channel MOS transistor is delayed, and the propagation delay time ΔT from when the input signal is input to when the output signal is output increases as shown in FIG. 5c.

Furthermore, if the pulse width of the input signal is short as shown in Figure 6a, the N-channel MOS transistor may turn OFF before node B is sufficiently discharged, and no pulse output may be obtained. 6b, c), there was a problem that it was not suitable for high-speed operation.

This invention was made to solve the above-mentioned problems, and it provides a semiconductor that constitutes a pulse generation circuit that can quickly and reliably generate an output with a short pulse width and a small delay from an input signal. The purpose is to obtain integrated circuits.

[Means for solving problems]

In the semiconductor integrated circuit according to the present invention, the feedback signal from the output terminal is connected in parallel to the first load element so that the load characteristic of the load element that determines the output pulse width can be changed by the feedback signal from the output terminal. A second load element that can control the load characteristics is provided.

[Effect]

In this invention, a second load element with a large current drive capacity, which is provided in parallel with a first load element that is always ON, receives a feedback signal from an output terminal.
Since it is turned on, output signals with short pulse widths can be generated quickly and reliably.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention, and in the figure, 1 ₀ to 1 _o and 3 are the same as in FIG. 3.
In addition, 2 is a P-channel MOS transistor as a first load element with a small current driving ability and has the same connection as P-channel MOS transistor 2 in FIG. 3. 4 has an input terminal connected to node B, and an output terminal. The delay circuit 5 connected to the node D is a first load element 2 whose drain is connected to the node B, whose gate is connected to the output terminal (node D) of the delay circuit 4, and whose source is connected to the power supply Vcc. P as a second load element with a larger current drive capacity than
It is a channel MOS transistor.

Next, the operation of the above embodiment will be explained using the waveform diagram of FIG. 2.

In steady state, node B is charged to "H" level via P channel MOS transistor 2 which is always ON, and node D is also at "H" level, so P channel MOS transistor 5 is OFF.
are doing. When a pulse-like input signal as shown in Figure _2a is applied to input terminal A0, N-channel
MOS transistor ₁₀ turns on and node B
However, since the current driving capability of the P-channel MOS transistor that pulls up node B is small, node B is rapidly discharged to the "L" level (T1 in FIG. 2b). After the delay time of the delay circuit 4, the node D becomes "L" level, and the P channel MOS transistor 5 is turned on. Since the P-channel MOS transistor 5 has a large current driving ability, the node B is charged to the "H" level in a short time (T2 in FIGS. 2b and 2d). When node B is charged to "H" level, node D becomes "L" level again, and P
The channel MOS transistor 5 is turned off and a steady state is established (T3 in FIG. 2d).

The output pulse width of this circuit is determined by the delay time of the delay circuit 4, but since the load element 5, which has a large current drive capacity, is turned on only when charging node B, even if the output pulse width is shortened, the input The propagation delay signal from the signal will not be large, and
Reliably responds to input signals with short pulse widths.

When signals are applied to other input terminals,
The same operation occurs when input signals are applied to multiple input terminals at the same time.

FIG. 7 shows another embodiment of the invention. In this embodiment, N-channel MOS transistors 1 ₀ to 1
N-channel as a switch element that connects the sources of _o in common and can be controlled by an external signal.
Connected to ground via MOS transistor 6,
The gate of N-channel MOS transistor 6 is connected to control input terminal F.

In this circuit, the control input terminal F is set to “L”.
By setting the output terminal C to the "L" level, it is possible to fix the output terminal C to the "L" level and stop the generation of pulses.

Further, FIG. 8 shows still another embodiment of the present invention. In this embodiment, the sources of P-channel MOS transistors 2 and 5 are connected to the power supply via a P-channel MOS transistor 7 as a switching element that can be controlled by an external signal, and an N-channel MOS transistor 8 is connected between node B and ground. is provided, and the gates of MOS transistors 7 and 8 are connected to a control input terminal E.

In this circuit, the control input terminal E is set to “H”.
By setting the output terminal C to the "H" level, it is possible to fix the output terminal C at the "H" level and obtain a pulse that remains "H" for a desired period.

〔Effect of the invention〕

As described above, according to the present invention, since the load characteristics of the load element that determines the output pulse width can be controlled by the feedback signal from the output terminal, a pulse generation circuit that operates at high speed and reliably can be realized. There are benefits to be gained.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a pulse generation circuit according to an embodiment of the present invention, FIG. 2 is a clock timing diagram showing signal changes in each part of FIG. 1, and FIG. 3 is a circuit diagram showing a conventional pulse generation circuit. Figure 4 is a clock timing diagram showing signal changes in each part of Figure 3.
Figure 5 is a clock timing diagram showing signal changes in each part of Figure 3 when the current drive capability of the load element 2 is increased, and Figure 6 is a clock timing diagram showing changes in the signals of each part in Figure 3 when the pulse width of the input signal is short. A clock timing diagram showing signal changes, and FIGS. 7 and 8 are both circuit diagrams of a pulse generation circuit according to another embodiment of the present invention. In the figure, 1 ₀ to 1 _o are N-channel MOS transistors, 2 and 5 are P-channel MOS transistors as the first and second load elements, 3 is an inverter, 4 is a delay circuit, and A ₀ to _{A o} are input terminals. ,F,E
is a control input terminal, C is an output terminal, 6 is an N-channel MOS transistor as a switching element,
7 and 8 are P and N channel MOS transistors as switching elements. In the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] 1. A MOS transistor whose gate is connected to an input terminal, whose drain is connected to an output terminal, and whose source is connected to ground; one end is connected to a power supply, and the other end is connected to the output terminal. a first load element connected in parallel with the first load element and controlled to turn on and off by the output of the delay circuit; The second element has a larger current drive capacity than the load element.
A semiconductor integrated circuit comprising: a load element; 2. The semiconductor integrated circuit according to claim 1, wherein the source of the MOS transistor is connected to ground via a switching element that can be controlled by an external signal. 3 One ends of the first and second load elements are connected to a power source via a switching element that can be controlled by an external signal, and a second load element that can be controlled by the external signal is connected between the output terminal and the ground. 2. The semiconductor integrated circuit according to claim 1, further comprising a switching element connected thereto.