JPH07249968A - Flip flop circuit and shift register circuit using the circuit - Google Patents

Abstract

PURPOSE:To reduce the number of elements constituting a flip flop (FF) circuit and to reduce its area by constituting the FF circuit only of a slave part of a master-slave type circuit and generating a complementary pulse synchronized with transition timing to a prescribed level of a clock signal to drive the FF circuit. CONSTITUTION:An input clock signal CLK is inputted to a 2-input NAND gate 31 in a pulse driver circuit and inputted also to an inverter 32 having a delay function. A delay inverse signal Va outputted from an inverter 32 is inputted to the other input of the NAND gate 31, which generates a reverse phase clock pulse phi2. The pulse 2 is inverted by an inverter 33 and outputted as a positive phase clock pulse phi1. The ON/OFF control of transfer gates 21, 24 in the FF circuit is executed by the pulses phi1, phi2. and after latching input data IN by the gate 21, the data are uutputted from the gate 24. Thereby the same function as the master-slave type can be obtained only by the slave part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-flop circuit and a shift register circuit using the same, and more particularly to a flip-flop circuit suitable for integrated circuit and a shift register circuit using the same.

[0002]

2. Description of the Related Art As an example of a conventional flip-flop circuit, there is a master / slave type, for example, Japanese Patent Laid-Open No. 58-168320 and Japanese Patent Laid-Open No. 1-286609.
The circuit disclosed in Japanese Patent Publication is generally used. The configuration is shown in reference to FIG.

FIG. 5A shows a main body portion of a flip-flop circuit, and FIG. 5B shows a clock driver circuit portion which generates a clock signal for driving the flip-flop circuit.

Referring to FIG. 5A, the master portion 1
The slave part 2 and the slave part 2 have basically the same structure, but are controlled by clock signals φa and φb from the clock driver circuit so that their operations are opposite to each other.

In the master portion 1, the input IN becomes the input of the inverter 12 via the transfer gate 11, and the output thereof becomes the output Va of the master portion 1 and the input of the inverter 13. This inverter 1
The output of 3 is transmitted to the input of the inverter 12 via the transfer gate 14.

The transfer gates 11 and 13 are on / off controlled complementarily by a pair of complementary signals φa and φb of the clock signal CLK.

The slave portion 2 is also provided with transfer gates 21 and 24 and inverters 22 and 23. The transfer gates 21 and 24 are also turned on / off in a complementary manner by a pair of complementary signals φa and φb of the clock signal CLK. Controlled.

In the clock driver circuit, the clock signal CLK is inverted by the inverter 25 to become the reverse phase clock φa, and the reverse phase clock is inverted by the inverter 26 to become the normal phase clock φb, so that the pair of complementary clocks φa, φb is generated.

FIG. 6 is a time chart showing the operation of the circuit of FIG. 5. When the clock signal CLK is at low level,
The master portion 1 takes in the input data IN, holds it when the clock signal CLK is at the high level, and sends the data Va to the slave portion 2. The slave portion 2 outputs the output data Va from the master portion 1 when the clock signal CLK is at high level, and holds it when the clock signal CLK becomes low level.

[0010]

Such a conventional flip-flop circuit is composed of a master part, a slave part, and a clock driver part. With higher integration, the configuration of the circuit itself that realizes flip-flop operation is changed to reduce the number of flip-flop gates.
It is required to reduce the power consumption and area of semiconductor integrated circuits.

An object of the present invention is to provide a flip-flop circuit capable of reducing power consumption and area by reducing the number of circuit components and a shift register circuit using the flip-flop circuit.

[0012]

A flip-flop circuit according to the present invention is a flip-flop circuit which performs an input latching operation in synchronization with a clock signal.
Latching the input when the pulse signals of the first and second levels are respectively at the first level and the second level, and then the latch state is maintained until the first and second pulse signals reach the first level and the second level, respectively. And a pulse generating means for detecting a transition state of the clock signal to a predetermined level and generating the first pulse and the second pulse having a complementary relationship with the first pulse. It has a feature.

A shift register circuit according to the present invention has a structure in which a plurality of flip-flop circuits having the above structure are connected in cascade.

[0014]

In the flip-flop circuit according to the present invention, the master portion of the master-slave type circuit is deleted, and instead, a pair of complementary pulse signals having a short pulse width synchronized with one level transition timing of the clock signal is generated. The flip-flop circuit of only the slave portion is driven by the pair of complementary pulse signals.

[0015]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.
(A) is a flip-flop main body, and (B) is a clock driver circuit for generating a pulse signal for driving the main body.

As shown in FIG. 1A, the flip-flop main body portion according to the present invention comprises only the slave portion of FIG. 5A, and therefore, the same portions as those of FIG. 5 are designated by the same reference numerals. Then, the transfer gates 21 and 24
Pair of complementary clock pulses φ1 and φ for controlling ON / OFF of
2 is different from the case of FIG. 5, the one generated by the clock driver circuit shown in FIG. 1B is used.

The input clock signal CLK serves as one input of the 2-input NAND gate 31 and is also applied to the inverter 32 having a delay function. The delayed inverted signal Va from the inverter 32 becomes the other input of the NAND gate 31.
The output of the NAND gate 31 has a reverse phase clock pulse φ2.
Is generated. Then, the negative phase clock pulse φ2 is inverted by the inverter 33 and the positive phase clock pulse φ
It becomes 1.

FIG. 2 is a timing chart showing the operation of the circuit of FIG. First, the operation of generating a pair of complementary clock pulses φ1 and φ2 by the clock driver circuit will be described. By inputting the conventional clock pulse CLK to the circuit of the NAND gate 31 and the delay inverter 32, the rising timing of the clock pulse CLK is detected, and a pulse equal to the delay time of the delay inverter 32 is synchronized with each rising timing. A negative polarity pulse φ2 having a width is generated by the NAND gate 31. Therefore, the positive phase pulse φ1 having the same width is generated from the inverter 33.

Since the transfer gate 21 of the input section is turned on when the clock pulse φ1 is at high level and φ2 is at low level, the input data IN is taken in during the short period. When φ1 is low level and φ2 is high level,
Since the transfer gate 21 is off and the transfer gate 24 is on, the fetched data is held and outputted to the output OUT during that period.

It is obvious that the same function can be maintained by replacing the transfer gates 21 and 24 with each other and replacing the clock pulses φ1 and φ2 with each other.

FIG. 3 shows a shift register circuit in which the circuits (R1 to Rn) shown in FIG. 1A are cascade-connected in n stages (n is an integer of 2 or more). The clock driver circuit generates a pair of complementary clock pulses .phi.1 and .phi.2 by using one circuit shown in FIG. 1B and supplies them to the latch circuits R1 to Rn in each stage in common.

FIG. 4 is an operation timing chart of the shift register circuit of FIG. 3, where V1 to Vn are the latch circuits R, respectively.
The output data of 1 to Rn are shown respectively.

[0024]

As described above, according to the flip-flop circuit of the present invention, the two-phase clock pulses φ1 and φ2 generated by the clock driver circuit are used as the original clock signal CL.
The drive pulse of the flip-flop circuit is generated by generating it for a short period in synchronization with only the rising edge (falling edge) of K. Therefore, the same function as the master-slave type is realized only by the slave without using the master-slave type. This has the effect of reducing power consumption and the area occupied by the circuit.

Particularly, in a shift register circuit formed by cascading a large number of flip-flop circuits, a very remarkable effect can be obtained because of the reduction of the master part.

[Brief description of drawings]

FIG. 1A is a diagram showing a flip-flop circuit according to an embodiment of the present invention, and FIG. 1B is a diagram showing a clock driver circuit for generating drive pulses of the circuit of FIG.

FIG. 2 is a timing chart showing the operation of the circuit of FIG.

FIG. 3 is a diagram showing a shift register circuit according to an embodiment of the present invention.

FIG. 4 is a timing chart showing the operation of the circuit of FIG.

5A is a diagram showing an example of a conventional flip-flop circuit, and FIG. 5B is a diagram showing a clock driver circuit for generating drive pulses of the circuit of FIG.

6 is a timing chart showing the operation of the circuit of FIG.

[Explanation of symbols]

 21, 24 Transfer gate 22, 23, 33 Inverter 31 NAND gate 32 Delay inverter

Claims (4)

[Claims] 1. A flip-flop circuit for latching an input in synchronization with a clock signal, wherein a first and a second pulse signal are respectively at a first level and a second level.
A latching means for latching the input at the level of 1 and then holding this latched state until the first and second pulse signals reach the first level and the second level, respectively, and a predetermined clock signal. A flip-flop circuit comprising: pulse generation means for detecting a transition state to a level and generating the first pulse and the second pulse having a complementary relationship therewith. 2. The pulse generating means detects a transition state of the clock signal to a predetermined level to generate the first pulse, and the pulse generating means inverts the first pulse to generate the second pulse. The flip-flop circuit according to claim 1, further comprising: 3. The latch means comprises a first inverter, a first transfer gate transmitting the input to the input of the first inverter, and a second inverter having the output of the first inverter as an input. And a second transfer gate for transmitting the output of the second inverter to the input of the first inverter, wherein the first transfer gate receives the first and second pulse signals respectively. The second transfer gate is turned on at the level and the second level, and the second transfer gate is turned on when the first and second pulse signals are at the second level and the first level, respectively. The flip-flop circuit according to claim 1. 4. A shift register circuit comprising a plurality of flip-flop circuits according to claim 1 or 3 connected in cascade.