JPS60142618A - Input buffer circuit - Google Patents

Abstract

PURPOSE:To eliminate the difference in delay time between an inverted and an inverted output, to improve the ability to drive a load, and to perform high- speed switching by providing a buffer of K-stage constitution to an output stage by using an MOS bipolar composite circuit which performs unsaturated operation. CONSTITUTION:An address input Ai is inputted to the level converting circuit composed of an inverter circuit 101 for level conversion which converts, for example, the input of a TTL level into the signal of a CMOS level and an inverter circuit 102 which adjusts leading edge and trailing edge characteristics. The uninverted input buffer circuit 103 consisting of PMOSM3, NMOSM7, NPNQ1 and NPNQ2 and the inverted input buffer 104 consisting of PMOSM4, NMOSM8, M9, M10, NPNQ3, and NPNQ4 generate an uninverted output signal ai and an inverted output signal -ai respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a μ buffer circuit, and particularly to an input buffer circuit suitable for high-speed semiconductor memories and the like.

[Background of the invention]

FIG. 1 shows a block diagram of a semiconductor memory.

In the figure, 10-1.10-2.10-M.

Each of 10-M+1.10-M+2.10-M1N is a manual buffer circuit, and has a non-inverting output and an inverting output for each input. 11 is a row decoder circuit, and 12 is a row driver circuit, which provides a row address to the memory cell array 15. 13 is a column decoder circuit, and 14 is a column driver circuit, which provides a column address to the memory cell array 15. In the memory cell array 15, memory cells of 2 rows and 2 columns are arranged in a matrix. Semiconductor memories are desired to have large capacity, high speed, and low power consumption, and CMOS memories are suitable for meeting the requirements for large capacity and low power consumption. However, the speed of ldcMOS memory is currently slower than that of bipolar memory, and efforts are being made to increase the speed. The speed of memory is defined by the access time, and in order to speed up the access time, in FIG. , it is necessary to make each of the output buffer circuits faster. In a high-speed memory, the speed of each circuit is from several ns to more than ten ns, and improvement in each speed leads to a large speed improvement in the memory system as a whole. In particular, improving the speed of the input buffer circuit 10 has a large effect because it not only increases the speed of the input buffer circuit 10 itself, but also contributes to increasing the speed and reducing power consumption of the subsequent decoder circuits 11 and 13.

FIG. 2 shows a conventional eight-person CMO buffer circuit.

In the figure, Ml-M5jri PMOS transistor, M
6 to MIO are NMO8) transistors, and 21 to 25
constitute a CMO8 inverter circuit, respectively. In particular, the inverter circuit 21 has a level conversion function. For example, an external low amplitude TTL signal (0.8V ~
2. OV) e Internal CMOS level Gogo (0V~5
V), the logic threshold of the inverter circuit 21 is designed to be approximately 1.5V.

Therefore, the size W/L (channel width/channel length) of NMOS M6 is usually several times larger than that of PM08Mx. Therefore, the rise time of the output of the inverter circuit 21 is slow, and the difference from the fall time becomes significantly large. The inverter circuit 22 is necessary to eliminate this difference, and by changing the size ratio of PMO8M2 and NMO8M7, the delay time of rise and fall is adjusted.

A non-inverted output signal aI for the address input signal AI is sent to the output of the inverter circuit 22 through two inverter circuits 23.
24 and take it out. Also, the address input signal A+
The inverted output signal i for the inverter circuit 22 is extracted by connecting an inverter circuit 25 to the output of the inverter circuit 22. therefore,
There is a difference Δtd between the delay times tdl and td2 corresponding to one stage of inverter between the non-inverted output signal at and the inverted output signal stone, and the operating waveform thereof is as shown in FIG. Delay time tc between both
If there is a difference Δtd between tl and td2, the memory system will operate with the slower signal. In addition, the difference in delay time between the two causes a hazard to occur in the subsequent decoder circuit,
Times W! r@ There is a fear that it will not have a negative impact on the work.

FIG. 4 shows a conventional example of a Kabatuka buffer for eight CMOs. In the figure, M1-M5 are PMO8) transistors, M6-
MIO is NMO8) transistor, 41,42.4
5 constitutes a CMOS inverter circuit. The inverter circuit 21 in FIG.
．． It is the same as 22. In this circuit, the non-inverted output signal at
Cross-connected inverter circuits 43, 44 are provided to obtain complementary outputs of the inverted output signals RI and KIMO+. The operation of the inverter circuits 43 and 44 is as follows: 1. Now, when the address input signal 11 is at a high level, the output signal of the inverter circuit 42 is at a high level.
The output signal of the inverter circuit 45 is at a low level. Therefore, NMO8M8゜PMO8M4 is turned on and NMO8M8゜PMO8M4 is turned on.
MO8M9 and PMO8M3 are turned off. As a result, the non-inverted output signal alu becomes high level and the inverted output signal t becomes low level.

Next, when the address input signal A1 is at a low level, the output signal of the inverter circuit 42 is at a low level, and the inverter circuit 45
output signal becomes high level. Therefore, NMO8M
9, PM08M3 is on, NMO8M8, PM08
M4 turns off. As a result, the non-inverted output signal al becomes low level and the inverted output signal i becomes high level. The operating waveforms of this circuit are shown in FIG. 5, and both the non-inverted output signal a1 and the inverted output signal i have a falling delay time tdl.
.

Rise delay time id2. compared to td4. td3 becomes slower, and the memory system operates using the slower signal. This circuit is different from the circuit shown in Figure 2), since there is no period when the non-inverting output signal al and the inverting/inverting output signal valve are at a high level, no hazard will occur in the subsequent decoder circuit, but it will affect the circuit operation. PMO8M3 and NMO8M
8 or PMO8M4 and NMO8M9 are simultaneously on for a period of time, so the time for the non-inverted output signal al and the inverted output signal stone to switch to high level or low level is delayed. Potential GN
Since a through current flows toward D, there is a drawback that power consumption increases.

In addition to the drawbacks mentioned above, in the conventional examples shown in FIGS. 2 and 4, the output section of the circuit is composed of a 0M08 circuit, so a common drawback is that the ratio of increase in delay time to increase in load is large. However, this drawback not only becomes an impediment to speeding up memory, but also increases address skew when there is a difference in fan-out or wiring length between multiple address buffers, and This can be a cause of malfunctions due to multiple selection of memory cells when the decoder circuit doubles or doubles.

Furthermore, when the load on the input buffer circuit becomes heavy, the rise and fall operations of its output become more gradual, but this reduces the operating speed of the decoder circuit connected to the subsequent stage.
This becomes a factor that increases power consumption.

FIG. 6 shows the rise and fall times tr of the input waveform using an example of an inverter circuit with a MOS size of W/L=10.

This figure shows the relationship between tf and delay time tpd, and the degree of dependence on the waveform of the input signal can be understood.

Figure 7 shows the relationship between input waveform rise and fall times tr and tf of the same CMOS inverter and power consumption pd.The larger the rise and fall times tr and tf are, the more PM
Since the period during which O8 and NMOS are simultaneously on becomes longer, power consumption increases.

[Purpose of the invention]

A first object of the present invention is to provide a manual buffer circuit in which the difference in delay time between a non-inverted output signal and an inverted output signal is achieved.

Still another object of the present invention is to provide a buffer circuit with a large load driving capacity and capable of high-speed switching.

[Summary of the invention]

The feature of the inventive cover sofa circuit is that a non-inverting buffer circuit and an inverting buffer circuit having a membrane structure are provided in the output stage in order to eliminate the delay time difference between the non-inverting output signal and the inverting output signal.

Furthermore, in a preferred embodiment of the present invention, in order to achieve high load drive capability and high-speed switching, the non-inverting buffer circuit and the inverting buffer circuit have non-saturation operation in which the input section is composed of a MOS transistor and the output section is composed of a bipolar transistor. MOS.

It is a bipolar composite circuit.

Further, in a preferred embodiment of the present invention, the input level conversion circuit is composed of a plurality of stages of inverter circuits, and is K-1.

[Embodiments of the invention]

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 8 is a schematic diagram of the configuration of the present invention.

In the figure, 81 is an inverter circuit for level conversion that converts, for example, an input signal at the 'I'TL level to a signal at 0MO8 level, and 82 is an inverter circuit for adjusting the rising and falling (9) characteristics. and constitutes an input level conversion circuit. 83 is a non-inverting buffer circuit, and 84 is an inverting buffer circuit. The inputs of the non-inverting buffer circuit 83 and the non-inverting buffer circuit 840 are the inverter 82.
, and generates a non-inverted output signal al and an inverted output signal η for the address input A+.

The operating waveforms of this embodiment are as shown in FIG. 9, and the delay times of the output signals al and al with respect to the input signal AI are t
d1. td2, but if the inputs of the non-inverting buffer circuit 83 and the inverting buffer circuit 84 are commonly connected to the output of the inverter circuit 82, and each is a one-stage buffer, the difference between ldl and td2 can be reduced to zero -fc , rs, can easily be made extremely small.

FIG. 10 shows a specific embodiment of the present invention. In the figure,
M1 to M4 are PMO8) transistors, M5 to MIO are N
Q1 to Q4 are NPN) transistors, and PM08Ml and NMO8NS, PMO8M2 and NMO8M6 are CMOS MOS size) transistor circuits 101 and 102, and constitute an input level conversion circuit. ．． N
PNQl and Q2 constitute a non-inverting buffer circuit 103,
PM08M4, NMO8M8, M9. MIO,NPN
Q3 and Q4 constitute an inverting buffer circuit 104. Note that the resistor R and NMO8MO constitute an input protection circuit 100, which prevents damage to the internal circuit when an excessive voltage such as a surge is applied to the input signal.

Now, the operation of the non-inverting buffer circuit 103 will be explained.

Now, when the output signal of the inverter circuit 102 switches from a low level to a high level, the pH [S M3 turns off,
Since NMO8M7 turns on, the base of NPNQ2 switches to low level, turning off NPNQ2U. On the other hand, NP
A base current is supplied from PMO8M2 to NQI, and the non-inverted output signal a switches from low level to high level.

Next, when the output signal of the inverter circuit 102 switches from high level to low level, NPNQI is turned off. On the other hand, since PMO8M3 is on and NMO8M7 (11) is off, NPNQ2 has a non-inverted output signal al.
The base current is supplied through PMO8M3 from NP
NQ2 turns on. Therefore, the non-inverted output signal al
switches from high level to low level. Thus, a non-inverted output signal at is obtained for the address input signal A+.

Next, the operation of the inversion buffer circuit 104 will be explained. Now, when the output signal of the inverter circuit 102 switches from low level to high level, PMO8M4 turns off and NMO8M
8 turns on, the base of NPNQ3 switches to low level, NPNQ3 turns off, and at the same time NMO8MIO
Also turns off. On the other hand, since NMO8M9 is turned on, NPN
Since the base current is supplied to Q4 from the inverted output signal stone through NMO8M9, NPNQ4 is turned on, and the inverted output signal i switches from high level to low level.

Next, when the output signal of the inverter circuit 102 switches from high level to low level, NMO8M8°M9 is turned off and NPNQ4 is also turned off. On the other hand, since PM08M4 is turned on, the base voltage (12) of NPNQ3 switches to high level, and NPNQ3 and NMO8MIO
turns on. Therefore, the inverted output signal layer switches from a low level to a high level. Thus, an inverted output signal i is obtained for the address input signal mermaid.

In the above operation process, the non-inverting buffer circuit 103 and the inverting buffer circuit 104 consume low power because there is no current path from the power supply potential Vcc to the ground potential GND in a steady state where the input signal is at a high level or a low level. Also, NPNQ1
~ Q4 has a non-saturated operation because the base and collector junctions are not forward biased during the switching process, and high-speed switching is possible. Furthermore, since the output section of the non-inverting buffer circuit and the inverting buffer circuit of the embodiment of the present invention is composed of bipolar transistors Q1 to Q4,
It has a high driving capacity for loads, and exhibits the ideal characteristics of low power consumption and fast switching.

FIGS. 11 and 12 show a comparison of characteristics between the CMOS inverter circuit, the non-inverting buffer circuit 103 (13) and the inverting buffer circuit 104 used in this embodiment.

In comparing the two, the MOS size of the CMOS inverter is set to W/L=10, the MO8 size of the inverting buffer circuit is similarly set to W/L=10, and the emitter size of the NPN transistor is set to Al=10 μm2. FIG. 11 shows delay time t and d characteristics with respect to load capacitance CL. The solid line (A) in the figure is a CMOS inverter circuit, and the solid line (A) is a CMOS inverter circuit.
B) shows the characteristics of the non-inverting buffer circuit 103 and the inverting buffer circuit 104 according to this embodiment.

As is clear from the figure, the bipolar output type non-inverting buffer circuit 103 and inverting buffer circuit 104 are CMO8
Capacitive load CL with delay time tpd compared to inverter circuit
It can be seen that dependence is extremely small and high-speed switching is possible.

FIG. 12 shows the characteristics of output rise and fall times tr and tf with respect to load capacitance CL. In the figure, the solid line (A) is a CMOS inverter circuit, and the solid line (B) is a non-inverting buffer circuit 103 and an inverting buffer circuit 104 according to this embodiment.
It is a characteristic of From the figure (14), it is clear that the bipolar output type non-inverting buffer circuit 103 and inverting buffer circuit 104 have extremely small load dependence of the output rise and fall times tr and tf compared to the 0M08 circuit. Based on the above description, the features of the input buffer circuit of this embodiment can be listed as follows.

(1) The delay time difference between the non-inverted output signal and the inverted output signal is small.

(2) High load driving capability, with extremely little deterioration in switching performance even under high loads.

(3) There is extremely little deterioration in the rise and fall times of the output signal even under high loads.

When an input buffer circuit with these features is adopted in a memory system, due to the high speed of the input buffer itself,
In addition to improving the access time of the memory system, it also improves the speed of the decoder circuits connected to the subsequent stage.
It also has a large ripple effect on low power consumption operation and stable operation with small address skew.

(15) The 7'cMO8 bipolar composite type non-inverting buffer circuit and inverting buffer circuit shown in the embodiments of the present invention are merely preferred circuit examples, and those skilled in the art can easily make various modifications.

For example, in FIG. 10, the gate t of NMO8MIO
"It may be connected to the collector of NPNQ4 instead of the base of NPNQ3. Also, in Figure 10, NMO8
Remove M1o and change the location of NMO8M9,
The gate of NMO8M9 is connected to the collector of NPNQ4, and the source and drain are connected to the base of NPNQ4 and PMO8M4.
They may be connected to the gates of NMO8M8, respectively.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, it is possible to obtain an input buffer circuit in which there is no delay time difference between a non-inverted output signal and an inverted output signal with respect to an input signal.

[Brief explanation of drawings]

Fig. 1 is a block configuration diagram of a semiconductor memory, Fig. 2 is a diagram showing a conventional CMO 8-person cover sofa circuit, (16) Fig. 3 is a diagram showing the operating waveforms of the circuit in Fig. 2, and Fig. 4 is a diagram showing the conventional A diagram showing the CMO 8-person cover circuit, Figure 5 is the 4th
6 is a diagram showing the delay time characteristics of the HCMOS inverter circuit, FIG. 7 is a diagram showing the power consumption characteristics of the CMOS inverter circuit, and FIG. 8 is a diagram showing the power consumption characteristics of the CMOS inverter circuit. 9 is a diagram showing the operating waveforms of the circuit in FIG. 8. FIG. 10 is a circuit diagram showing an embodiment of the present invention. FIG. 11 is a diagram showing delay time characteristics with respect to load CL. FIG. 12 is a diagram showing the rise and fall characteristics with respect to the load Cx. 83.103...Non-inverting output buffer circuit, 84°(
17) Note 10 /lNn Anq Ajian N 慄20 兄3 Zujo 4. mouth fan S mouth rattan 60 θ mu I (11S20 person i) a trt tj (xs) 爛1[23 0g 10 I5 20 manpower n tr, tflfL5) 砺B口葡'1 ﾆ10Fig. 111 Fig. 12 Fig. Ct ( P.F.)

Claims (1)

[Claims] 1. In an input buffer circuit that generates two output signals in a complementary relationship to one input signal, an input level conversion circuit and a circuit that responds to the output of the input level conversion circuit are provided. An input buffer circuit comprising: a non-inverting buffer circuit having a stage configuration; and an inverting buffer circuit having a stage configuration, which is arranged in parallel with the non-inverting buffer circuit and responds to the output of the input level conversion circuit. 2. In claim 1, the non-inverting buffer circuit and the inverting buffer circuit are MOS transistors each having an input section composed of an MO8 transistor and an output section composed of a Bibo 2 transistor;
An input buffer circuit characterized by being a bipolar composite circuit. 3. The input buffer circuit according to claim 1 or 2, wherein the input level conversion circuit is a multi-stage inverter circuit. 4. An input buffer circuit according to claim 1, characterized in that K=1.