JPH0514170A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To reduce a through-current from a power supply to ground without causing a problem such as reduction in noise margin. CONSTITUTION:The output buffer circuit consists of pre-drivers G0-G2, a P- channel MOS TR TP being a final stage TR of a power supply side and an N-channel MOS TR being a final stage TR at a ground side. A delay capacitor C1 delays the state transition from OFF to ON of the P-channel MOS TR TP. A delay capacitor C2 delays the state transition from OFF to ON of the N-channel MOS TR TN. Thus, when an output of the output buffer circuit changes from L to H state or vice versa, the event of the final stage TRs to be turned on simultaneously is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention uses a final stage transistor for switching an output to the power supply side and a final stage transistor for switching an output to the ground side to turn on the power supply side or the ground side. The present invention relates to an output buffer circuit for driving an output to an H state or an L state, and more particularly to an output buffer circuit capable of reducing a shoot-through current from a power source side to a ground side via the final stage transistor.

[0002]

2. Description of the Related Art A logic gate, which is a digital circuit that performs a binary logical operation, outputs two electrical states as a result of the logical operation.

Normally, these two electrical states that are output have two types of voltage values. That is, logical value "0"
Low voltage state (or 0V voltage state; hereinafter referred to as L state) and a High voltage state corresponding to the logical value "1".
It is in a voltage state (or power supply voltage state; hereinafter referred to as H state).

In an output buffer circuit which drives an output by a switching operation of a transistor, in order to perform an output switching operation at a higher speed, the impedance of the final stage transistor of the output buffer circuit used for switching is lowered. .

On the other hand, a final stage transistor for switching the output to the power supply side (hereinafter referred to as the power supply side final stage transistor) and a final stage transistor for switching the output to the ground side (hereinafter referred to as the ground side final stage transistor). In the output buffer circuit using the output buffer circuit, when the output of the output buffer circuit is switched from the L state to the H state or when the logic state is switched from the H state to the L state, the power source side final stage transistor It is known that a through current from the power supply to the ground is generated by turning on and the ground-side final stage transistor together.

FIG. 7 is a circuit diagram of a conventional output buffer circuit.

The output buffer circuit shown in FIG.
It is composed of pre-drivers G0 to G2, a P-channel MOS transistor TP which is a power supply side final stage transistor, and an N-channel MOS transistor TN which is a ground side final stage transistor.

This output buffer circuit inputs the signal e 2 from the internal circuit and outputs it to the pad P.

In the output buffer circuit shown in FIG. 7, when the output is switched from the H state to the L state or when the output is switched from the L state to the H state, the P channel MOS transistor TP is temporarily provided. Both the N-channel MOS transistor TN and the N-channel MOS transistor TN are turned on, which causes a through current from the power supply VDD to the ground GND.

Generally, at the moment when the output of the output buffer circuit is switched, a peak current for driving the load capacitance connected to the output of the output buffer circuit is generated.

At this time, if the impedance of the final stage transistor of the output buffer circuit is lowered to increase the speed, both the power source side final stage transistor and the ground side final stage transistor are turned on or almost turned on. The through current from the power source to the ground increases, and the peak current at this time also increases.

Further, due to the generation of such peak current,
If power supply noise or ground noise occurs in the power supply line or the ground line that supplies power to the output buffer circuit, other logic circuits that are supplied with power from the power supply line or the ground line may malfunction. There is a fear.

Therefore, conventionally, when the logical state of the output of the output buffer circuit is switched from the L state to the H state or when the logical state is switched from the H state to the L state, the final stage transistor on the power supply side and the ground are connected. There is disclosed a technique of reducing a shoot-through current from a power source to a ground due to the fact that both the side final stage transistor and the side final stage transistor are turned on or almost turned on.

For example, in Japanese Patent Laid-Open No. 61-277225,
The final-stage transistor that switches the output to the ground side is composed of multiple MOS (metal oxide semic) connected in parallel.
onductor) transistor, and the gate electrodes of the plurality of MOS transistors are sequentially connected in series by electric resistance, so that the output of the output buffer circuit becomes H
A technique is disclosed in which, when the state is switched to the L state, the plurality of ground side final stage transistors are sequentially turned on. According to the technique disclosed in Japanese Patent Laid-Open No. 61-277225, the output H of the output buffer circuit is
The peak current of the current flowing from the output of the output buffer circuit to the ground side via the ground side final stage transistor at the time of switching from the state to the L state can be reduced, and power supply noise and ground noise are also reduced. be able to.

In Japanese Patent Laid-Open No. 63-31217, in an output circuit of a semiconductor integrated circuit, a first inverter composed of a P-channel transistor and an N-channel transistor and a P-channel transistor having a common input with the first inverter are provided. And a second inverter composed of an N-channel transistor, the output of the first inverter is input to the gate of one transistor of the output stage inverter, and the output of the second inverter is connected to the other of the output stage inverter. A technique is disclosed in which the gates of the transistors are input and the turn-on timings of the other transistors are made more gradual than the turn-off timings of the other transistor. According to the technique disclosed in Japanese Patent Laid-Open No. 63-31217, it is possible to reduce the situation where both the power-side final-stage transistor and the ground-side final-stage transistor of the output buffer circuit are turned on or almost turned on. This makes it possible to reduce the shoot-through current from the power supply to the ground. Further, since the turn-on timings of the power-supply-side final-stage transistor and the ground-side final-stage transistor are gradual, the current change of the signal output from the output buffer can be gradual. As a result, the change in the current consumption of the output buffer circuit becomes gentle, and the power supply noise and the ground noise can be reduced.

In Japanese Patent Laid-Open No. 1-209813, CMOS
(Complementary metal oxide semiconductor) Between the output buffer using the transistor and the drive circuit of the output buffer, the impedance of the signal line connecting the output buffer and the drive circuit is changed according to the input signal of the output buffer. A technique of providing a means for making it disclosed is disclosed. According to the technique disclosed in Japanese Patent Laid-Open No. 1-209813, the power source side final stage transistor and the ground side final stage, which occur when the output of the output buffer circuit is switched from the H state to the L state or from the L state to the H state, It is possible to prevent the timing at which the transistor and the transistor are turned on at the same time from occurring, to eliminate the through current of the output buffer, thereby increasing the current consumption and reducing the power supply noise and ground noise.

[0017]

However, the above-mentioned JP-A-61-277225, JP-A-63-31217,
In Japanese Patent Laid-Open No. 1-209813, when the output of the output buffer circuit is switched from the H state to the L state or from the L state to the H state, the power source side final stage transistor or the ground side final stage transistor is turned from the OFF state to the ON state. The state change to (1) is delayed by using electric resistance.

That is, when the output of the output buffer circuit is switched from the H state to the L state or from the L state to the H state,
The electric signal is used to delay the signal input to the final-stage transistor that is turned on from the off state.

When the signal input to the final stage transistor is delayed by using the electric resistance as described above, the noise margin of the final stage transistor in the ON state is reduced, and malfunction due to noise occurs. There is a problem that the risk of will increase.

The above-mentioned Japanese Patent Laid-Open No. 1-209813 discloses
In response to the input signal of the output buffer circuit, the impedance (electrical resistance) of the input of the final stage transistor that turns from the OFF state to the ON state is increased. This increased impedance continues during the ON state of the final stage transistor. As a result, the noise margin of the final stage transistor that is in the ON state is reduced.

The present invention has been made to solve the above-mentioned conventional problems, and uses a final stage transistor for switching the output to the power supply side and a final stage transistor for switching the output to the ground side, and uses the power supply side. Alternatively, in the output buffer circuit that drives the output to the H state or the L state by turning it on to the ground side, the output is changed from the H state to the L state without causing a problem such as a decrease in noise margin.
It is an object of the present invention to provide an output buffer circuit capable of reducing a shoot-through current from the power supply side to the ground side via the final stage transistor, which occurs at the time of switching from the L state to the H state.

[0022]

The present invention uses a final stage transistor for switching the output to the power supply side and a final stage transistor for switching the output to the ground side.
A delay capacitor for delaying the on / off state change of the final stage transistor in an output buffer circuit that drives the output to the H state or the L state by turning on the power source side or the ground side, and the delay capacitor. A first pass transistor for switching the final stage transistor to the final stage transistor, and switching the final stage transistor from an on state to an on state by switching the first pass transistor. The object is achieved by delaying the change of state to the.

Further, in claim 1, the delay capacitor is provided for each of the final stage transistors that need to delay the state change from the OFF state to the ON state, and for each of these delay capacitors, the power source side or ground. A second pass transistor for switching to the side and initializing, and the delay not used for delaying the state change of the final stage transistor from the off state to the on state by switching the second pass transistor. By initializing the capacitor, the same problem is achieved.

Further, in claim 1, a total of two first pass transistors are provided, which switch the same delay capacitor to each of the final stage transistors that switch to the power supply side or to the ground side. The same delay capacitor delays the change in the state of each of the final stage transistors from the off state to the on state, thereby achieving the same problem.

[0025]

According to the present invention, when the output of the output buffer circuit is switched from the H state to the L state or from the L state to the H state,
In order to prevent the power-side final-stage transistor and the ground-side final-stage transistor from being turned on at the same time, the one of the final-stage transistors that changes from the off state to the on state at the time of this switching The state change is delayed.

Further, in the present invention, the delay of the state change from the off state to the on state of the final stage transistor at the time of this switching to the on state is delayed by using the delay capacitor.

The present invention also finds the configuration of the first pass transistor in order to delay the state change of the final stage transistor from the off state to the on state by using the delay capacitor.

That is, when switching the output of the output buffer circuit from the H state to the L state or from the L state to the H state,
The first pass transistor is used to connect a delay capacitor to the input side of the final-stage transistor that turns from the off state to the on state, and delays the state change of the final-stage transistor that turns from the off state to the on state to the on state. I am trying.

The connection position of the delay capacitor by the first pass transistor may be any position as long as it can delay the state change of the final stage transistor from the off state to the on state to the on state. It may be any input side, and is not limited to being directly connected to the gate of the final stage transistor.

As described above, according to the present invention, the output of the output buffer circuit is changed from the H state to the L state or from the L state to the H state.
At the time of switching to the state, it is possible to shorten the time during which both the power-supply-side final-stage transistor and the ground-side final-stage transistor are on, or prevent both of them from being on.

Further, in the final-stage transistor which is in the steady state of the ON state, the charging of the delay capacitor is completed, and there is no problem such as a decrease in noise margin as in the conventional case.

Further, for example, when the present invention is applied to an output buffer circuit of a gate array type integrated circuit, an unused cell of the gate array can be used as a delay capacitor, and the integrated circuit layout area can be effectively reduced. Not only can it be used effectively, but the efficiency of integrated circuit layout design can be improved.

[0033]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram of the first embodiment of the present invention.

In FIG. 1, the output buffer circuit arranged between the internal circuit and the pad P is a pre-driver G.
0 to G2, a P-channel MOS transistor TP1 which is a power supply side final stage transistor, and an N-channel MOS transistor TN which is a ground side final stage transistor.

Further, one electrode of the delay capacitor C1 is connected to the power supply VDD, and the other electrode is connected to the first pass transistor PT1a and the second pass transistor PT2a.

The first pass transistor PT1a switches between the delay capacitor C1 and the gate of the P-channel MOS transistor TP. The second pass transistor PT2a includes the delay capacitor and the power source V
Switch to and from DD.

One electrode of the delay capacitor C2 is connected to the ground GND. Also, this delay capacitor C
The other electrode of 2 has a first pass transistor PT1b and
It is connected to the second pass transistor PT2b.

The first pass transistor PT1b switches between the delay capacitor C2 and the gate of the N-channel MOS transistor TN. The second pass transistor PT2b switches between the delay capacitor C2 and the ground GND.

FIG. 2 is a symbol diagram of the pass transistor which is the first pass transistor and the second pass transistor used in this embodiment.

FIG. 3 is a circuit diagram of the inside of the pass transistor which is the first pass transistor and the second pass transistor used in this embodiment.

2 and 3, the control line C1
And C2 and the signal lines S1 and S2 correspond to those having the same reference numerals in FIG. 2 and FIG. 3, respectively.

The pass transistor PT shown in FIGS. 2 and 3 is turned on between the signal lines S1 and S2 when the control line C1 is in the L state and the control line C2 is in the H state.

On the other hand, the control line C1 is in the H state, and
When the control line C2 is in the L state, the signal line S1 and the signal line S2 are in the OFF state.

When the signal lines S1 and S2 of the pass transistor PT are in the ON state, the current flows from S1 to S2.
Can also flow from S2 to S1.

FIG. 4 is a time chart of signals of each part of this embodiment.

In FIG. 4, signals e 1, f 1, g
1 and h 1 are signals at the same symbols in FIG.
Further, the signals e2, f2, g2, h2 in FIG. 4 are signals at the portions indicated by the same reference numerals in the conventional output buffer circuit shown in FIG.

The operation of the output buffer circuit when the input of the output buffer circuit of this embodiment changes from the L state to the H state and the output changes from the H state to the L state will be described below with reference to the time chart of FIG. explain.

In FIG. 4, in the initial state at time t 0, the signal e1 which is also the output of the internal circuit is in the L state,
The output from the output buffer circuit of this embodiment is in the H state.

At this time t 0, the signal f 1 output by the pre-driver G0 by inputting the signal e 1 is in the H state, and the signal g 1 output by the pre-driver G1 by inputting the signal f 1 is In the L state, the signal h1 input from the signal f1 and output by the pre-driver G2 is in the L state.

At this time t 0, the P channel MOS is
The transistor TP is in the ON state and the N-channel MOS
The transistor TN is off.

After that, at time t 1, the signal e 1 which is also a signal from the internal circuit starts rising from the L state to the H state.

After that, at time t 2, the signal f 1 output from the pre-driver G0 after receiving the signal e 1 starts to change from the H state to the L state.

At time t 3, the signal f 1 is input and the signal g 1 output by the pre-driver G 1 starts to rise, and the same signal f 1 is input and the signal h 1 output by the pre-driver G 2 rises. Begins.

The signal g 1 and the signal h 1 start rising at the same time t 3, but the signal g 1 is completely in the H state at the time t 4, so that the signal h 1 is at the time t 5 It becomes a complete H state. In this way, the state transition of the signal h 1 from the L state to the H state is more gradual than that of the signal g 1 because of the action of the delay capacitor C2.

The signal g 1 is input to the gate of the P-channel MOS transistor TP, and this signal g 1 is at H level.
In this state, the P-channel MOS transistor TP1 that was in the on state is turned off. Also, the signal h 1
Is input to the gate of the N-channel MOS transistor TN, and when the signal h 1 is in the H state, the N-channel MOS transistor TN that has been in the OFF state is in the ON state.

Therefore, in this embodiment, when the signal e 1 which is also an input signal from the internal circuit is switched from the L state to the H state, the time when the signal g 1 is completely in the H state, Since the time t5 at which the signal h1 is completely in the H state is delayed, both the P-channel MOS transistor TP, which is the power source side final stage transistor, and the N channel MOS transistor TN, which is the ground side final stage transistor, are turned on. It is never in a state. Alternatively, both are turned on for a very short period.

The operation of the output buffer circuit when the input of the output buffer circuit of this embodiment changes from the H state to the L state and the output changes from the L state to the H state will be described below with reference to the time chart of FIG. explain.

First, as a steady state, at time t 10,
The signal e 1 that is also an input signal from the internal circuit is in the H state, the output of the output buffer circuit is in the L state, the P-channel MOS transistor TP which is the power supply side final stage transistor is in the OFF state, and the ground side final The N-channel MOS transistor TN, which is a stage transistor, is on.

At time t 11, the signal e 1 starts changing from the H state to the L state.

At time t12, the signal e1 input and the signal f1 output by the pre-driver G0 starts to change from the L state to the H state.

Thereafter, at time t 13, the signal f 1 is input and the signal g 1 output from the pre-driver G1 begins to change from the H state to the L state, and at the same time, the same signal f 1 is generated.
And the signal h 1 output by the pre-driver G2 starts to change from the H state to the L state.

These signals g 1 and h 1 are at H at almost the same time.
Although the state starts to change from the state to the L state, first, the signal h 1 is completely in the L state at time t 14, and thereafter, the signal g 1 is completely in the L state at time t 15. Thus, the signal g
The state transition of the signal H 1 from the H state to the L state is slower than the state transition of the signal h 1 from the H state to the L state because of the function of the delay capacitor C1 shown in FIG.

This signal g 1 is input to the gate of the P channel MOS transistor TP, and when the signal g 1 changes from the H state to the L state, the P channel MOS which has been in the OFF state.
The transistor TP is turned on.

The signal h 1 is input to the gate of the N-channel MOS transistor TN, and when the signal h 1 changes from the H state to the L state, the N-channel MOS which was in the ON state.
The transistor TN is turned off.

Therefore, in this embodiment, since the time t 15 when the signal g 1 is completely in the L state is delayed from the time t 14 when the signal h 1 is completely in the L state, the output buffer circuit When the output is in the H state, first, the N-channel MOS transistor TN which is the ground side final stage transistor is turned off, and then the P channel MOS transistor TP which is the power source side final stage transistor is turned on.

Therefore, in this embodiment, when the output of the output buffer circuit changes from the L state to the H state, neither the power source side final stage transistor nor the ground side final stage transistor is turned on. Alternatively, the period in which both are in the ON state is extremely short.

In the present embodiment, as shown in FIG. 1, when the pass transistors PT1a and PT2a are switched from off to on or from on to off, the signal g 1 input to the pass transistor PT1a is determined. It is possible to operate the pre-driver G1 faster by the delay time than the change of the logic state of.

Also, pass transistors PT1b and PT2
Also for b, the operation of switching from off to on or from on to off is performed by the pass transistor PT1b.
The predriver G2 can be operated faster than the change in the logic state of the signal h 1 input to the predriver G2.

Therefore, these pass transistors PT1a
, PT2a, PT1b, and PT2b are switched from off to on, or from on to off, even if both pass transistors PT1a and PT2a are turned on, or Even if both PT1b and pass transistor PT2b are turned on, the through current flowing through these pass transistors is extremely small.

In FIG. 4, the difference between the time chart of this embodiment and the time chart of the conventional output buffer circuit is that the state transition of the signal g 1 from the H state to the L state corresponds to the corresponding signal g 2 This is a point that is delayed compared with the state transition from the H state to the L state. In addition, the state transition of the signal h 1 from the L state to the H state is delayed compared to the corresponding state transition of the signal h 2 from the L state to the H state.

FIG. 5 is a circuit diagram of the second embodiment of the present invention.

In FIG. 5, reference numerals TP, TN, G0
~ G2, P, VDD, GND, e 1f 1, g 1, h 1
Are the same as those having the same reference numerals in FIG.

The pass transistors PT1c and PT1d shown in FIG. 5 are the same as the pass transistors described above with reference to FIGS.

In the second embodiment of the present invention shown in FIG. 5, only one delay capacitor C3 is used to switch the P-channel MOS transistor TP, which is the power source side final stage transistor, from the OFF state to the ON state. And the delay of switching the N-channel MOS transistor TN, which is the ground side final stage transistor, from the OFF state to the ON state.

In the second embodiment of the present invention shown in FIG. 5, not only the same effect as that of the first embodiment of the present invention described with reference to FIG. Can be reduced from 2 to 1, and the number of pass transistors can be reduced from 4 to 2.

FIG. 6 is a pattern diagram of an example of a cell of a gate array type semiconductor integrated circuit.

When a desired logic circuit is constructed using a gate array type semiconductor integrated circuit, normally, unused cells remain after the integrated circuit layout design.

Therefore, such an unused cell can be used for the delay capacitor of the present invention.

For example, the cell shown in FIG. 6 (basic cell)
In, the delay capacitor of the present invention can be constructed using the diffusion layer shown by the alternate long and short dash line.
It is possible to deal with it only by designing the wiring.

[0081]

As described above, according to the present invention, the final stage transistor for switching the output to the power supply side,
In the output buffer circuit that drives the output to the H state or the L state by turning on the power supply side or the ground side by using the final stage transistor that switches the output to the ground side, there is a problem such as reduction of noise margin. It is possible to reduce the shoot-through current from the power supply side to the ground side through the final-stage transistor, which occurs when the output is switched from the H state to the L state or from the L state to the H state, without causing An excellent effect can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a symbol diagram of a pass transistor used in the first and second embodiments of the present invention.

FIG. 3 is a circuit diagram of the pass transistor.

FIG. 4 is a time chart of the first embodiment.

FIG. 5 is a circuit diagram of a second embodiment of the present invention.

FIG. 6 is a pattern diagram of an example of a cell of a gate array type semiconductor integrated circuit.

FIG. 7 is a circuit diagram of a conventional output buffer circuit.

[Explanation of symbols]

C1 to C3 ... Delay capacitor, PT ... Pass transistor, PT1a to PT1d ... First pass transistor, PT2a, PT2b ... Second pass transistor, TP, TP1 ... P channel MOS transistor, TN, TN1 ... N channel MOS transistor, G0 G2 ... Pre-driver, VDD ... Power supply, GND ... Ground, C1, C2 ... Control line, S1, S2 ... Signal line, e1, e2, f1, f2, g1, g2, h1, h2 …signal.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁵ Identification code Office reference number FI Technical display location H03K 17/687 8221-5J H03K 17/687 F

Claims (3)

[Claims] 1. A final stage transistor that switches an output to a power supply side and a final stage transistor that switches an output to a ground side are turned on to a power supply side or a ground side to output an H state or An output buffer circuit driven to an L state, comprising: a delay capacitor for delaying an on / off state change of the final stage transistor; and a first pass transistor for switching the delay capacitor to the final stage transistor, An output buffer circuit, characterized in that, when switching the on / off state of the final stage transistor, the state change of the final stage transistor from the off state to the on state is delayed by switching the first pass transistor. 2. The delay capacitor according to claim 1, wherein each of the final-stage transistors that needs to delay the state change from the off state to the on state is provided, and each delay capacitor has a power supply side or a ground. A second pass transistor for switching to the side and initializing, and the delay not used for delaying the state change of the final stage transistor from the off state to the on state by switching the second pass transistor. An output buffer circuit characterized by initializing a capacitor. 3. The first delay circuit according to claim 1, wherein the same delay capacitor is switched to the power supply side or to each of the final stage transistors which are switched to the ground side.
An output buffer circuit comprising a pass transistor, wherein the same delay capacitor delays a change in state of each of the final stage transistors from an off state to an on state.