JPH01146188A - Semiconductor circuit - Google Patents

Abstract

PURPOSE:To obtain a high-speed multiinput ECL gate by clamping a common collector node having the large floating capacity of the multiinput ECL gate with a clamp transistor. CONSTITUTION:The output of buffer circuits XB0-XB5 is respectively impressed to the bases of input transistors Qc1-Qc6 of a NAND gate G0, the collectors of the transistors Qc1-Qc6 are clamped by a transistor Qc8, and the amplitude of this collector node is suppressed to be extremely small. Consequently, the increase of delay time is extraordinarily small even when the input number of the NAND gate G0 is increased. Thus, the high-speed multiinput ECL gate can be obtained.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor device, and in particular to a semiconductor circuit suitable for increasing the speed of a multi-input ECL gate, and a semiconductor circuit suitable for increasing the speed of a bipolar memory using this type of gate. This relates to a decoder circuit.

[Conventional technology]

Conventionally, as one of the decoder circuits of bipolar memory,
A circuit that combines a wired OR using an ECL gate and a NAND gate is well known (see utility model registration number r1481216J).

FIG. 11 shows an example of a conventionally used decoder circuit using ECL gates.
Three buff 77 circuits, XB, , XB, are shown.

The buffer circuit XB0 includes two transistors Q, ,Q,
, two resistors R1 and R2, a current source I, and eight emitter followers EF. XB□,X
B2 also has a similar configuration. The outputs of each emitter follower are wired-ORed in appropriate combinations for partial decoding. In the example of this figure, the buffer circuit XB,.

XB1. The output of XB is wired-ORed, and the output of
Eight partial decoded outputs of 2.X a s . . . , X2.X□.Xo are obtained. These outputs will be at a low level only when the input addresses are in a particular combination, for example, outputs Y to Y to Heel will be at a low level only when all inputs X0, Xl, and X2 are all at a high level. In Figure 11.

One input of the NAND gate Go (the base of the transistor Qc) is connected to the output Y and G.

Although not shown, an address input 9 such as X z
-X 4 and X s are also provided with buffers similar to those of XBo, etc., and are similarly partially decoded by wired OR. Among these outputs, for example, η, “
X, ,X, is applied to the base of another input of the NAND gate O (transistor QC,).

In this case, the output of the NAND gate GO is such that both its two inputs are low, i.e. all inputs X. The level becomes high only when ~X5 all reach high level. Similarly,
The outputs of the other 8×8-1=63 NAND gates also become high level only when a specific combination of inputs is applied to each one.

In the conventional example described above, the number of decoder outputs is 64, that is, a memory cell array of about 64/4 bits in both rows and columns is driven. In order to further increase the number of bits, the number of wired ORs or the number of NAND gate inputs may be increased. However, in this case, increasing the number of wired ORs not only increases the number of wired ORs, but also increases the number of emitter followers driven by one buffer circuit, so the time constant of the collector of the buffer circuit increases. increases significantly. Furthermore, increasing the number of inputs to the NAND gate slows down the collector response of the NAND gate.

[Problem that the invention seeks to solve]

In the conventional decoder circuit described above, when the number of wired ORs is large, the delay time increases accordingly;
When the number of wired ORs is reduced, the number of NAND inputs of the ECL gate that receives the wired OR output increases, and as a result, the time constant of the collector of the NAND gate becomes large, and the delay time increases. In practice, the design is made with a moderate compromise between the two, so it is difficult to increase the speed. Therefore, as a high-speed decoder, a transistor gate equipped with a pull-up circuit
20836) is also used. Generally, in this type of decoder, the amplitude of the decoder line is determined by the word line amplitude, and the amplitude is relatively large.Therefore, one effective way to speed up this type of decoder is to reduce the amplitude of the decoder line. However, when the amplitude is lowered, there are drawbacks such as the output level fluctuating significantly depending on the logical combination of address inputs, so it is difficult to further increase the speed. In addition, this type of decoder uses the wired
Compared to a decoder that combines OR and ECL gates, it is very fast, but the circuit configuration is complex and design is quite difficult, and it is difficult to reduce the wiring width because a large current flows through the decoder wire. The good news is that miniaturization is difficult.

The purpose of the present invention is to solve such conventional problems and to provide multi-input ECL without increasing delay time as the number of inputs increases.
The purpose of the present invention is to provide an ECL gate semiconductor circuit which can increase the speed of the gate, is extremely simple in design like a conventional decoder circuit using an ECL gate, and is faster than a transistor gate type.

[Means for solving problems]

In order to solve the above problems, the semiconductor circuit of the present invention includes a plurality of input transistors whose emitters and collectors are connected in common, and a reference voltage transistor whose emitters are commonly connected to the plurality of input transistors. The semiconductor circuit is characterized in that a suppressing means for suppressing potential fluctuations of the common collector is provided.

The suppressing means is characterized in that it has a transistor whose emitter is connected to a common collector of the plurality of input transistors, whose base is connected to a low impedance voltage source, and whose collector is connected to a load resistor, Another feature is that a current source is connected to the collector.

Further, the semiconductor circuit described above can be operated by applying the outputs of the plurality of buffer circuits to the bases of the plurality of input transistors.

[Effect]

In the present invention, the common collector node of the NAND gates constituting the semiconductor circuit is clamped by a transistor, and the voltage amplitude at this node becomes very small. Therefore, even if the number of NAND gate inputs (the number of input transistors, etc.) is increased, the increase in delay time is very small.Therefore, the number of NAND gate inputs is increased, and instead, the number of wired ORs using emitter followers is increased. The response of the buffer circuit and emitter follower can be made very fast by making it very small or by not using a wired-OR.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. Although an embodiment in which the present invention is applied to a decoder circuit will be described below, it goes without saying that the present invention can be applied to any logic circuit as a high-speed ECL gate.

FIG. 1 is a block diagram of a decoder circuit showing a first embodiment of the present invention.

This decoder circuit has multiple buffer circuits and multiple NAN
Consists of D gates. The buffer circuit XBO consists of two transistors Q, Q, two resistors R, R2, and two emitter followers (transistor Q3 and current source, transistor Q4 and current source [:). configured. Other buffer circuits XBI to XB5 have similar configurations, although not shown. The outputs of these buffer circuits are:

are respectively applied to the bases of the input transistors of the NAND gate GO.

NAND gate Go has six input transistors Q. □
~Qcs and a reference voltage transistor QC7. Particularly in this embodiment, the collectors of the transistors Qc to QCG are clamped by the transistor Qca, and the amplitude of this collector node is suppressed to an extremely small value of several tens of mV. The voltage amplitude of this common collector node is equal to the ECL gate current IC8.

It is determined by the ratio to the bias current flowing through transistor Q:6. In other words, the base of Qcs is connected to a constant voltage Vat.

Therefore, the potential of the common collector C is determined by voL-vBc, where the base-emitter voltage of the transistor QCs is VslE. By the way, VBIE is determined by its emitter current, and the difference ΔV between VBB when the current is 2 and □ is.

ΔV = VBE (I z) - VBE (I t) = k
It is expressed as T/qQn (I2/Iz). Here, k is the Boltzmann constant, T is the junction temperature expressed in absolute temperature, and q is the charge of the electron. At room temperature, kT
/q"F26mV. Therefore, for example, Ib"I
If it is C8, IC1i+ is the transistor Qc~QC
The emitter current of QCs when it flows through any of s is 2 = IC8 + Ib, and the current I when it does not flow through any of them.
When C = I, the voltage change at the common collector node C is as follows.

ΔV 426 Become. However, if the bias current is increased, the output high level of the NAND gate becomes lower, which may cause problems in some cases. Therefore.

For example, if Ib=(1/10)Ias.

ΔV 426
ΔV426X Qn(21) is 479 mV, but at this level, the voltage fluctuation is still sufficiently small and high-speed switching is possible. Furthermore, even if Ib=I CB/100, ΔV is 4120+sV, and a considerable increase in speed can be expected. On the other hand, when this current source is not used, when transistors Qc to Qo6 are off, the current flowing to QC@ becomes only a leak current, and the voltage fluctuation at the common collector node C is about 0.6V (of course , depending on the characteristics of the process and device), and the delay time increases considerably.

In this embodiment, the output of the NAND gate (decoder) is
The current is taken out from the collector C' of the transistor QC0 via the emitter follower transistor QC (current source IP). This output is used to drive word lines and bit line selection circuits, as will be described later. The stray capacitance of the node C' is very small because it is only that associated with the transistors QCIyQcs, the resistor R, etc., regardless of the number of inputs to the NAND gate. Therefore, the NAND gate of the decoder of the present invention can be made high-speed almost regardless of the number of inputs.
The D gate can be powered by six people, and the buffer circuit can directly drive the NAND gate without performing wired OR. In this configuration.

Since there is no delay due to wired-OR, and the NAND gate is sufficiently fast even with a large number of inputs, a very high-speed decoder circuit can be constructed as a whole. In addition,
In this figure, all the current sources of the emitter follower are placed near the emitter of the emitter follower, but by arranging them in this way.

Since it is no longer necessary to flow a large emitter follower current through the decoder lines such as X-2 . . . Further, the power supply potentials vcc' and vcC' may be set to appropriate values according to design.

FIG. 2 is a block diagram of a decoder circuit showing a second embodiment of the present invention. In this embodiment, each output of the buffer circuit drives two emitter followers and performs two wired ORs. Generally, if the number of wired ORs is about two, the increase in delay time is small, so take into account this increase in delay time and the decrease in delay time in NAND gates, etc., and adjust the number of wired ORs and the input of the NAND gate. What is necessary is to determine the optimum value of the number. In the example of FIG. 2, the input transistors are 3 of the transistors Qct*Qcz+Qcz.
The configuration of the NAND gate can be simplified. Further, the common collector node is clamped by the transistor QCs, and the voltage amplitude of the collector node is kept small. Current source Ib has a similar function to the embodiment of FIG.

FIG. 3 is a block diagram of a decoder circuit showing a third embodiment of the present invention. This is a buffer circuit.

Darlington emitter follower of NAND gate etc.
This is an example of an emitter follower. The rest of the configuration is similar to the configuration shown in FIG. 1, so please refer to the explanation of FIG. 1.

This example Darlington emitter follower is advantageous for driving heavy loads. Of course, it is not necessary that all emitter followers be Darlington emitter followers, and either one of a buffer circuit and a NAND gate may be used.

In the above embodiments, the current source of the emitter follower.

For example, the construction in Figure 1. and IF are shown as constant current sources, but instead of constant current sources, these current sources use discharge circuits that flow a large current when the emitter follower output falls to speed up the fall. You can.

As such a discharge circuit, a delay type discharge circuit that continues to flow a discharge current until the waveform falls sufficiently at the time of falling is suitable, and an example of such a discharge circuit is shown in FIG. (a) is the specification of Japanese Patent Application No. 57-221935, (b) is the specification of Japanese Patent Application No. 62-1
This is a circuit described in the specification of No. 28109. By using these circuits, the contradictory problems of high speed and low power consumption can be solved. It goes without saying that these discharge circuits may have any configuration other than that shown in FIG. 4.

As described above, in the embodiments shown in FIGS. 1 to 3, NAN
The output of the D gate is used to drive word lines and bit line selection circuits. That is, for example, it is applied to word lines W-Wn of a memory circuit consisting of a memory cell array and peripheral circuits as shown in FIG. 5, and inputs B-Bm of a bit line selection circuit.

As the discharge circuit for the word line, the circuit shown in FIG. 4 may be used, or another circuit, for example,
The discharge circuit described in Japanese Patent No. 795 may be used. Also,
As a memory cell, diode clamp type, SBD
Load resistance switching type.

Any memory cell such as a pnpn type may be used.

Note that the configuration and operation of the memory cell array and peripheral circuits shown in this figure are well known, so detailed explanations will be omitted.

FIG. 6 is a configuration diagram of a durable ECL gate showing a fourth embodiment of the present invention. In the embodiments shown in FIGS. 1 to 3, only negative outputs were output because they were applied to decoder circuits, but in this embodiment, positive outputs are also output in addition to negative outputs. Since the positive side is composed of one VBB transistor, generally the negative side is made up of transistors Qc,
It is not necessary to clamp the common collector by (of course, you can include it if necessary). Incidentally, in order to make the levels on the positive side and the negative side the same, a bias current ■5□ having the same current value as the bias current Ib□ on the negative side is subtracted from the positive side. In some cases, the current value of Ib□ may be changed to Ib□ as necessary. Also, if it is unnecessary, it may not be used.

FIG. 7 is a block diagram of a decoder circuit showing a fifth embodiment of the present invention. This shows an example in which a NAND and a latch (flip-flop) are constructed using ECL gates. Further, the buffer circuit portion is the same as that shown in FIG.

This NAND and latch circuit is of a series gate type, and the common collector of the transistors forming the multi-input gate is clamped by the transistor QCs. A signal (clock) with a phase opposite to the clock CL is applied to 1 to perform differential operation, holding the decoder output, and capturing the next decoder output. By using a reference voltage vBB-c instead of σ (or CL), the decoder output is held while the clock CL input is at a high level (σ is at a low level), and the clock CL input is at a low level (when CL is at a low level). (high level), the next decoder output may be taken in.

FIG. 8 is a block diagram of a decoder circuit showing a sixth embodiment of the present invention. This shows only the NAND and latch circuit portions in FIG. 7. In this embodiment, the collector of transistor Qa is also connected to transistor QCL.
(common collector node of ECL gates).

Similarly, the collector of transistor QA is also connected to transistor QC.
It is connected to the emitter of L'. Of course, similarly to FIG. 7, the transistor Qct,' can be omitted.

In this case, the collectors of transistors QA and QBB are directly connected to RLz without passing through transistor QCL'. It is also possible to omit the bias current source (indicated by a broken line in the figure).

FIG. 9 is a block diagram of a decoder circuit showing a seventh embodiment of the present invention. This figure, like Figure 8, also has the NAN of Figure 7.
Only D and the latch circuit portion are shown. The seventh embodiment is based on the emitter follower Ql shown in FIG. FAw QEFB
This is a current source with +rB replaced with a centralized current source. When QEFA outputs a high level, current source transistors QIAI QIB are turned on and current flows.

At this time, the emitter follower QEFB outputs a low level, but it is a current source. The rise is fast because it is discharged by . On the other hand, when Q EFA falls, the current that had been flowing to the device until then continues to flow for a short period of time, so Q
The fall of EFA is also fast. When such a current source is used, only one decoder output is always on.

IA, I. Since only one is turned on, power consumption can be significantly reduced. Note that the diode D performs a level shift and prevents saturation of Q+At QIB, and may be unnecessary depending on the design, so it can be omitted in that case.

In Fig. 10, the current source IA in Fig. 9 is of the delayed type, and the discharge current continues to flow for the required period even after the output of QEFA falls, so the falling of Q[EFA is The speed can be significantly increased compared to the case shown in the figure.

By configuring the decoder circuit described above, it is possible to incorporate logic circuit functions that conventionally existed in the periphery of a memory LSI into a memory chip, thereby increasing the speed and performance of the entire computer system, for example.

〔Effect of the invention〕

As described above, according to the present invention, a very high-speed ECL gate is provided by clamping the common collector node of a multi-input ECL gate, which has a large stray capacitance, with a clamp transistor. Also, if you configure a decoder circuit using this gate, ECL NAND
Gates are very fast even with multiple inputs, so there is no need for wired ORs for partial decoding in the buffer circuit, or the number of wired ORs can be very small, resulting in a very fast decoder circuit as a whole. can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a decoder circuit showing a first embodiment of the invention, FIG. 2 is a block diagram of a decoder circuit showing a second embodiment of the invention, and FIG. 3 is a block diagram of a decoder circuit showing a second embodiment of the invention. FIG. 4 is a diagram showing an example of a current source circuit for discharging; FIG. 5 is a diagram showing an example of a memory circuit driven by the output of the decoder circuit according to the present invention; FIG. 6 is a configuration diagram of a durable ECL gate showing a fourth embodiment of the present invention;
The figure is a configuration diagram of a decoder circuit showing a fifth embodiment of the invention, FIG. 8 is a block diagram of a decoder circuit showing a sixth embodiment of the invention, and FIG. 9 is a configuration diagram of a decoder circuit showing a sixth embodiment of the invention. 6Qcm to QCs: input transistors; FIG. 10 is a configuration diagram of a decoder circuit showing an eighth embodiment of the present invention; FIG. 11 is a configuration diagram of a conventional decoder circuit; QC? : Reference voltage transistor, Qca : Transistor to suppress common collector potential fluctuation
Ib+IC8: Current source. Figure Φ (a) Figure 6a C ER Figure 8

Claims (1)

[Claims] 1. A semiconductor circuit having a plurality of input transistors whose emitters and collectors are each commonly connected, and a reference voltage transistor whose emitters are commonly connected, A semiconductor circuit characterized in that a suppressing means for suppressing potential fluctuations of the common collector is provided. 2. The above-mentioned suppression means includes a transistor whose emitter is connected to a common collector of the plurality of input transistors, whose base is connected to a low-impedance voltage source, and whose collector is connected to a load resistor. The semiconductor circuit according to the range 1 above. 3. The inhibiting means includes a transistor whose emitter is connected to a common collector of the plurality of input transistors, whose base is connected to a low impedance voltage source, and whose collector is connected to a load resistor, and further connected to the common collector. Claim 1 characterized in that a current source is connected.
Semiconductor circuit described in section. 4. The semiconductor circuit according to claim 2 or 3, wherein the outputs of a plurality of buffer circuits are applied to the bases of the plurality of input transistors.