JPS52127051A - Waveform shaping circuit - Google Patents
Waveform shaping circuitInfo
- Publication number
- JPS52127051A JPS52127051A JP4341176A JP4341176A JPS52127051A JP S52127051 A JPS52127051 A JP S52127051A JP 4341176 A JP4341176 A JP 4341176A JP 4341176 A JP4341176 A JP 4341176A JP S52127051 A JPS52127051 A JP S52127051A
- Authority
- JP
- Japan
- Prior art keywords
- waveform shaping
- shaping circuit
- circuit
- disposition
- positive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
PURPOSE: To reduce the phase deviation in the positive and negative clock pulse outputs by properly selecting the disposition and connection for inverter circuit in the waveform shaper circuit.
COPYRIGHT: (C)1977,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4341176A JPS52127051A (en) | 1976-04-16 | 1976-04-16 | Waveform shaping circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4341176A JPS52127051A (en) | 1976-04-16 | 1976-04-16 | Waveform shaping circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS52127051A true JPS52127051A (en) | 1977-10-25 |
JPS5747855B2 JPS5747855B2 (en) | 1982-10-13 |
Family
ID=12662984
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4341176A Granted JPS52127051A (en) | 1976-04-16 | 1976-04-16 | Waveform shaping circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS52127051A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53139456A (en) * | 1977-05-11 | 1978-12-05 | Nec Corp | Clock driver circuit |
US6580302B2 (en) | 2000-07-06 | 2003-06-17 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit and layout design method thereof |
-
1976
- 1976-04-16 JP JP4341176A patent/JPS52127051A/en active Granted
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53139456A (en) * | 1977-05-11 | 1978-12-05 | Nec Corp | Clock driver circuit |
JPS5834982B2 (en) * | 1977-05-11 | 1983-07-30 | 日本電気株式会社 | clock driver circuit |
US6580302B2 (en) | 2000-07-06 | 2003-06-17 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit and layout design method thereof |
Also Published As
Publication number | Publication date |
---|---|
JPS5747855B2 (en) | 1982-10-13 |
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