JPH07169288A - Batch erasing type non-volatile memory - Google Patents

Abstract

PURPOSE:To increase operational speed and to improve using convenience by arranging required memory transistors(TR) in a matrix state at the intersection of a word line and a data line, erasing for each word line, and performing writing and reading through a latch circuit corresponding to a data line. CONSTITUTION:Memory cells of an insulation gate type FET having a structure of two layers gate are arranged at the intersection of word lines and data lines, and a memory array having memory cells of matrix arrangement is formed. And erasing operation is performed for each word line to which a control gate of a memory cell is connected. On the other hand, writing and reading operation are performed for each word line corresponding to data lines through a sense amplifier of a latch circuit used commonly as the write amplifier. Therefore, erasing, writing and reading of many bits for each word line are efficiently performed, memory access is performed at a high speed, interchangeability between a file memory and a magnetic memory device can be obtained and using convenience is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a batch erasing type non-volatile memory device (flash EEPROM;
The present invention relates to an eraseable & programmable read only memory), which is effective when used for speeding up the rewriting time.

[0002]

2. Description of the Related Art An electrical batch erasing type EEPROM is a system in which all of the memory cells formed on a chip are collectively operated, or a group of memory cells among the memory cells formed on the chip are collectively operated. It is a non-volatile memory device that has a function of erasing physically. Such a batch erase type EEPR
Regarding OM, for example, 1980 IEE, International, Solid-State
Circuits Conference (IEEE INTERNATIONAL SOL
ID-STATE CIRCUITS CONFERENCE) pages 152-153, 19
1987 IEE, International, Solid-State Circuits Conference
(IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENC
E) pages 76-77, IEE Journal
Of Solid State Circuits, Vol. 23, No. 5 (1988), pages 1157 to 1163 (IEEE, J. Solid-S
tate Cicuits, vol.23 (1988) pp.1157-1163).

FIG. 14 is a schematic diagram showing a cross-sectional structure of a memory cell of an electrically collective erasing type EEPROM which was announced at the International Electron Device Meeting in 1987. The memory cell shown in the figure has a structure very similar to that of a normal EPROM memory cell. That is, a memory cell is an insulated gate field effect transistor (hereinafter referred to as a MOS) having a two-layer gate structure.
FET or simply referred to as a transistor).

In the figure, 8 is a P-type silicon substrate, 1
1 denotes a P-type diffusion layer formed on the silicon substrate 8 and 10
Is a low-concentration N type diffusion layer formed on the silicon substrate 8, and 9 is an N type diffusion layer formed on each of the P type diffusion layer 11 and the N type diffusion layer 10. Further, 4 is a floating gate formed on the P-type silicon substrate 8 via a thin oxide film 7, 6 is a control gate formed on the floating gate 4 via the oxide film 7, 3 is a drain electrode, Reference numeral 5 is a source electrode. That is, the memory cell in the figure is composed of an N-channel type MOSFET having a two-layer gate structure, and information is stored in this transistor. Here, the information is substantially retained in the transistor as a change in threshold voltage.

Unless otherwise specified, a case where a transistor for storing information (hereinafter referred to as a storage transistor) in a memory cell is an N-channel type will be described below. The operation of writing information to the memory cell shown in FIG. 14 is the same as that of the EPROM. That is, the write operation is performed by injecting into the floating gate 4 hot carriers generated in the vicinity of the drain region 9 connected to the drain electrode 3. Due to this write operation, the threshold voltage of the memory transistor seen from the control gate 6 becomes higher than that of the memory transistor which has not performed the write operation.

On the other hand, in the erase operation, a high electric field is generated between the floating gate 4 and the source region 9 connected to the source electrode 5 by grounding the control gate 6 and applying a high voltage to the source electrode 5. Then, the electrons accumulated in the floating gate 4 are extracted to the source electrode 5 through the source region 9 by utilizing the tunnel phenomenon through the thin oxide film 7. As a result, the stored information is erased. That is, the erase operation lowers the threshold voltage of the memory transistor as viewed from the control gate 6.

In the read operation, a voltage applied to the drain electrode 3 and the control gate 6 so that weak writing to the memory cell, that is, undesired carrier injection to the floating gate 4 is not performed. Is limited to a relatively low value. For example, a low voltage of about 1 V is applied to the drain electrode 3 and a low voltage of about 5 V is applied to the control gate 6.
By detecting the magnitude of the channel current flowing through the memory transistor by these applied voltages, "0" or "1" of the information stored in the memory cell is determined.

[0008]

In the applicant of the present application, a write operation is performed by a tunnel current as a memory transistor having a control gate and a floating gate, and charges are injected into the floating gate contrary to the conventional case. By doing so, a memory transistor has been developed which performs an erase operation by making the threshold voltage higher than the selection level of the word line. In this configuration, since the threshold voltage of the erase operation for the memory transistor is set higher than the selection level of the word line, the charge of the floating gate is extracted to the substrate side as in the conventional case. Like a memory transistor that lowers the voltage, it is turned into the depletion mode by over-erasing and the word line is turned on even though it is at the non-selection level.This makes other memory cells unreadable. There is no.

However, in the case where the write operation is performed by the tunnel current, the voltage applied to the drain of the storage transistor at the time of read is made as low as possible so that the tunnel current is not generated by the read operation and erroneous writing is prevented. There is a need. Therefore, the memory cycle of the read operation from the memory transistor as described above becomes relatively slow. Therefore, the inventor of the present application can perform the erase operation in units of word lines, and accordingly, the write operation and the read operation are also performed in units of word lines, so that memory access per unit data is performed. I thought about speeding up and improving usability.

An object of the present invention is to provide a batch erasing type non-volatile memory device which is easy to use while achieving high speed operation. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, due to the relative potential relationship between the control gate and the substrate, charges are injected from the substrate side to the floating gate through the tunnel insulating film to perform an erase operation, and the relative potential between the control gate and the drain is compared. Depending on the relationship, memory transistors are formed by arranging memory transistors, which perform a write operation by discharging charges from the floating gate to the drain side through the tunnel insulating film, in a matrix at the intersections of the word lines and the data lines. A latch circuit is provided corresponding to the data line, and an erase operation is performed in units of word lines to which the control gates are coupled, and a write operation and a read operation are performed in units of word lines via the latch circuits.

[0012]

According to the above-mentioned means, data consisting of a large number of bits can be efficiently rewritten on a word line basis, so that memory access per unit data can be speeded up and compatibility with a magnetic memory device as a file memory can be achieved. It is possible to improve the usability.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a conceptual diagram of an embodiment for explaining an erase operation in a batch erase type nonvolatile memory device according to the present invention. A memory cell bias is shown in FIG. 9A, a memory array circuit is shown in FIG. 9B, and an address space is shown in FIG.

In (A), the memory MOSFET has a stacked gate structure similar to the above. However, the gate insulating film between the floating gate and the semiconductor substrate is
It is composed of a thin oxide film that allows a tunnel current to flow.
In the erase operation, + Vg is applied to the control gate and -Vw is applied to the substrate. As a result, a high electric field in which a tunnel current flows is generated between the substrate and the floating gate, and electrons are injected from the substrate side toward the floating gate. As a result, the memory M
The OSFET is turned off with respect to the selected level of the word line in the erased state. When deleting, the source
Although not particularly limited, a voltage −Vw is applied to the drain, but the erase operation itself is performed by a bias between the gate and the substrate.

In the memory array circuit of (B), a plurality of storage MOSFETs are made into one block and the drain and the source are made common. Between the common drain of the memory MOSFET and the data line, select MO is respectively provided.
An SFET is provided. At the time of erasing, the source line and the data line are shared with the substrate potential −Vw. At this time, select M
Since the gate voltage of the OSFET is 0V, it is turned on, and the common drain and source in the block both have the above voltage −
It becomes Vw. The control gate of the storage MOSFET is connected to the word line. The select MOSFET is selected by a select line extending in parallel with the word line, and this select line can be called a main word line.

In the erase operation, the substrate We
A negative voltage such as -Vw (-4V) is applied to ll, and a selection voltage + Vg such as + 12V is supplied to the word line. As a result, the batch erase operation is performed in units of word lines. In this embodiment, one word line is a storage unit such as one sector. One sector is not particularly limited, but is 51
It consists of 2 bytes. That is, one word line (not physically one) has 512 × 8
= About 4K memory cells are connected. In this case, if eight memory arrays are provided, 512 memory transistors are assigned to one word line, so that word line selection is possible even if a word driver having a relatively small current driving capability is used. The operation can be performed at high speed.

In (C), the word line selection signal is handled as a sector address in the memory space. In other words, 0 in memory space corresponds to the address of the word line.
The sectors from 1 to n are assigned, and the erase operation is performed in units of such sectors. That is, in this embodiment, the X address corresponding to the word line is input as the sector address.

FIG. 2 is a conceptual diagram of an embodiment for explaining the write operation in the batch erase type nonvolatile memory device according to the present invention. A memory cell bias is shown in FIG. 9A, a memory array circuit is shown in FIG. 9B, and an address space is shown in FIG.

In (A), during the write operation,
-Vg (-9.5V) is applied to the control gate, and + Vd (4.5V) is applied to the drain. As a result, a high electric field that causes a tunnel current to flow between the floating gate and the drain is generated, and electrons are emitted from the floating gate toward the drain. The non-selected word line is set to VCC (+ 3V), and the storage MOSF to which the drain voltage + Vd as described above is applied.
In ET, a write operation is not performed because no substantial tunnel current is generated. As a result, the threshold voltage of the written memory MOSFET is lowered and the memory MOSFET is turned on with respect to the selected level of the word line. During this write operation, the source is opened.

In the memory array circuit of (B), a common drain side select MOSF of the storage MOSFETs.
ET is turned on by applying a high level (“H”) to the gate during a write operation. As a result, the drain of the storage transistor is connected to the data line. The source-side selection MOSFET is turned off by applying a low level (“L”) to the gate during a write operation. Therefore, memory M
The common source of the OSFET is opened. And, as shown by way of example as a representative,
The data line is + V corresponding to "1" and "0" of the write signal.
When set to d / 0V, the threshold voltage of the storage MOSFET is selectively changed.

In the figure, + Vd / 0V is applied to one storage MOSFET, but in reality, write signals are transmitted to all the data lines, and the selected state is set. The write operation is simultaneously performed on all the storage transistors connected to the selected word line. In this embodiment, a tunnel current is used for the write operation. As a result, since the tunnel current flowing through the memory transistor is very small, it is possible to write about 4K bits at once as described above.

Here, in the case of a writing method in which hot electrons are generated in the vicinity of the drain to inject charges into the floating gate like a conventional memory transistor, an erase operation is performed by a tunnel current in units of word lines, for example. Even in this case, the current flowing through the memory transistor during the write operation becomes enormous, so it is impossible to write a large amount of data all at once as in the present invention. Should be.

In (C), since the selection signal of the word line is handled as the sector address in the memory space, sectors 0 to n are allocated in the memory space corresponding to the address of the word line. The write operation is performed in sector units. As a preparation for the write operation to the storage transistor for one sector, write data is serially input to the register. When data for one sector is input, the write data held in the register is transmitted to each of the data lines, and the data is simultaneously written to the storage transistors connected to the selected word line.

As described above, by dividing the memory cell into blocks and applying the ground potential of the data line or the circuit to each of them through the selection MOSFET, the stress to the non-selected memory cells can be reduced. That is, the word line is set to the non-selected state and the data line is set to the selected state to prevent the write voltage from being applied to the memory cell that should hold the data in the write operation. With this configuration, the above-mentioned stress is only applied to a small number of memory cells in the block.

FIG. 3 is a conceptual diagram of an embodiment for explaining the read operation in the batch erase type nonvolatile memory device according to the present invention. A memory array circuit is shown in FIG. 7B, and an address space is shown in FIG. The bias of the memory cell is omitted because it is easier to understand than that in (B).

A high level such as VCC (+ 3V) is applied to the selected word line. A low level such as 0V is applied to the unselected word lines. Then, as shown as a representative in the data line, + Vrd (+
It is precharged to a bias voltage such as 1V). If the memory transistor is in the erased state, the word line selection level V
Since the threshold voltage is raised with respect to CC, it is turned off, and the potential of the data line remains + Vrd. On the other hand, if the write operation as described above is performed and the threshold voltage is lower than the selection level VCC of the word line, it is turned on and the precharge voltage Vrd of the data line is discharged. In this way, the potential of the data line is set to the high level and the low level and read according to the stored information of the storage transistor.

In the figure, + Vrd is applied to one storage MOSFET, but in reality, the precharge voltage + Vrd is applied to all the data lines, and the selected state is set. The read operation is simultaneously performed from all the storage transistors connected to the selected word line.

In (C), since the selection signal of the word line is treated as a sector address in the memory space, sectors 0 to n are allocated in the memory space corresponding to the address of the word line. The read operation is performed in the sector unit. In such a read operation to the memory transistor for one sector, the read data from the memory transistor is sensed and latched in parallel by the register as the first step.
As the second stage, the read data held in the register is serially output.

FIG. 4 is a conceptual diagram for explaining the operation of the collective erase type nonvolatile memory device according to the present invention. In the same figure, in order to facilitate understanding of the present invention, it is shown in comparison with a conventional flash memory rewriting method. That is, FIG. 1A shows a conventional flash memory rewriting method, and FIG. 1B shows a flash memory rewriting method according to the present invention.

In the case where the erase operation is performed in block units across a plurality of sectors as in (A), 1
When changing the storage data of only the sector, the storage data of all the above blocks are read out and the RAM (random
It is saved in another storage area such as access memory).

Next, on the flash memory side, the erasing operation is performed in block units, and in the separate storage area, data is rewritten to the sector to be changed. And
By rewriting all the data in the separate storage area to the flash memory, the data rewriting is completed.

In the rewriting method as described above, even if there is only one sector to be changed, the operation of saving the data of all the sectors of the block to be erased to the RAM etc. one by one, the erasing operation in the unit of block, and the separate storage It takes a long time to read and write n sectors, such as changing data in the area and writing from the separate storage area to the plus memory. Then, even in the sector where the data does not need to be changed, erasing and writing are performed,
The number of times of rewriting increases, which shortens the life of the flash memory.

In the case where data can be erased in sector units as shown in (B), only the sector to be changed is erased, and then the data for one sector is written to complete the above rewriting. To do. With this configuration, the rewriting time can be greatly reduced to about 1 / 2n when one block in (A) above has n sectors.
It is assumed that the read and write times for one sector are the same, and the erase time is ignored.

FIG. 5 is a schematic block diagram of one embodiment of the batch erase type nonvolatile memory device according to the present invention. Each circuit block in the figure is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

The row address (sector address) is input to the row (X) address buffer. The address signal taken into the row address buffer is decoded by the row decoder to form a selection signal for one word line. As described above, the row decoder uses the selection MOSF in each of the write operation, the erase operation, and the read operation.
Since the potential of the main word line connected to the gate of ET and the word line connected to the control gate of the storage transistor are different, the selection / non-selection level of the voltage corresponding to each operation mode is output. It has an output circuit.

In the memory array, storage transistors are provided at the intersections of the word lines and the data lines, as described above. However, as described above, the data line is connected to the drains of the plurality of storage transistors via the selection MOSFET.
Similarly, the sources of the storage transistors forming these one blocks are connected to the circuit ground potential via the selection MOSFET.

The data line is connected to the sense amplifier.
This sense amplifier has a function of reading out and sensing the high level and the low level of the data line and latching the same. This sense amplifier is
It is the same as the register. Although not particularly limited, as the sense amplifier, a circuit similar to a CMOS sense amplifier used in a known dynamic RAM is used. That is, the sense amplifier is composed of a pair of CMOS inverter circuits whose inputs and outputs are cross-connected to each other, and a power switch which supplies an operating voltage and a ground voltage of the circuit to a plurality of CMOS inverter circuits.

The sense amplifier is also used as a register for holding write data. That is, it is connected to the input / output line via the column switch circuit, and in the read operation, the one selected by the column switch is serially transmitted to the I / O (input / output) buffer via the input / output line. It is output from the input / output terminal I / O. At the time of write operation, write data serially input from the input / output terminal is transmitted to the input / output line through the I / O buffer and taken into the sense amplifier as a latch circuit corresponding to the data line through the column switch, and all When the data acquisition is completed, it is transmitted to the corresponding data lines all at once, and the write operation is performed.

The column switch connects the input / output node of the sense amplifier to the input / output line according to the selection signal formed by the column decoder. The column decoder decodes the count output formed by the counter that counts the serial clock,
The selection signal of the column switch is formed. This counter can be regarded as a column (Y) address generation circuit.
The serially input write data is input in synchronization with the serial clock, and the serially output read data is output in synchronization with the serial clock.

The I / O terminal is used not only for inputting and outputting data, but also as an input terminal for a command designating an operation mode. The command input from the I / O terminal is decoded by the operation control logic, and the timing signal and potential setting necessary for the specified operation are performed. In the figure, the control input terminal and the control circuit for receiving it are omitted.

When erasing, writing and reading are performed in units of one word line as one sector as in this embodiment, the HDC (hard disk controller) is used.
It becomes easy to control with a normal mass storage controller like this, and the construction of the memory system becomes easy. Then, compatibility with a file memory such as a hard disk memory can be obtained, and replacement with that becomes easy. In this case, by providing a plurality of memory arrays such as eight, allocating the same sector address with each memory mat as one memory mat, and providing corresponding input / output lines and I / O buffers, Input / output is possible in units of multiple bits such as bytes.

FIG. 6 is a schematic block diagram of another embodiment of the batch erase type nonvolatile memory device according to the present invention. In this embodiment, a management byte is stored in one memory array in addition to data storage data. That is, in the memory array, the storage area of one sector designated by one word line is
The normal data and the management byte are physically connected at the same address and integrally configured.

The management byte is not particularly limited, but EC
It is used as a redundant bit for C (error detection and correction), the number of times of sector rewriting, an address pointer, and the like. The address pointer is used to create a list structure that determines the reading order of data over consecutive sectors.

A controller for setting the management byte start address in the counter is provided in order to allow only the management byte to be read and written. In addition, in order to use the function of inputting an initial value to the counter in this way, serial access of the data for one sector can be serially accessed from any bit. Are provided and input to the column address buffer. The address fetched in this column address buffer is input to the counter as the start address.

The selective addressing in one sector as described above can be used for the write operation as well as the read operation. Here, the important point is that the write operation is performed via the sense amplifier. That is, prior to the write operation, the read operation is instructed and the data for one sector is taken into the sense amplifier. After that, when the management byte start address or start address is loaded to the counter and serial data is input, the data input from the I / O terminal is written to the sense amplifier corresponding to the selected data line, Partial data replacement is possible.

If the data stored in the sense amplifier is written by performing the erase operation in units of word lines after the read operation, only the management byte of one sector or one sector of It is possible to rewrite including the management byte from the middle of. In this case, the memory array of the normal data part is composed of eight memory mats, and the management byte part is also composed of one memory mat, so that input / output to / from the external terminal can be performed in units of one byte.

FIG. 7 is a timing chart for explaining an example of the operation of the batch erase type nonvolatile memory device according to the present invention. A normal serial read mode is shown in FIG. 9A, and a management byte / head address designation mode is shown in FIG.

As shown in (A), in the normal serial read mode, the low level of the chip enable signal / CE (where / represents a bar meaning that the low level is an active level, the same applies hereinafter). Causes the chip to be selected and the write enable signal / W
E fetches the sector address at the first falling timing. Then, the first half of the command input from the input / output terminal I / O is fetched at the rising timing of the signal / WE, and input from the input / output terminal I / O at the timing when the signal / WE is set to low level and rises to high level again. Capture the latter half of the executed command.

When the serially input command is decoded and the read mode is determined, the operation of selecting the main word line and the word line according to the voltage level corresponding to the read mode is performed. Then, the stored information of the memory cell connected to the selected word line is amplified and held by the sense amplifier.

The counter performs a counting operation in synchronization with the serial clock SC, generates a column address, and sequentially holds the held data for one sector taken into the sense amplifier as D0, D1, D2. I / O terminal I
Output from / O. In this way, all data for one sector can be sequentially output. However, when only data from Dn in one sector is required, the time n × tSC required for serial output from D0 to Dn−1 becomes a dead time.

FIG. 9B shows a timing chart when serially outputting from the arbitrary n-th data Dn of one sector. Similarly to the above, the chip is selected by the low level of the chip enable signal / CE,
The sector address is fetched at the first falling timing of the write enable signal / WE. And the above signal /
The first half of the command input from the input / output terminal I / O is fetched at the rising timing of WE. Above signal / WE
The sector start address (n) is taken in from the address terminal at the timing when the
The latter half of the command input from the input / output terminal I / O is fetched at the timing when WE rises to the high level again.

When the serially input command is decoded and the read mode is determined, the operation of selecting the main word line and the word line according to the voltage level corresponding to the read mode is performed. Then, the stored information of the memory cell connected to the selected word line is amplified and held by the sense amplifier.

The counter starts the sector start address n
Is set, the nth data Dn, Dn + 1, Dn + 2, Dn + of one sector taken in by the sense amplifier in synchronization with the serial clock SC is set.
Output from the input / output terminal I / O is sequentially made like 3 ... In this way, of all the data for one sector, only the data from the arbitrary n-th byte can be read at high speed.

In this configuration, the sector address and the start address in the sector can be input in time series from the same address terminal, so that the number of address terminals and the address buffer can be made common. The management byte can be read by inputting the start address in the sector as described above.
However, since the column address in which the management byte is stored is fixedly determined in advance, the start address of the management byte is stored internally as in the embodiment of FIG. It becomes easy to set the start address of the management byte in the counter.

FIG. 8 shows a schematic block diagram of another embodiment of the batch erasing type nonvolatile memory device according to the present invention. A random access mode is shown in FIG. 9A, and a serial access mode of the embodiment is shown in comparison in FIG.

In the embodiment of FIG. 9A, the read mode and the write mode are random access. Therefore, if a column address buffer is newly provided and the memory array has 2 ^m columns (the number of data lines is 2 ^m ), a column address consisting of m bits is input. The m-bit column address fetched in the column address buffer is input to the column decoder instead of the counter as described above. The column decoder forms a selection signal for the column switch and performs write and read operations in units of 1 byte, for example.

Even in this configuration, since the erase operation is performed in word line units as described above, the data for one sector is stored in the RAM or the like except when all the data for one sector is rewritten. After evacuating to, delete it. Then, the saved data is sequentially written again to the original column address.
In the case of a write operation, one sense of data is sequentially stored in a sense amplifier that acts as a write amplifier,
It is also possible to write data for one sector at a time. In this configuration, ^{assuming that} there are 2 ⁿ word lines, n + m address pins are used.

When the erase, write and read operations are limited to the serial access in the unit of security (word line) as shown in (B), n address pins are formed in the same memory array configuration. Row address,
The number can be reduced to n + 1 consisting of one serial clock. The batch erasing non-volatile memory device is advantageous in compatibility with a magnetic memory device such as a hard disk memory, and is advantageous in replacement as a characteristic. Therefore, even if the access is limited to the sector unit as described above, the usability becomes poor. Since the number of address terminals can be reduced to about half, the size of the package can be reduced and the number of external wirings for mounting can be reduced.

FIG. 9 is a conceptual diagram for explaining the read operation of the batch erase type nonvolatile memory device according to the present invention. In this embodiment, the memory array is divided into left and right parts with the sense amplifier as the center. Then, the reference voltage applied to the data line of the non-selected memory array is used as the reference voltage of the sense amplifier having the CMOS latch structure as described above.

In the flash memory of this embodiment,
Storage MOS corresponding to the selected word line as shown in FIG.
1 sector data from FET and n as management data
A first-stage read operation (referred to as 1st access) in which the byte data is sensed by the sense amplifier array and is amplified and latched is performed. That is, signal /
The time from the rise of WE to the start of serial output is defined as the 1st access time.

As shown in (B), the data held in the sense amplifier array is synchronized with the serial clock, and the input / output terminal I / O is passed through the common I / O line and the main sense.
Is the serial access time. With this configuration, when outputting data for one sector serially, the 1st access time of (A) above can be ignored, and since the serial access time is substantially as shown in (B), high-speed reading is possible. become. However, when performing the read operation in units of multiple bytes by specifying the read start address in the sector,
The 1st access time cannot be ignored.

Therefore, a batch erasing type nonvolatile memory device having both the random access function shown in FIG. 8A and the serial access function shown in FIG. 8B can be constructed. That is, the output from the column address buffer and the output from the counter are selectively supplied to the column decoder of FIG. 8A according to the operation mode. Alternatively, in the embodiment of FIG. 6, the column address buffer may be provided with a column address terminal so that the initial value of the counter is supplied to the decoder as it is according to the operation mode, thereby adding a random access function.

FIG. 10 is a conceptual diagram for explaining the read operation when the random access function as described above is added. In this embodiment, the sense amplifier train is in the output high impedance state because the timing signal for activating it is not generated. Therefore, the data line DL selected by the column switch is
The selected MOSFET is connected to the common I / O line and the selected MOSFET is read out by the current sense provided on the common I / O line. That is, a bias voltage is transmitted to the selected data line by a current sense circuit similar to the conventional EPROM, and the current sense determines whether or not there is a current depending on the ON / OFF state of the storage MOSFET, and the read is performed. A read operation is performed on data (for example, 1 byte).

In this random access mode, the chip enable signal / CE is set to the low level, the storage MOSFET specified by the row address and the column address is selected, and the random access time is until the current MOSFET and the main sense are output. To be done.

FIG. 11 shows a timing chart of the read operation corresponding to the embodiment of FIG. Based on the timing when the write enable signal / WE changes to high level, the time tACC0 until the first data D0out is output is the 1st access time as described above, and the data D0ou is synchronized with the serial clock SC.
The time tSC at which t and D1out are sequentially output is the serial access clock time. Now, when reading n bytes by serial access, tACC0
It takes + n × tSC time.

FIG. 12 shows a timing chart of the read operation corresponding to the embodiment of FIG. The random access mode is designated by inputting a command, the address is taken in with the signal / CE set to the low level as in the normal EPROM, and the time until the data corresponding thereto is output is the random access time tACC. In such a random access mode, n × tACC is required to read n bytes.

When the same n bytes are read, the read time (tACC0 +
(n × tSC) and the read time (n × tACC) in the random access mode are almost the same, the serial access mode is advantageous when the number of n is large, and the number is small when the number of n is small. The random access mode is advantageous.

In the device having the serial access mode and the random access mode as in this embodiment, it is possible to switch the modes according to the number of read data, so that rational and high-speed reading can be performed. .

FIG. 13 is a flow chart for explaining an example of the rewriting operation in the batch erasing type nonvolatile memory device according to the present invention. In the same figure, in order to facilitate understanding of the invention, a flowchart diagram for explaining a rewriting operation in a conventional flash memory is also shown. That is, (A1) and (A2) are
The rewriting operation by the conventional method is shown, and the rewriting operation according to the present invention is shown in (B).

That is, in the conventional method, the erase bias is applied to the erase block by the erase command as shown in FIG. At this time, the charge is extracted from the floating gate to the substrate side by the tunnel current. Therefore, when the extraction amount is large, the threshold voltage is too low and the depletion mode is set. When the depletion mode is set in this way, the memory MOSFET is turned on and reading becomes impossible even though the word line is at the non-selection level. Therefore, by carrying out erase verify, a tunnel current is made to flow for a relatively short period of time to perform erasing little by little and the verify is performed to complete the erase operation.

In FIG. 7A, the write operation is performed by the write command. With this write command, data for one sector is serially input to the data latch, and when the data for one sector is complete, the write operation is started by applying the write bias. Also at this time, hot electrons are generated for a relatively short period of time, writing and verifying are performed little by little, and it is repeated until the threshold voltage of the memory MOSFET reaches a desired high voltage.

On the other hand, in the present invention, a rewrite command is provided as shown in (B). By this rewrite command, write data is first latched. The address of one sector is selected while the data is latched, and the erase bias is applied. The erase bias is applied by flowing a tunnel current from the substrate side to the floating gate of the memory MOSFET as described above.
Since the erase operation is performed so as to raise the threshold voltage, the tunnel current is made to flow for a relatively long time period in which complete erase is possible. That is, in the erasing method as described above, the threshold voltage of the memory MOSFET becomes high and the memory cell is turned off with respect to the selection level of the word line. There is no such problem.

Immediately after the application of the erase bias, the write bias is applied. At this time, the tunneling current is made to flow for a relatively short time, and writing and verifying are performed little by little to make the storage MOS.
It is repeated until the threshold voltage of the FET reaches a desired high voltage. In other words, even if the threshold voltage of the specific storage MOSFET is made higher than that of the other storage MOSFET by the erase operation, the desired low threshold voltage can be surely obtained as long as the above writing method is adopted. Since such a write operation is performed, there is no problem.

In the batch erasing type non-volatile memory device of the present invention, the erasing and writing as described above are performed. Therefore, a rewriting command is provided and one command is input from the outside so that the normal RAM Since it is possible to perform such rewriting, the usability is improved. That is,
A host side such as a CPU (Central Processing Unit) or a microcomputer only needs to issue a command and serially input write data.

That is, when the above-mentioned command issuance and serial input of data are completed, the batch erasing nonvolatile memory device is disconnected from the system bus and connected to peripheral circuits such as other memories to perform other information processing. You can go into action. During this period, the batch erasing type non-volatile memory device itself performs the erasing operation and the writing operation as described above. Then, the rewriting completion signal is sent to the CPU, or the writing completion signal can be read from the CPU by polling and the rewriting of the next sector can be started by a row or the like.

When the batch erasing type non-volatile memory device constitutes a data memory unit and constitutes an external memory device together with a controller such as a hard disk controller and is connected to the host system via such a controller, it is provided in the controller. When the rewriting data of a plurality of sectors and the number of sectors of the rewriting start sector address are input to the buffer memory, the rewriting of a plurality of sectors can be performed in a relatively short time by such a controller.

The functions and effects obtained from the above-mentioned embodiment are as follows. That is, (1) charges are injected from the substrate side to the floating gate through the tunnel insulating film to perform the erase operation due to the relative potential relationship between the control gate and the substrate, and the relative relation between the control gate and the drain is obtained. Memory transistors are arranged in a matrix at the intersections of the word lines and the data lines to perform a write operation by discharging charges from the floating gate to the drain side through the tunnel insulating film according to the potential relationship. A latch circuit is provided corresponding to the data line of the memory array, and an erase operation is performed in a unit of word line to which the control gate is coupled, and a write operation and a read operation are performed in a unit of word line via the latch circuit. By doing so, it is possible to efficiently rewrite data consisting of many bits in word line units. Since it is Ukoto, units can be made compatible with the magnetic memory device as speed and file memory of the memory access per data, the effect is obtained that usability is improved.

(2) As the above-mentioned latch circuit, the sense amplifier for sensing the stored information on the data line and the write amplifier for holding the write data and transmitting the write data to the data line also serve as a simplification of the circuit. The effect of becoming

(3) The input / output node of the above latch circuit is connected to the data input / output line by the selection signal formed by the address counter whose initial value can be designated, and is serially connected to the external terminal by the data input / output line. By performing the output and the input of, it is possible to obtain the effect that the desired data can be efficiently input and output.

(4) In the above memory array, the same sector address is assigned to the word lines of a plurality of memory mats, and erasing, writing and reading are performed in such sector units so that the external terminals are not connected to the external terminals. 1
The effect that serial input and output can be performed in units of a plurality of bits such as bytes is obtained.

(5) Management of data and the like is simplified by physically providing management information including at least one of data, rewriting history, redundancy information for ECC, and address pointer in the sector. The effect that it can be obtained is obtained.

(6) As a selection signal for connecting the input / output node of the latch circuit to the data input / output line, it is formed based on the column address supplied from the external terminal according to the designation of the random access operation mode. As a result, the effect that the unit data can be read at high speed is obtained.

(7) In the random access operation mode of (6), the latch circuit is placed in the non-operation state, and the stored information is read by the current sense amplifier provided in the data input / output line. By doing so, it is possible to obtain an effect that efficient reading can be realized with low power consumption.

(8) The operation modes including the erase, write and read operations are specified by the command input from the data terminal at the timing specified by the control signal, so that the number of external control terminals is reduced. The effect that various operation modes can be set is obtained.

(9) As the above command, by providing a rewrite command for continuously performing the erase and write operations in sector units, the effect of simplifying the rewrite control can be obtained.

(10) By limiting the addresses supplied from the outside only to the addresses designating the sectors, it is possible to mount on a package having a small number of external terminals and to facilitate mounting on a wiring board. To be

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the memory MOSFET may have any configuration as long as it is erased and programmed by the tunnel current as described above.
INDUSTRIAL APPLICABILITY The present invention can be widely used as a batch erasing type nonvolatile memory device in which erasing and writing are performed by tunnel current.

[0088]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, due to the relative potential relationship between the control gate and the substrate, charges are injected from the substrate side to the floating gate through the tunnel insulating film to perform an erase operation, and the relative potential between the control gate and the drain is compared. Depending on the relationship, memory transistors are formed by arranging memory transistors, which perform a write operation by discharging charges from the floating gate to the drain side through the tunnel insulating film, in a matrix at the intersections of the word lines and the data lines. A latch circuit is provided corresponding to the data line, and an erase operation is performed in units of word lines to which the control gates are coupled, and a write operation and a read operation are performed in units of word lines via the latch circuits. To efficiently rewrite data consisting of multiple bits in word line units. Since it can be made compatible with the magnetic memory device as speed and file memory of memory accesses per unit data,
It is easy to use.

As the latch circuit, the sense amplifier for sensing the stored information on the data line and the write amplifier for holding the write data and transmitting the write data to the data line also serve as a simplification of the circuit.

An input / output node of the latch circuit is connected to a data input / output line by a selection signal formed by an address counter whose initial value can be designated, and outputs and outputs data serially with an external terminal. By allowing input and output, desired data can be input and output efficiently.

In the above memory array, the same sector address is assigned to the word lines of a plurality of memory mats, and erasing, writing, and reading are performed in units of such sectors, so that 1 byte is used as an external terminal. Serial input and output can be performed in units of multiple bits as described above.

The above-mentioned sector is provided with management information including at least one of data, its rewriting history, redundant information for ECC, and address pointer physically combined, so that data management can be easily performed. it can.

By forming it as a selection signal for connecting the input / output node of the latch circuit to the data input / output line on the basis of the column address supplied from the external terminal according to the designation of the random access operation mode, The unit data can be read at high speed.

In the random access operation mode, the latch circuit is placed in the non-operation state, and the stored information is read by the current sense amplifier provided in the data input / output line. Efficient reading can be realized with low power consumption.

Designation of each operation mode including erasing, writing and reading is performed by a command input from a data terminal at a timing designated by a control signal, so that a variety of operation can be performed with a small number of external control terminals. The mode can be set.

Rewriting control is simplified by providing a rewriting command for sequentially performing erasing and writing operations in sector units as the above command.

By limiting the address supplied from the outside to only the address designating the sector, it can be mounted on a package having a small number of external terminals and can be easily mounted on a wiring board.

[Brief description of drawings]

FIG. 1 is a conceptual diagram of an embodiment for explaining an erase operation in a batch erase nonvolatile memory device according to the present invention.

FIG. 2 is a conceptual diagram of an embodiment for explaining a write operation in the batch erase nonvolatile memory device according to the present invention.

FIG. 3 is a conceptual diagram of an embodiment for explaining a read operation in the batch erase type nonvolatile memory device according to the present invention.

FIG. 4 is a conceptual diagram for explaining a rewriting operation in the batch erasing nonvolatile memory device according to the present invention.

FIG. 5 is a schematic block diagram showing an embodiment of a batch erase type nonvolatile memory device according to the present invention.

FIG. 6 is a schematic block diagram showing another embodiment of the batch erase nonvolatile memory device according to the present invention.

FIG. 7 is a timing chart for explaining an example of the operation of the batch erasing nonvolatile memory device according to the present invention.

FIG. 8 is a schematic block diagram showing another embodiment of the batch erase nonvolatile memory device according to the present invention.

FIG. 9 is a conceptual diagram for explaining a read operation of the batch erase type nonvolatile memory device according to the present invention.

FIG. 10 is a conceptual diagram for explaining a read operation when a random access function is added.

FIG. 11 is a timing chart of a read operation corresponding to the embodiment of FIG. 9 described above.

12 is a timing chart of a read operation corresponding to the embodiment of FIG.

FIG. 13 is a flow chart diagram for explaining an example of a rewrite operation in the batch erase nonvolatile memory device according to the present invention.

FIG. 14 is a schematic sectional structural view of a memory cell of a conventional batch erase type EEPROM.

[Explanation of symbols]

3 ... Drain electrode, 4 ... Floating gate, 5 ... Source electrode, 6 ... Control gate, 7 ... Thin oxide film,
8 ... P-type silicon substrate, 9 ... N-type diffusion layer, 10 ... Low-concentration N-type diffusion layer, 11 ... P-type diffusion layer.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 29/788 29/792 7210-4M H01L 27/10 434 29/78 371 (72) Inventor Otani Hiroaki 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device Development Center (72) Inventor Osamu Sakai 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi, Ltd. Semiconductor Division (72) Inventor Tanaka Toshihiro 1-280, Higashi Koigokubo, Kokubunji, Tokyo Metropolitan Research Laboratory, Hitachi, Ltd. (72) Inventor, Yasuro Kubota 5-20-1, Kamimizuhonmachi, Kodaira-shi, Tokyo Hiratsuru SLS Engineering Co., Ltd.

Claims (10)

[Claims] 1. A relative potential relationship between a control gate and a substrate causes an electric charge to be injected from a substrate side to a floating gate through a tunnel insulating film to perform an erasing operation. A memory array in which storage transistors that perform a write operation by discharging charges from the floating gate to the drain side through the tunnel insulating film due to a potential relationship are arranged in a matrix at intersections of word lines and data lines; An erase operation in units of word lines to which the control gates are coupled, and a write operation and a read operation in units of word lines through the latch circuits. A batch erasing type non-volatile memory device which is enabled. 2. The collective erasing type of claim 1, wherein the latch circuit also serves as a sense amplifier for sensing stored information on the data line and a write amplifier for holding write data and transmitting it to the data line. Non-volatile storage device. 3. The input / output node of the latch circuit is connected to a data input / output line by a selection signal formed by an address counter capable of designating an initial value, and the data input / output line is serially connected to an external terminal. The batch erasing type nonvolatile memory device according to claim 2, wherein output and input are performed. 4. The memory array according to claim 1, wherein the same sector address is assigned to word lines of a plurality of memory mats, and erasing, writing and reading are performed in such sector units. The batch erasing type non-volatile memory device according to claim 1, claim 2 or claim 3. 5. The sector according to claim 4, wherein the sector stores data together with rewriting history, redundancy information for ECC, and management information including at least one of address pointers. Erasable nonvolatile memory device. 6. A selection signal for connecting an input / output node of the latch circuit to a data input / output line is formed on the basis of a column address supplied from an external terminal according to designation of a random access operation mode. The batch erasing type non-volatile memory device according to claim 3, wherein 7. In the random access operation mode, the latch circuit is placed in a non-operation state, and stored information is read by a current sense amplifier provided in the data input / output line. 7. The batch erasing type nonvolatile memory device according to claim 6. 8. The specification of each operation mode including the erasing, writing and reading is performed by a command input from a data terminal at a timing specified by a control signal. Claim 2,
Claim 3, Claim 4, Claim 5, Claim 6 or Claim 7
All-in-one non-volatile memory device. 9. The batch erase type non-volatile memory device according to claim 8, wherein the command includes a rewrite command in which an erase operation and a write operation in sector units are continuously performed internally. . 10. The batch erase type non-volatile memory device according to claim 4, wherein the address supplied from the outside is only an address designating a sector.