JPH06314495A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To increase the operating margin of a flash memory and to prevent malfunction by applying a bias voltage of positive potential whose absolute value is smaller than the selecting level of a data line to the source line of a non-selecting memory cell. CONSTITUTION:Grounded potential is supplied to the source line SSO of a memory block MBSO including a selection memory cell MCB, but a first bias voltage of positive potential VP3 is given to the source line SS1 of a memory block MBS1 including a non-selection memory cell MCF. This voltage increases the source potential of the memory cell MCF, formation of a channel between the source and the drain is prevented and the lowering of the threshold voltage of the memory cell is suppressed. Consequently, the threshold voltage of the memory cell MCF becomes constant regardless of a disturbance time even when the initial threshold voltage is low. Consequently, the variation of the threshold value of the memory cell is suppressed, the operating margin of the flash memory is increased and the malfunction is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a flash memory having a memory array in which floating gate structure type non-volatile memory cells are arranged in a grid as a basic constituent element, and such a flash memory. The present invention relates to a technique which is particularly effective when used in a single-chip microcomputer having a built-in memory.

[0002]

2. Description of the Related Art EPROM (Erasable and Erasable)
Programmable Read Only M
memory: Read-only memory (Erasable / Programmable) or EEPROM (Electrical)
y Erasable and Programmable
A single-chip microcomputer incorporating a non-volatile memory such as e Read Only Memory (electrically erasable / programmable read only memory) is described in, for example, Japanese Patent Laid-Open No. 1-164169. In such a microcomputer, a non-volatile memory including an EPROM or an EEPROM stores programs, operation data, etc. necessary for step control of the microcomputer.

As is well known, the information stored in the EPROM is erased by irradiating it with ultraviolet rays. Therefore, the EPROM or its mounting board must be removed from the device when the information is erased. In this respect, the EEPROM is capable of erasing the retained information when the device is mounted, and its usability is E
It is superior to PROM, but as a memory cell, MNOS (Met
al Nitride Oxide Semiconductor
uctor: MOSF for selection in addition to a memory element made of metal, nitride, oxide, semiconductor, etc.
ET (Metal Oxide Semiconductor)
tor Field Effect Transist
or: a metal oxide semiconductor field effect transistor. In this specification, a MOSFET is used as a general term for an insulated gate field effect transistor. Therefore, the required layout area is 2.5 to 5 times that of an EPROM, and the chip occupation area is correspondingly increased. .

On the other hand, a flash memory (batch erasing type EEPROM) whose memory cell is composed of one transistor like the EPROM and is capable of batch erasing held information.
Are described, for example, in Japanese Patent Application Laid-Open No. 2-289997. In addition, a so-called floating gate structure type non-volatile memory cell having a control gate and a floating gate (hereinafter referred to as a floating gate structure cell) is arranged in a grid pattern and is connected to a predetermined number of data lines. US Pat. No. 5,065,365 discloses, for example, a so-called block erase type flash memory that includes a memory array that is divided into blocks in units of memory cells and is capable of erasing retained information in units of blocks. These flash memories are EPROM and E
In addition to having the features of EPROM, especially in block-type flash memory, it is possible to shorten the average time required to rewrite retained information by selectively erasing retained information for each application by erasing in block units. Become.

[0005]

In the conventional block erase type flash memory as described above, the block division of the memory array is coupled in the data line direction, that is, to a predetermined number of data lines as described above. It is performed in units of a predetermined number of memory cells. On the other hand, flash memory is
As described above, the program, the operation data, etc. of the microcomputer are provided for storage, and these programs, operation data, etc. have a word structure corresponding to the bus form of the microcomputer, etc. Further, in order to promote speeding up and high integration of a memory array such as a flash memory, the number of word lines, that is, the address space is expanded in the row direction rather than the number of data lines, that is, the address space is expanded in the column direction. Is taken to be so-called vertical structure. That is, in consideration of block erasing for each application, the block division of the memory array is indispensable to correspond to the bus form of the microcomputer or the like, that is, the word configuration of the program and the operation data to be held information,
In a memory array adopting a vertically long structure, there is no choice but to divide into blocks in the direction in which a relatively large word line is spread and also to be divided into memory cells that are coupled to a plurality of data lines according to the word line configuration. It becomes a big thing. As a result, there arises a problem that the average time required for rewriting the information held in the flash memory cannot be shortened as expected.

To address this, the inventors of the present invention have devised a method of dividing the memory array of the flash memory in the word line direction, that is, by using memory cells connected to a predetermined number of word lines as a unit. We have developed a block erase type flash memory that adopts a new block division method. As a result, the block division of the memory array can be realized with the memory cell coupled to one word line as a minimum unit, and is suitable for storing a relatively small-scale operation data as shown in FIG. 3, for example. A relatively small-capacity memory block MBS0 and the like and a relatively large-capacity memory block MBL0 and the like suitable for storing a relatively large-scale program are provided, and the block division of the memory array is set in association with the use of the storage area. This makes it possible to sufficiently reduce the average time required to write the held information. In this flash memory, the memory cells M that constitute the memory blocks MBS0 and MBL0, etc.
The control gate of C has a corresponding word line WS00.
To WS015 and WL00 to WL01023, respectively, and their drains are commonly connected to corresponding data lines B0 to Bn, respectively. Further, the sources of the memory cells MC forming each block are commonly coupled to the corresponding source line SS0 or SL0, respectively,
It is coupled to the source switch SS.

However, the inventors of the present application faced the following problems while increasing the scale of the block erase flash memory as described above. That is, when the flash memory is set to the write mode, for example, the selected word line WS00 to which the control gate of the selected memory cell MCB to be written is coupled, as shown in FIGS. Is supplied with a positive potential VP12 having a relatively large absolute value, and the non-selected word lines WS01 and WS10 to WS1 to which the control gates of the non-selected memory cells that are not to be written are coupled.
The ground potential GND, that is, 0 V is supplied to 1 and the like. At this time, a positive potential VP such as + 6.5V is applied to the selected data line B1 etc. to which the drain of the selected memory cell MCB is coupled.
6, the ground potential GND is supplied to the non-selected data lines B0 and B2 to Bn to which the drains of the non-selected memory cells are coupled. Further, the ground potential GND is supplied to all the source lines SS0 and SS1 etc. to which the sources of the memory cells of each memory block are coupled.

The source lines SS0 and SS1 etc. are at the ground potential G.
When coupled to ND, for example, the non-selected memory cell M whose drain is commonly coupled to the drain of the selected memory cell MCB, that is, the data line B1 and has a low threshold voltage.
In CF or the like, as shown in FIG. 7, the floating gate potential rises due to the drain coupling, and the N-type diffusion layer ND1 serving as the source S and the N serving as the drain D are formed.
A channel CH is formed between the channel CH and the type diffusion layer ND2.
Then, hot carriers composed of hot holes and hot electron pairs are generated in the channel CH, and hot holes among them are injected into the floating gate FG to cause write disturb, that is, data disturb via the data line. As a result, the non-selected memory cell MC
The threshold voltage of F and the like decreases, and in the worst case, the non-selected memory cells MCF and the like become depleted, resulting in malfunction of the flash memory. It should be noted that such a data disturb is generated when the source lines SS0 and S
Even when S1 and the like are opened, the same occurs through the parasitic capacitance of each source line.

Next, when the flash memory is set to the erase mode, for example, the selected memory block M to be erased is selected.
As illustrated in FIGS. 4 and 22, the positive potential VP12 is supplied to the selected source line SS0 of BS0, and the ground potential GND is applied to the unselected source line S1 of the unselected memory block MBS1 that is not the erase target. Supplied. At this time, all word lines WS00 and WS01 and W
The ground potential GND is supplied to S10, WS11 and the like, and all the data lines B0 to Bn are opened.

When the data lines B0 to Bn are opened, the memory cells MCA and the like forming the selected memory block MBS0 have a positive potential VP such as + 12V at their sources.
When 12 is applied, the threshold voltage is lowered and the data of logic "1" is held. At this time,
When the threshold voltage of the memory cell MCA or the like becomes small to some extent, a channel CH is formed between the N-type diffusion layer ND1 serving as the source S and the N-type diffusion layer ND2 serving as the drain D, so that the drain is in an open state. Even if it is said that the current flows from the source to the drain. As a result, hot holes are injected into the floating gate FG, and the threshold voltage lowers, that is, the speed-up erasing occurs according to the drain capacitance as shown in FIG. As a result, the threshold voltage of the memory cells MCA and the like which form the selected memory block MBS0 lowers than expected, and so-called erase variation increases.

On the other hand, both erasing and writing of the retained information in the flash memory are performed by FN (Fowler Nor).
dheim: Fowler-Nordheim) When using the tunnel phenomenon, the selected word line W0 to which the control gate of the memory cell MCB to be written is coupled is, as illustrated in FIGS.
The selected data line B1 to which the negative potential VN10 having a relatively large absolute value such as 10 V is supplied and whose drain is coupled
Is supplied with a positive potential VP5 such as + 5V. At this time, the non-selected memory cell MCD that is not the write target
Unselected word lines W to which control gates of
The ground potential GND is supplied to 1 and the like, the ground potential GND is supplied to the non-selected data lines B0 and Bn to which the drains are coupled, and all the source lines SL are connected.
The ground potential GND is supplied to 0 to SLn or they are opened. Therefore, in an unselected memory cell MCD or the like having a low threshold voltage, as illustrated in FIG.
A channel CH is also formed between the N-type diffusion layer ND3 serving as the source S and the N-type diffusion layer ND4 serving as the drain D, and hot holes are injected into the floating gate FG to lower its threshold voltage. Even if the threshold voltage is high, the potential difference between the drain and the floating gate is large, so that the floating gate FG
The electrons due to the FN tunnel phenomenon are emitted from the drain to the drain, and the threshold voltage thereof similarly decreases.

A first object of the present invention is to suppress the data disturb at the time of writing in a flash memory or the like in which the memory array is divided into blocks in the word line direction, and suppress the decrease in the threshold voltage of the memory cell. To do. A second object of the present invention is to suppress accelerated erasing at the time of erasing a flash memory or the like in which the memory array is divided into blocks in the word line direction, and to suppress erase variations in the threshold voltage of memory cells. Especially. A third object of the present invention is to suppress the data disturb at the time of writing in a flash memory or the like, in which both erasing and writing are performed by utilizing the FN tunnel phenomenon, and suppress the decrease of the threshold voltage of the memory cell. Especially. A fourth object of the present invention is to prevent the inversion of the held information while compressing the minimum unit of block division of the flash memory. A fifth object of the present invention is to improve the usability of the flash memory, shorten the average write time, and improve its reliability.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0014]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, in a flash memory or the like that includes a memory array in which cells with a floating gate structure are arranged in a grid pattern and the memory array is divided into blocks in the word line direction, its drain is commonly used as the drain of a selected memory cell during a write operation. A source of an unselected memory cell that is coupled and whose source is not commonly coupled to the source of the selected memory cell is provided with a first bias voltage whose absolute value is less than the selected level of the data line, or its drain is the drain of the selected memory cell. A second bias voltage whose absolute value is smaller than the selected level of the data line is applied to the control gate of the non-selected memory cell whose source is not commonly connected to the source of the selected memory cell. In the erase operation, the drain of the unselected memory cell whose drain is coupled to the drain of the selected memory cell has a third absolute value smaller than the selection level of the source line.
Gives a bias voltage of. Furthermore, in a flash memory or the like in which both erasing and writing are performed by using the FN tunnel phenomenon, the sources of the selected and non-selected memory cells and their control gates are not commonly coupled to the control gates of the selected memory cells during the write operation. A fourth bias voltage whose absolute value is smaller than the selection level of the data line is applied to the control gate of the selected memory cell, and the drain of the memory cell is composed of a high concentration diffusion layer and its source is composed of a low concentration diffusion layer. To do.

[0015]

According to the above-mentioned means, while suppressing the block division unit of the memory array, the data disturb during the write operation and the accelerated erase during the erase operation are suppressed to lower the threshold voltage of the memory cell and erase the same. Variation can be suppressed. As a result, it is possible to improve the usability of the flash memory, shorten the average time required for writing the flash memory, prevent the inversion of the retained information in the memory cell, and improve the reliability of the flash memory.

[0016]

【Example】

1. Outline and problems of flash memory in which the memory array is divided into blocks with a predetermined number of word lines as a unit, and countermeasures 1.1. Outline of flash memory 1.1.1. Structure and Operating Principle of Memory Cell FIG. 1 shows a cross-sectional structure diagram of an embodiment of a floating gate structure cell constituting a memory array of a flash memory to which the present invention is applied, and FIG. 2 shows its drain current. A characteristic diagram of one embodiment for explaining the relationship between the voltage and the gate-source voltage is shown. Based on these figures, the structure of the floating gate structure cell which serves as the storage element of the flash memory of this embodiment and its operating principle will be described first.

In FIG. 1, the non-volatile memory cells forming the memory array of the flash memory of this embodiment are
A so-called floating gate structure cell, which is a P-type semiconductor substrate P
The pair of N-type diffusion layers ND1 and ND2 formed on the surface of the SUB are used as the source S and the drain D, respectively.
Of these, a low-concentration N-type semiconductor region N ⁻ is formed between the diffusion layer ND1 and the P-type semiconductor substrate PSUB, and a high-concentration P region is formed between the diffusion layer ND2 and the P-type semiconductor substrate PSUB. A type semiconductor region P ⁺ is formed.

In the middle of the diffusion layers ND1 and ND2, that is, in the upper layer of the channel region, the thickness is 10 nm (nanometer).
A floating gate FG is formed across a relatively thin insulating film IS1, and a control gate CG is formed above the floating gate FG with an insulating film IS2 having a relatively large thickness.

In this embodiment, in the operation of writing the retained information to the memory cell, a voltage having a relatively large absolute value is applied to the control gate CG and the drain D to accelerate the electrons flowing out from the source by a high electric field near the drain. In that case, it is realized by injecting lucky electrons into the floating gate FG that do not experience collisions that lose energy (channel hot electron injection). When channel hot electron injection is performed to the floating gate FG, the memory cell is supposed to hold information of so-called logic "0" as shown in FIG. 2, and its threshold voltage is, for example, 6V. Such a relatively large value Vth0 is set.

On the other hand, the erasing operation of the information held in the memory cell is realized by, for example, applying a positive potential having a relatively large absolute value to the source S and extracting the electrons accumulated in the floating gate FG to the source S side by the tunnel phenomenon. To be done. When electrons are extracted to the source S by the tunnel phenomenon, the memory cell is supposed to hold information of so-called logic "1", as shown in FIG.
The threshold voltage is set to a relatively small value Vth1 such as 0.5V.

Next, in the read operation of the information held in the memory cell, in order to avoid weak writing to the memory cell, that is, inadvertent carrier injection to the floating gate FG, for example, the drain D has a relatively small absolute value of about + 1V. Applying a positive potential to the control gate CG
It is performed by applying a positive potential of about 5V. When the memory cell holds information of logic "1" and its threshold voltage is set to a relatively small value Vth1, a relatively large read current is passed between its drain and source. When the memory cell holds the information of logic "0" and the threshold voltage is set to a relatively large value Vth0,
A relatively small read current is passed between the drain and source. These read currents are transferred from the corresponding data lines to the common data lines CD0 to CD7, as described later.
Is transmitted to the corresponding read amplifier of the read / write circuit RW via the, and the logical level of the information held in the memory cell can be determined by the magnitude of the read current.

1.1.2. Configuration of Memory Array FIG. 3 is a partial circuit diagram of a memory array including the floating gate structure cells of FIG. The structure and operation of the memory array included in the flash memory of this embodiment and the features thereof will be described with reference to FIG.

In FIG. 2, the memory array MARY of the flash memory of this embodiment has 16 word lines WS00 to WS015 to WSp0 to WSp15, respectively.
P + 1 small-capacity memory blocks MBS0 to MBSp divided in units of 16 × (n + 1) floating gate structure cells MC and 1024 word lines WL00 to WL01023 to WLq0 to WLq.
It has q + 1 large-capacity memory blocks MBL0 to MBLq divided in units of 1024 × (n + 1) floating gate structure cells MC coupled to q1023.
Of these, the control gates CG of the n + 1 memory cells MC arranged in the same row of the memory blocks MBS0 to MBSp have corresponding word lines WS00 to WS01.
5 to WSp0 to WSp15 are commonly coupled to each other, and the drains of 16 memory cells MC arranged in the same column are commonly coupled to corresponding data lines B0 to Bn, respectively. The sources of all the memory cells MC configuring the memory blocks MBS0 to MBSp are commonly coupled to the corresponding source lines SS0 to SSp, respectively.

Similarly, the large capacity memory blocks MBL0 to MBL0
The control gates CG of n + 1 memory cells MC arranged in the same row of MBLq have corresponding word lines W
L00 to WL01023 to WLp0 to WLp102
10 commonly connected to 3 and arranged in the same row
The drains of the 24 memory cells MC are commonly coupled to the corresponding data lines B0 to Bn, respectively. All the memory cells M forming the memory blocks MBL0 to MBLq
The sources of C are commonly coupled to the corresponding source lines SL0 to SLq.

Word lines WS00-W forming memory blocks MBS0-MBSp and MBL0-MBLq.
S015 to WSp0 to WSp15 and WL00
~ WL01023 to WLq0 to WLq1023 are
As will be described later, it is coupled to the X address decoder XD. Further, the data lines B0 to Bn are coupled to the read / write circuit RW via the Y switch YS, and the source line SS0.
~ SSp and SL0 to SLq are source switches S
Bound to S.

As described above, the memory array MARY of the flash memory according to this embodiment is 16 × coupled to the word line direction, that is, 16 or 1024 word lines.
Block division is performed using (n + 1) or 1024 × (n + 1) memory cells as a unit to form p + 1 small capacity memory blocks MBS0 to MBSp and q + 1 large capacity memory blocks MBL0 to MBLq. As will be described later, these memory blocks are a unit of erasing retained information, and each memory block has 16 × (n +).
1) or 1024 × (n + 1) memory cells correspond to the corresponding source lines SS0 to SSp or SL0 to SLq.
When a predetermined positive potential VP12 is supplied to, the erased state, that is, the information of logic "1" is held.

As is well known, in a memory integrated circuit such as a flash memory, the number of data lines, that is, the number of word lines, that is, the width of the address space in the column direction, rather than the number of data lines in the column direction, is promoted in order to promote high speed and high integration. The address space has a large spread in the row direction, and has a so-called vertically long structure. Therefore, when the block division of the memory array is performed in the data line direction, that is, in the unit of a predetermined number of memory cells coupled to a predetermined number of data lines, like the conventional flash memory, the minimum unit becomes large, As a result, the average write time required for the flash memory increases. However, in the case of the flash memory of this embodiment, since the block division of the memory array is performed in the word line direction, even if the bit width of the bus of the microcomputer including the flash memory becomes large, the minimum unit is one word. It can be compressed down to lines. Therefore, for example, by assigning this minimum unit to the calculation data storage area,
By compressing the area to be erased / rewritten, the average time required for writing to the flash memory can be shortened.

The flash memory of this embodiment is
Although the memory blocks MBL0 to MBLq having a relatively large capacity are provided, these memory blocks can be used for storing a program that requires a relatively large storage area, for example. In this way, by dividing the memory array into a plurality of memory blocks of different sizes, the storage area of the flash memory is divided into blocks of the optimum size for each application, while reducing the average write time. ,
The use efficiency of the storage area can be improved.

1.1.3. Operating Conditions in Each Mode FIG. 4 shows a selection condition diagram in the erase mode and the write mode of the memory array MARY of FIG.
This selection condition diagram shows the selection conditions for the flash memory developed by the inventors of the present application prior to the present invention, and is provided to clarify the problem. The flash memory to which the present invention is applied has the same selection conditions except for a part thereof, but the problems of the previously developed flash memory and the countermeasures therefor will be described in detail in a later section.

As described above, the erasing operation of the flash memory is performed in units of memory blocks, and the source line of the selected memory block to be erased, that is, the selected source line, is as shown in FIG. 4A. , + 12V, which is a positive potential VP12 (first positive potential) having a relatively large absolute value. At this time, the ground potential GND is supplied to the source line of the non-selected memory block which is not to be erased, that is, the non-selected source line. Further, all the data lines shared by each memory block are in the open state OPEN, and the ground potential GND is supplied to all the word lines forming each memory block. As a result,
In the memory cell that constitutes the selected memory block, the electrons accumulated in the floating gate FG are extracted to the source side by the tunnel phenomenon, which causes 0.5
It has a relatively small threshold voltage Vth1 such as V.

Next, the write operation of the flash memory is not particularly limited, but is performed in units of eight memory cells, and the selected word line to which the control gate of the selected memory cell to be written is coupled is shown in FIG. Four
As shown in (b), the positive potential VP12 is alternatively supplied. At this time, the positive potential VP6 (second positive potential) of an intermediate potential such as +6.5 V is selectively supplied to the eight selected data lines to which the drains of the selected memory cells are coupled according to the write data. . Further, the ground potential GND is supplied to both the non-selected word line to which the control gates of the non-selected memory cells that are not to be written are connected and the non-selected data line to which the drain thereof is connected, so that the selected and non-selected memory cells are connected to each other. The ground potential GND is supplied to all the source lines to which the sources are coupled.
As a result, in the eight selected memory cells, channel hot electrons are generated and selectively injected into the floating gate FG, whereby a relatively large threshold voltage Vth0 such as 6V is obtained.

1.1.4. Block Configuration of Flash Memory FIG. 5 shows a block diagram of an embodiment of a flash memory to which the present invention is applied, that is, a flash memory including the memory array of FIG. An outline of the configuration and operation of the flash memory of this embodiment will be described with reference to FIG. The flash memory of this embodiment is included in a single-chip microcomputer, although not particularly limited thereto. The circuit elements forming each block in FIG. 5 are formed on the surface of one semiconductor substrate such as single crystal silicon together with other circuit elements (not shown) of the single chip microcomputer.

In FIG. 5, the flash memory of this embodiment has the memory array MARY divided into p + 1 small capacity memory blocks MBS0 to MBSp and q + 1 large capacity memory blocks MBL0 to MBLq, as described above. The basic component. Word lines WS00 to WS015 to WSp0 to WSp15 and WL00 to WL010 which form these memory blocks.
23 to WLq0 to WLq1023 are coupled to the X address decoder XD and selectively set to a predetermined selected or non-selected level. The X address decoder XD is supplied with i + 1-bit internal address signals X0 to Xi from the X address buffer XB. Also, X address buffer X
B to i + via address input terminals AX0 to AXi
1-bit X address signals AX0 to AXi are supplied.

The X address buffer XB has an address input terminal AX0 when the flash memory is selected.
~ X address signals AX0-A supplied via AXi
Xi is taken in and held, and internal address signals X0 to Xi are formed based on these X address signals,
It is supplied to the X address decoder XD. The X address decoder XD decodes the internal address signals X0 to Xi supplied from the X address buffer XB and sets the corresponding word line of the corresponding memory block to a predetermined selection or non-selection level. The word line selection and non-selection levels in the flash memory of this embodiment will be described later.

Next, the data lines B0 to Bn shared by each memory block of the memory array MARY are coupled to the Y switch YS. The Y switch YS includes, but is not particularly limited to, n + 1 switch MOSFETs provided between the data lines B0 to Bn and the eight common data lines CD0 to CD7. The gates of these switch MOSFETs are sequentially connected in common to each other, and corresponding data line selection signals are commonly supplied from the Y address decoder YD. As a result, the switch MOSFETs that form the Y switch YS are selectively turned on by eight by setting the corresponding data line selection signal to the high level, and are common to the corresponding eight data lines B0 to Bn. The data lines CD0 to CD7 are selectively connected.

The Y address decoder YD has a j + 1-bit internal address signal Y0 from the Y address buffer YB.
~ Yj are supplied. Further, the Y address buffer YB is supplied with j + 1-bit Y address signals AY0 to AYj via address input terminals AY0 to AYj.

The Y address buffer YB has an address input terminal AY0 when the flash memory is selected.
~ YY address signals AY0-A supplied via AYj
Yj is taken in and held, and internal address signals Y0 to Yj are formed based on these Y address signals,
It is supplied to the Y address decoder YD. The Y address decoder YD decodes the internal address signals Y0 to Yj supplied from the Y address buffer YB and sets the corresponding data line selection signal to the high level.

On the other hand, the source lines SS0 to SSp and SL0 to SL of each memory block of the memory array MARY.
q is coupled to the source switch SS. Internal address signals X0 to Xi are supplied to the source switch SS from the X address buffer XB. When the flash memory is in the selected state, the source switch SS is X
The predetermined bits of the internal address signals X0 to Xi supplied from the address buffer XB are decoded and the source lines SS0 to SSp or SL0 of the corresponding memory block are decoded.
SLq is set to a predetermined selection or non-selection level. The source lines SS0 to SS0 in the flash memory of this embodiment are
The selection and non-selection levels of SSp and SL0 to SLq will be described later.

Data lines B0 to B of the memory array MARY
The common data lines CD0 to CD7 to which n is selectively connected by eight via the Y switch YS are respectively coupled to the corresponding unit circuits of the read / write circuit RW.

The read / write circuit RW has a common data line C.
It includes eight unit circuits provided corresponding to D0 to CD7, and each of these unit circuits includes one write amplifier and one read amplifier. Of these, the input terminal of each write amplifier is the corresponding data input / output terminal D0.
To D7, the output terminals of which are coupled to the corresponding common data lines CD0 to CD7. The input terminals of each read amplifier are connected to the corresponding common data lines CD0 to CD7.
, And its output terminal is connected to the corresponding data input / output terminals D0 to D7. An internal control signal WC is supplied from the timing generation circuit TG to each write amplifier of the read / write circuit RW.

Each write amplifier of the read / write circuit RW is selectively operated by receiving the high level of the internal control signal WC when the flash memory is selected in the write mode. In this operating state, each write amplifier forms a predetermined write signal according to the write data supplied via the corresponding data input / output terminals D0 to D7, and the memory array MARY via the corresponding common data line CD0 to CD7. Are written in the selected eight memory cells. The level of the write signal output from the write amplifier is a positive potential VP6 such as +6.5 V when the corresponding write data is a logical "0", and the corresponding write data is a logical "1". At this time, it is set to the ground potential GND, that is, 0V.

On the other hand, each read amplifier of the read / write circuit RW has the corresponding common data lines CD0 to CD7 from the eight selected memory cells of the memory array MARY when the flash memory is selected in the read mode.
A read signal output via the flash memory is amplified and sent to the outside of the flash memory via the corresponding data input / output terminals D0 to D7. In this embodiment, the memory array M
The read signal output from the selected memory cell of ARY is a current signal corresponding to the threshold voltage of the selected memory cell as described above. Therefore, each read amplifier of the read / write circuit RW includes a current-voltage conversion circuit for converting a read signal obtained as a current signal into a voltage signal.

The timing generation circuit TG is provided with a memory enable signal MEB, a write enable signal WEB and an output enable signal OEB which are supplied as start control signals from a pre-stage circuit (not shown) of the microcomputer.
Various internal control signals are selectively formed based on the above, and are supplied to each part of the flash memory.

1.2. Cause of write disturb and its countermeasure 1.2.1. Cause of Write Disturb FIG. 6 shows a connection diagram at the time of source grounding in the write mode of the flash memory of FIG. 4, which was developed by the present inventors prior to the present invention, and FIG. 7 shows the problem. A cross-sectional structure diagram for explaining is shown. Also,
FIG. 8 shows a connection diagram when the source is opened in the write mode of the flash memory of FIG. 4, and FIG. 9 shows a cross-sectional structure diagram for explaining the problem. Further, FIG. 10 shows a general characteristic diagram for explaining the relationship between the drain voltage and the leak current of the floating gate structure cell, and FIG. 11 shows data between memory blocks of different sizes in the memory array. A calculation diagram is shown to explain the disturbance. Based on these figures,
Among the problems of the flash memory developed by the inventors of the present application prior to the present invention, the mechanism and the cause of the write disturb will be described. In the connection diagram below, a memory cell to be written is indicated by a dotted circle. Further, the selected memory block including the selected memory cell and the memory block to be erased are shown by thick solid lines, and the unselected memory blocks are shown by dotted lines.

In the write mode of the flash memory developed by the inventors of the present invention prior to the present invention, as shown in FIGS. 4 and 6, the word line to which the control gate of the selected memory cell MCB to be written is coupled. W
A positive potential VP12 of + 12V is alternatively supplied to S00, and the data line B1 to which the drain is coupled is selectively supplied with a positive potential of + 6.5V on condition that the corresponding write data is logic "0". The potential VP6 is supplied. At this time, the non-selected word lines WS01, W to which the control gates of the non-selected memory cells not to be written are coupled.
The ground potential GND is supplied to S10 and WS11 and the like, and the ground potential GN is also applied to the non-selected data lines B0 and B2 to Bn to which the drain of the selected memory cell MCB is not coupled.
D is supplied. In addition, the ground potential GND is supplied to the source lines SS0 and SS1 to which the sources of all the memory cells are coupled.

From these facts, first, the selected memory cell M
In CB, since the drain is set to the positive potential VP6, channel hot electrons are generated, drawn to the positive potential VP12 of the control gate CG and injected into the floating gate FG, and the threshold voltage thereof is increased to about 6V. Further, its control gate is coupled to the selected word line WS00 and its drain is the unselected data line B0.
In the non-selected memory cell MCA or the like coupled to, the channel hot electrons are not generated because the drain is set to the ground potential GND, the control gate is coupled to the non-selected word line WS10, and the drain is the non-selected data line B1. In the non-selected memory cell MCE etc. coupled to
Again, since the drain is set to the ground potential GND, channel hot electrons are not generated.

However, in a non-selected memory cell MCF whose control gate is coupled to the non-selected word line WS10 and its drain is coupled to the selected data line B1,
As illustrated in FIG. 7, the threshold voltage is 0.5V.
That is, in the erased state, the potential of the floating gate FG rises due to the drain coupling, and the channel CH is formed. Therefore, as shown in FIG. 10, a similar leak current flows through the source and drain of the non-selected memory cell MCF or the like. As a result, electron-hole pairs as hot carriers are generated, and the hot holes among these are injected into the floating gate FG, and the threshold voltage of the non-selected memory cells MCF and the like decreases. Further, when the threshold voltage is 6 V, that is, in the written state, the potential difference between the drain and the floating gate is large, so that the electrons accumulated in the floating gate FG are extracted to the drain side by the tunnel phenomenon.
As a result, the threshold voltage of the non-selected memory cells MCF and the like also decreases. Due to the write disturb as described above, when the non-selected memory cell MCF or the like is in the erased state, it is depleted, and when it is in the written state, it is inverted to the erased state, resulting in malfunction of the flash memory. Become.

In the write disturb, that is, the data disturb via the data line as described above, as shown in FIGS. 8 and 9, the source line is in the open state OPEN.
Even in such a case, it similarly occurs via the parasitic capacitance Cs of the source, resulting in lowering the threshold voltage of the non-selected memory cells MCF and the like.

By the way, in the case of the flash memory of FIG. 5 in which the memory array is divided into a plurality of memory blocks of different sizes, the influence of the data disturb on the non-selected memory cells changes depending on the size of the memory block. That is, assuming that the time required for writing per bit is 100 μs (microseconds) and the operation of collectively erasing the target memory block and then selecting and writing all the word lines is repeated 10,000 times, for example, Small capacity memory block M
As shown in FIG. 11, the data disturb time received by the non-selected memory cells included in BS0 to MBSp is small in the memory blocks MBS0 to MB in which writing is performed.
If it is performed for Sp, it takes 1.5 ms (milliseconds), but writing is performed in a large capacity memory block M.
If performed on BL0 to MBLq, 1
It will reach 024 seconds.

As shown in FIG. 14 described later, in the conventional flash memory in which the ground potential GND is applied to the source lines of the selected and unselected memory cells, especially when the initial threshold voltage of the unselected memory cells is low, The change in the threshold voltage due to the data disturb increases as the disturb time increases. That is, in a flash memory in which the memory array is divided into a plurality of memory blocks of different sizes, the effect of data disturb on unselected memory cells differs depending on the size of the memory block. As a result, the threshold voltage varies and the operating margin of the flash memory decreases.

1.2.2. Countermeasure by Providing Bias Voltage to Non-Selected Source Line FIG. 12 shows a connection diagram of an embodiment in which a countermeasure is given to the non-selected source line in the write mode of the flash memory of FIG. , FIG. 13 and FIG. 14 respectively show a sectional structure diagram and a characteristic diagram for explaining the effect. Based on these figures, an outline of the data disturb countermeasure of the flash memory to which the present invention is applied and its features will be described.

In FIG. 12, the write operation in the flash memory of this embodiment is performed by selecting the selected memory cell MCB.
Selected word line WS0 to which the control gate of
A positive potential VP12 of + 12V is supplied to 0, and a positive potential V of + 6.5V is applied to the selected data line B1 to which the drain is coupled.
This is done by supplying P6. At this time, the ground potential GN is applied to the other unselected word lines WS01 to WS015 of the memory block MBS0 including the selected memory cell MCB.
D is supplied to the non-selected data lines B0 and B2 to Bn
Is also supplied with the ground potential GND. Selected memory cell MC
The ground potential GND is supplied to the source line SS0 of the memory block MBS0 including B.

However, in this embodiment, the ground potential GND is supplied to the source line SS0 of the memory block MBS0 including the selected memory cell MCB, but the source line SS1 of the memory block MBS1 including the non-selected memory cells MCF and the like. That is, the drain is the selected memory cell MCB
Of unselected memory cells M whose common source is not coupled to the source of the selected memory cell MCB.
A first bias voltage such as + 3.5V, that is, a positive potential VP3 (third positive potential) is applied to the source such as CF. As shown in FIG. 13, this bias voltage raises the source potential of the non-selected memory cells MCF and the like to prevent a channel from being formed between the source and drain thereof and suppress the generation of hot holes. Unselected memory cell M
It acts to suppress a decrease in the threshold voltage of CF or the like. Therefore, the threshold voltage of the non-selected memory cells MCF is
As shown in FIG. 14, even when the initial threshold voltage is as low as 0.5 V, it takes a constant value regardless of the disturb time. As a result, variations in the threshold voltage of the memory cells can be suppressed, the operation margin of the flash memory can be increased, and malfunctions thereof can be prevented.

1.2.3. Countermeasure by Providing Bias Voltage to Non-Selected Word Lines FIG. 15 shows a connection diagram in the case where a countermeasure is applied to the non-selected word lines in the write mode of the flash memory of FIG. 5, and FIG. Shows a cross-sectional structure diagram for explaining the effect. Also, FIG.
7 shows a general characteristic diagram for explaining the relationship between the gate voltage and the gate current of the floating gate structure cell, and FIGS. 18 and 19 show the bias voltage of the non-selected word line in FIG. Cross-sectional structural diagrams are respectively shown for explaining the problems when the temperature is too low or too high. Further, FIG. 20 shows a characteristic diagram for explaining the effect of the measure of FIG. 15, and FIG. 21 shows another characteristic diagram for explaining the effect of the measure of FIG. Based on these drawings, another outline of the data disturb countermeasure of the flash memory to which the present invention is applied and its features will be described.

In FIG. 15, the write operation in the flash memory of this embodiment is performed in the selected memory cell MCB.
Selected word line WS0 to which the control gate of
A positive potential VP12 of + 12V is supplied to 0, and a positive potential V of + 6.5V is applied to the selected data line B1 to which the drain is coupled.
This is done by supplying P6. At this time, the ground potential GND is supplied to the non-selected word line WS01 to which the control gates of the non-selected memory cells are coupled, and the ground potential GND is also supplied to the non-selected data lines B0 and B2 to Bn.
Is supplied.

However, in this embodiment, the source line SS of the memory block MBS1 that does not include the selected memory cell.
1 and the like are opened, and word lines WS10 to WS11 and the like of the unselected memory blocks, that is, their drains are commonly coupled to the drains of the selected memory cells MCB and their sources are not commonly coupled to the sources of the selected memory cells MCB. A second bias voltage such as + 1V, that is, a positive potential VP1 (fourth positive potential) is applied to the control gate of the selected memory cell MCF or the like. Although this bias voltage does not prevent the channel CH from being formed between the source and drain of the non-selected memory cell MCF as shown in FIG. 16, its potential is as shown in FIG. It corresponds to a gate voltage which is a boundary value between a region where the gate current of the non-selected memory cell MCF or the like mainly flows under the influence of avalanche hot holes and a region where the gate current mainly flows under the influence of avalanche hot electrons. To be done. Therefore, the non-selected memory cell M
Even if the channel CH is formed between the source and drain of CF or the like, the gate current, that is, the movement of charges to the floating gate FG, disappears, and the threshold voltage does not change. As a result, variations in the threshold voltage of the memory cell can be suppressed, the operation margin of the flash memory can be increased, and the malfunction thereof can be prevented.

By the way, when the bias voltage of the non-selected word line WS10 or the like is set to a low potential such as 0.5 V in the measure of FIG. 15, the initial operating point of the non-selected memory cell MCF or the like is b in FIG. It becomes a point. Therefore, in the non-selected memory cell MCF or the like, as shown in FIG. 18, avalanche hot holes are injected from the channel CH formed between the source and drain of the avalanche hot hole to the floating gate FG, whereby the gate voltage thereof is increased. To rise. As a result, the operating points of the non-selected memory cells MCF and the like reach the point d through the point c in FIG. 17, and eventually become stable.

On the other hand, when the bias voltage of the non-selected word line WS10 or the like is set to a high potential such as 1.5 V in the countermeasure of FIG. 15, the initial operating point of the non-selected memory cell MCF or the like is f in FIG. It becomes a point. Therefore, in the non-selected memory cell MCF or the like, as shown in FIG. 19, avalanche hot electrons are injected from the channel CH formed between the source and drain of the avalanche hot electron into the floating gate FG, and thereby the gate voltage thereof is increased. descend. As a result, the operating point of the non-selected memory cells MCF and the like reaches the point d after passing through the point e in FIG. 17 and becomes stable.

That is, the floating gate structure type memory cell has a stable point of the gate voltage which is not affected by avalanche hot holes and hot electrons, and when the initial gate voltage deviates from this stable point. Avalanche hot holes or hot electrons are injected so that the potential of the floating gate FG reaches a stable point. As is clear from the above description, in the flash memory of this embodiment, the control gate CG of the non-selected memory cell corresponds to the above stable point in advance.
Since a bias voltage of 0 V is applied, injection of hot holes and hot electrons into the floating gate FG is suppressed, resulting in suppression of change in threshold voltage. In FIG. 20, the gate voltage Vg is +
The relationship between the threshold voltage of the non-selected memory cells MCF and the like and the disturb time when changing to 0.5V, + 1.0V and + 1.5V is shown in association with FIG. The relationship between the initial threshold voltage and the disturb time when a gate voltage of +1.0 V is applied to the control gate CG of the selected memory cell MCF or the like is shown. As is clear from these figures, when the control gate CG is applied with a bias voltage of +1.0 V corresponding to the above-mentioned stable point, the threshold voltage of the non-selected memory cells MCF is stable regardless of the disturb time. Will be things.

1.3. Causes of Erasure Disturb and Countermeasures 1.3.1. Cause of Erase Disturbance FIG. 22 shows a connection diagram in the erase mode of the flash memory of FIG. 4 developed by the inventors of the present application prior to the present invention. Further, FIG. 23 shows a sectional structure diagram for explaining the problem, and FIG. 24 shows a characteristic diagram for explaining accelerated erase in the flash memory of FIG. Among these problems of the flash memory developed by the inventors of the present application prior to the present invention, the mechanism and the cause of accelerated erasing will be described based on these drawings.

In FIG. 22, the erase mode of the flash memory developed by the inventors of the present invention prior to the present invention is as follows:
This is performed by supplying a positive potential VP12 of + 12V to the source line SS0 of the selected memory block MBS0 to be erased. At this time, the ground potential GND is supplied to the source line SS1 and the like of the non-selected memory block MBS1 and the like which are not to be erased. Further, the ground potential GND is supplied to all the word lines forming each memory block, and the data lines B0 to Bn shared by these memory blocks MB are in the open state OPEN.

From these facts, first, in the selected memory block MBS0, since the positive potential VP12 of + 12V is supplied to the corresponding source line SS0, each memory cell MC
The electrons accumulated in the floating gate FG of are extracted to the source side by the tunnel phenomenon. Therefore, the threshold voltage of all the memory cells MC forming the selected memory block MBS0 is lowered to about 0.5V, and thereby the information of logic "0" is held. On the other hand, in the unselected memory block MBS1 and the like, since the ground potential GND is supplied to the corresponding source line SS1 and the like, electrons are not extracted by the tunnel phenomenon, and all the memory cells that configure the unselected memory block MBS1 and the like. The MC threshold voltage does not change.

By the way, in the memory cell MCA or the like which constitutes the selected memory block MBS0, as shown in FIG. 23, the channel CH is formed when the threshold voltage thereof is lowered to some extent, and the channel CH is formed from the source to the drain. A current for charging the drain capacitance Cd flows. At this time, hot holes of hot carriers generated in the channel CH are injected into the floating gate FG, and so-called accelerated erasing is performed in which the threshold voltage of the selected memory cell MCA or the like is abnormally lowered. The influence of this accelerated erase on the threshold voltage of the selected memory cell MCA or the like is
As shown in FIG. 24, the larger the value of the drain capacitance Cd, the larger the drain capacitance Cd, which causes an increase in erase variation as a flash memory.

1.3.2. Measures by Applying Bias Voltage to Data Line FIG. 25 shows a connection diagram of an embodiment in which a measure to apply a bias voltage to the data line is applied in the erase mode of the flash memory of FIG. 5, and FIG. Shows a cross-sectional structure diagram for explaining the effect. Based on these figures, the outline and the features of the flash memory erase erasure countermeasure to which the present invention is applied will be described.

In FIG. 25, the erase operation in the flash memory of this embodiment is performed by selecting the selected memory block MBS.
This is performed by supplying the positive potential VP12 of + 12V to the 0 source line SS0. At this time, the ground potential GND is applied to the source line SS1 and the like of the non-selected memory block MBS1.
Is supplied, and the ground potential GND is also supplied to all word lines of each memory block.

However, in this embodiment, the data lines B0 to Bn shared by the memory blocks have +1.0.
A third bias voltage such as V, that is, a positive potential VP1 (fifth positive potential) is applied. This bias voltage is
6, the drain potential of the memory cells MBA and the like which form the selected memory block MBS0 is increased to prevent a channel from being formed between the source and the drain thereof and suppress the generation of hot holes, Cell MCA
It acts to prevent the threshold voltage, etc., from unnecessarily decreasing due to accelerated erasing. As a result, it becomes possible to suppress the erase variation of the flash memory and increase the operation margin thereof.

2. Outline and problems of flash memory for erasing / writing by FN tunnel phenomenon and countermeasures 2.1. Outline of flash memory 2.1.1. Structure and Operating Principle of Memory Cell FIG. 27 shows an FN (Fowler-Nordheim:
Fowler-Nordheim) Erase due to tunnel phenomenon
A cross-sectional structure diagram of a floating gate structure cell forming a memory array of a flash memory for writing is shown in FIG.
Shows a characteristic diagram for explaining the relationship between the drain current and the gate-source voltage. Based on these figures, the structure of the floating gate structure cell which serves as the storage element of the flash memory of this embodiment and its operating principle will be described first.

In FIG. 27, the non-volatile memory cell forming the memory array of the flash memory of this embodiment is a so-called floating gate structure cell, which is a high-concentration N-type diffusion formed on the surface of the P-type semiconductor substrate PSUB. Layer ND
3 and ND4 are the source S and the drain D, respectively. In the middle of the diffusion layers ND3 and ND4, that is, in the upper layer of the channel region, a floating gate FG is formed with a relatively thin insulating film IS3 interposed therebetween, and a relatively thick insulating film IS is formed on the floating gate FG.
A control gate CG is formed with 4 in between.

In this embodiment, the operation of writing the retained information to the memory cell is performed by the FN tunnel phenomenon by applying a negative potential having a relatively large absolute value to the control gate CG and applying a positive intermediate potential to the drain D. It is realized by extracting electrons from the floating gate FG to the drain. When electrons are extracted from the floating gate FG, the memory cell is
As shown in FIG. 8, the information of logic “0” is held, and its threshold voltage is set to a value Vth0 smaller than that of the memory cell in the erased state in which no writing is performed.

On the other hand, in the erase operation of the retained information of the memory cell, a positive potential having a relatively large absolute value is applied to the control gate CG, and electrons are injected from the P-type semiconductor substrate PSUB to the control gate CG by the FN tunnel phenomenon. It is realized by When electrons are injected into the control gate CG by the tunnel phenomenon, the memory cell is supposed to hold information of logic "1" as shown in FIG. 28, and its threshold voltage is relatively high. It is set to a large value Vth1.

2.1.2. Configuration of Memory Array FIG. 29 is a partial circuit diagram of a memory array including the floating gate structure cells of FIG. An outline of the configuration and operation of the memory array included in the flash memory of this embodiment will be described with reference to FIG.

In FIG. 29, the memory array MARY of the flash memory of this embodiment has m + 1 word lines W0 to Wm arranged in the horizontal direction and n + 1 data lines B0 arranged in the vertical direction in FIG. To Bn. At the intersection of these word lines and data lines, (m + 1) ×
(N + 1) floating gate structure cells MC are arranged in a grid. Of these, the control gates CG of the n + 1 memory cells MC arranged in the same row of the memory array MARY are commonly coupled to the corresponding word lines W0 to Wm. The drains of the m + 1 memory cells MC arranged in the same column have corresponding data lines B0 to B0.
Each of them is commonly coupled to Bn and its source is commonly coupled to the corresponding source line SL0 to SLn.

The word lines W0 to Wm forming the memory array MARY are coupled to an X address decoder XD (not shown). The data lines B0 to Bn are coupled to the read / write circuit RW via a Y switch YS (not shown), and the source lines SL0 to SLn are coupled to a source switch SS (not shown).

As described above, the erase operation of the floating gate structure cells forming the memory array MARY is performed by applying a positive potential having a relatively large absolute value to its control gate. Therefore, when the memory array configuration of FIG. 29 is adopted, the erase operation of the memory cell is performed in units of word lines.

2.1.3. Operating Conditions in Each Mode FIG. 30 shows selection condition diagrams in the erase mode and the write mode of the memory array MARY of FIG. It should be noted that this selection condition diagram shows the selection conditions before the improvement of the flash memory developed by the inventors of the present invention prior to the present invention, and is provided to clarify the problem. The flash memory to which the present invention is applied has the same selection conditions except for a part thereof, but problems and countermeasures of the flash memory of FIG. 30 will be described in a later section.

As described above, the erase operation of this flash memory is performed in units of word lines, and the selected word line to which the control gate of the selected memory cell to be erased is connected is shown in FIG. +1 as shown
A positive potential VP15 having a relatively large absolute value such as 5 V is supplied. At this time, the ground potential GND is supplied to the non-selected word line to which the control gate of the non-selected memory cell which is not to be erased is coupled. The ground potential GND is supplied to all the data lines B0 to Bn, and the ground potential GND is also supplied to all the source lines SL0 to SLn. As a result, n + 1 coupled to the selected word line
In each memory cell, electrons are injected from the semiconductor substrate into its control gate due to the FN tunneling phenomenon, so that it has a relatively large threshold voltage Vth1.

Next, the write operation of the flash memory is performed in memory cell units, and the selected word line to which the control gate of the selected memory cell to be written is coupled is as shown in FIG. , −10 V and a relatively large absolute value of the negative potential VN10 (first negative potential) are alternatively supplied. At this time, the selected data line to which the drain of the selected memory cell is coupled is +5.0.
A positive potential VP5 (sixth positive potential) such as V is supplied alternatively. Further, the ground potential GND is supplied to both the non-selected word line to which the control gates of the non-selected memory cells that are not to be written are connected and the non-selected data line to which the drain thereof is connected, so that the selected and non-selected memory cells are connected to each other. The ground potential GND is supplied to all the source lines to which the sources are coupled, or the open state OP
It is referred to as EN. As a result, in the selected memory cell, the electrons accumulated in the floating gate are extracted to the drain side by the FN tunneling phenomenon, and thus have a relatively small threshold voltage Vth0.

2.2. Cause of write disturb and its countermeasure 2.2.1. Cause of Write Disturb FIG. 31 shows a connection diagram in the write mode of the flash memory of FIG. 30, which was developed by the inventors of the present invention prior to the present invention, and FIG. 32 is for explaining the problem. A cross-sectional structural diagram is shown. Based on these figures, the problem of the flash memory of FIG. 30, that is, the mechanism and the cause of the write disturb due to the data disturb will be described.

In the write mode of the flash memory developed by the inventors of the present application prior to the present invention, as shown in FIGS. 30 and 31, the word line to which the control gate of the selected memory cell MCB to be written is coupled. Negative potential VN10 of -10V is alternatively supplied to W0, and the data line B1 to which the drain is coupled is selectively supplied with + 5.0V on condition that the corresponding write data is logic "0". Positive potential VP5 is supplied. At this time, the ground potential GND is supplied to the word line W1 or the like to which the control gates of the non-selected memory cells MCD or the like which are not to be written are connected, and the other data lines B0 and B2 to which the drain of the selected memory cell MCB is not connected.
The ground potential GND is also supplied to Bn. The ground potential GND is supplied to all the source lines SL0 to SLn.

From these things, first, the selected memory cell M
In CB, the positive potential VP5 is supplied to its drain and the negative potential VN10 is supplied to its control gate, so that the electrons accumulated in the control gate are extracted to the drain side, and the threshold voltage is lowered to Vth0. To be extinguished. On the other hand, in the non-selected memory cell MCA or the like whose control gate is coupled to the selected word line W0 and its drain is coupled to the non-selected data line B0, the drain is set to the ground potential GND, so that the FN tunnel phenomenon does not occur. , Its threshold voltage does not change. Further, in a non-selected memory cell MCC whose control gate is coupled to the non-selected word line W1 and its drain is coupled to the non-selected data line B0, the control gate and the drain are set to the ground potential GND, so that the FN tunnel is also generated. The phenomenon does not occur.

However, in the non-selected memory cell MCD or the like having its control gate coupled to the non-selected word line W1 and its drain coupled to the selected data line B1, the source lines SL0, SL1 etc. are coupled to the ground potential GND. At this time, as illustrated in FIG. 32, when the threshold voltage is a low value Vth0, that is, in the write state, the potential of the floating gate FG rises due to the drain coupling, and the channel CH is formed. Therefore, a leak current flows in the source and drain of the non-selected memory cell MCD, the generated hot holes are injected into the floating gate FG, and the threshold voltage of the non-selected memory cell MCD decreases. It should be noted that such data disturb similarly occurs through the parasitic capacitance of each source line even when the source lines SL0, SL1 and the like are opened during writing. In addition, the threshold voltage Vt is high
In the case of h1, that is, in the erased state, the electrons accumulated in the floating gate FG are extracted to the drain side by the FN tunnel phenomenon due to the potential difference between the drain and the floating gate, which also causes the unselected memory cells MCD, etc. The threshold voltage drops.

2.2.2. Measures by Applying Bias Voltage to All Source Lines and Non-Selected Word Lines FIG. 33 shows a case where measures are taken to apply bias voltage to all source lines and non-selected word lines in the write mode of the flash memory of FIG. FIG. 34 shows a connection diagram of one embodiment of the present invention, and FIG. 34 shows a sectional structure diagram for explaining the effect. Based on these figures, an outline of the data disturb countermeasure of the flash memory to which the present invention is applied and its features will be described.

In FIG. 33, the write operation in the flash memory of this embodiment is performed in the selected memory cell MCB.
Supply a negative potential VN10 of -10V to the selected word line W0 to which the control gate of the same is connected, and a positive potential VP5 of + 5.0V to the selected data line B1 to which its drain is connected.
Is provided. At this time, the ground potential GND is supplied to the non-selected data lines B0 and B2 to Bn.

However, in this embodiment, all the source lines SL0 to SLn are supplied with the fourth bias voltage such as +2.0 V, that is, the positive potential VP2 (seventh positive potential), and all the non-source voltages are applied. The bias voltage is also supplied to the selected word line W1 and the like. These bias voltages are
As shown in FIG. 13, the source potential of the non-selected memory cell MCD or the like is increased to prevent a channel from being formed between the source and the drain of the non-selected memory cell MCD, prevent the generation of hot holes, and prevent the generation of hot holes between the drain and floating gate. , And acts to prevent the electrons accumulated in the floating gate from being extracted to the drain side.
As a result, it is possible to suppress a decrease in the threshold voltage of the non-selected memory cells MCD and the like, thereby increasing the operation margin of the flash memory and preventing its malfunction.

2.2.3. Problems of Measures for Applying Bias Voltage to Source Line FIG. 35 is a cross-sectional structure diagram for explaining problems when measures for applying a bias voltage to the source line are applied in the write mode of the flash memory of FIG. Has been done. Based on the figure, the problem of the measure for applying the bias voltage to the source line, that is, the mechanism and the cause of the source disturb will be described.

As described above, in the flash memory of this embodiment, the bias voltage of +2 V, that is, the positive potential VP2 is applied to all the source lines SL0 to SLn, the non-selected word lines W1, etc. It prevents the threshold voltage from decreasing. However, when attention is paid to a non-selected memory cell MCA whose control gate is coupled to the selected word line W0 and its drain is coupled to the non-selected data line B0, as shown in FIG.
On the contrary, since the potential difference between the source and the floating gate becomes large, a source disturb occurs in which the charge accumulated in the floating gate FG is extracted to the high concentration diffusion layer ND3 serving as the source S, and the unselected memory cell MC
There arises a problem that the threshold voltage of A or the like is lowered.

2.2.4. Countermeasure by Decreasing Concentration of Source Diffusion Layer FIG. 36 is a cross-sectional structure diagram for explaining the effect when the countermeasure by reducing the concentration of the source diffusion layer is applied to the flash memories of FIGS. 30 and 35. It is shown. The outline and the characteristics of the source disturb countermeasure in the flash memory of this embodiment will be described with reference to FIG.

In FIG. 36, in the floating gate structure cell which constitutes the memory array MARY of the flash memory of this embodiment, at least the portion immediately below the floating gate FG of the N type diffusion layer serving as the source S thereof has a low concentration N. It is formed by the type diffusion layer N ⁻ . Therefore, paying attention to the non-selected memory cells MCA and the like, the negative potential V of −10 V is applied to the control gate CG during the write operation.
When N10 is applied and a bias voltage of +2 V, that is, the positive potential VP2 is applied to the source S thereof, the depletion layer DL is formed immediately below the floating gate FG, and the potential difference between the source and the floating gate is reduced.
As a result, extraction of the electrons accumulated in the floating gate FG to the source side can be suppressed, which can suppress a decrease in the threshold voltage of the non-selected memory cells MCA and the like.

3. Outline and problems of cross-point type flash memory and countermeasures 3.1. Overview of crosspoint flash memory 3.1.1. Configuration of Memory Array FIG. 37 is a partial circuit diagram of an embodiment of the memory array MARY included in the cross-point type flash memory to which the present invention is applied. Based on the figure,
An outline of the configuration and operation of the memory array MARY, which is a characteristic part of the cross-point type flash memory to which the present invention is applied, will be described. In this example,
The application examples of the measures shown in FIGS. 27 to 34 are given.

In FIG. 37, the memory array MARY of the flash memory of this embodiment includes a plurality of memory blocks, and these memory blocks are arranged in the horizontal direction as represented by the memory block MB0 in FIG. The m + 1 word lines W0 to Wm arranged, the n + 1 data lines B0 to Bn arranged in the vertical direction, and (m + 1) × (n + 1) arranged in a grid pattern at the intersections of these word lines and data lines. ) Floating gate structure cells MC
Including and respectively. Of these, the control gates CG of the n + 1 memory cells MC arranged in the same row of each memory block are commonly coupled to the corresponding word lines W0 to Wm.

On the other hand, the drains of m + 1 memory cells MC arranged in the same column of each memory block are integrated as common drain regions D0 to Dn, and these common drain regions D0 to Dn are N-channel MOSFETs.
It is coupled to corresponding data lines B0-Bn via Q1. Similarly, the sources of the m + 1 memory cells MC arranged in the same column of each memory block are integrated as common source regions S0 to Sn, and these common source regions S0 to Sn are connected via the N-channel MOSFET Q2. Are coupled to corresponding source lines SL0-SLn. MOS
The gate of the FET Q1 corresponds to the corresponding block selection line BSB.
0 and the like, and the gate of the MOSFET Q2 is commonly connected to the corresponding block select line BSS0 and the like.

Word lines W0 to Wm forming the memory array MARY and block selection lines BSB0 and BS and BS.
S0 and the like are coupled to an X address decoder XD (not shown). Further, the data lines B0 to Bn are not shown in Y
The read / write circuit RW is coupled through the switch YS, and the source lines SL0 to SLn are coupled to a source switch SS (not shown).

3.1.2. Operating Conditions of Each Mode FIG. 38 shows a selection condition diagram in the erase mode and the write mode of the memory array MARY of FIG. It should be noted that this selection condition chart shows the selection conditions of the same flash memory developed by the inventors of the present application prior to the present invention, and is provided to clarify the problem. In the flash memory to which the present invention is applied,
The same selection conditions are used except for a part, but the problems of the previously developed flash memory and the countermeasures against it will be explained in the later chapter.

The erase operation of this flash memory is performed in units of the word line of the designated memory block, that is, the selected memory block, and the selected word line to which the control gate of the selected memory cell to be erased of the selected memory block is connected. 38A, as shown in FIG. 38A, the positive potential VP having a relatively large absolute value such as + 15V.
15 are supplied. At this time, the block selection lines BSB0 and BSS0 of the selected memory block are still supplied with the positive potential VP15, and the unselected word lines to which the control gates of the unselected memory cells which are not to be erased in the selected memory block are coupled. , The ground potential GND is supplied. In addition, the ground potential GND is supplied to all the data lines B0 to Bn, and all the source lines SL0 to SLn.
Is also supplied with the ground potential GND. Needless to say, the ground potential GN is applied to all word lines, data lines, and source lines of the non-selected memory block which are not erase countermeasures.
D is supplied, and the block selection line also has the ground potential GND.
Is supplied.

As a result, in the n + 1 memory cells coupled to the selected word line of the selected memory block, electrons are injected from the semiconductor substrate to its control gate due to the FN tunnel phenomenon, thereby increasing its threshold voltage. It

Next, the write operation of the flash memory is performed in memory cell units, and the selected word line to which the control gate of the selected memory cell to be written in the specified selected memory block is coupled is shown in FIG. ), The negative potential VN10 having a relatively large absolute value such as −10 V is alternatively supplied. At this time, the positive potential VP5 such as + 5.0V is alternatively supplied to the selected data line to which the drain of the selected memory cell is coupled. Further, the ground potential GND is supplied to both the non-selected word line to which the control gate of the non-selected memory cell that is not the write target of the selected memory block is coupled and the non-selected data line to which the drain thereof is coupled,
The ground potential GND is supplied to all the source lines to which the sources of the selected and unselected memory cells are coupled. The ground potential GN is applied to all word lines, data lines, and source lines of the non-selected memory block that are not used for writing.
D is supplied, and the block selection line also has the ground potential GND.
Is supplied.

As a result, in the selected memory cell, the electrons accumulated in the floating gate of the selected memory cell are extracted to the drain side by the FN tunnel phenomenon, whereby the threshold voltage is selectively reduced.

3.2. Cause of write disturb and its countermeasure 3.2.1. Cause of Write Disturb FIG. 39 shows a connection diagram in the write mode of the flash memory of FIG. 38 developed by the present inventors prior to the present invention. The problem of the flash memory in FIG. 38, that is, the cause of the write disturb due to the data disturb will be described with reference to these drawings. In the connection diagram below, only the memory block MB0 to be written is representatively shown.

In the write mode of the flash memory developed by the inventors of the present invention prior to the present invention, as shown in FIGS. 38 and 39, the word line to which the control gate of the selected memory cell MD to be written is coupled. Negative potential VN10 of -10V is alternatively supplied to W0,
The positive potential VP5 of +5.0 V is selectively supplied to the data line B1 to which the drain is coupled, provided that the corresponding write data is logic "0". At this time,
Block select line BSB corresponding to memory block MB0
The positive potential VP15 is supplied to 0 and BSS0. Further, the ground potential GND is supplied to the word lines W1 to Wm to which the control gates of the non-selected memory cells that are not the write target of the memory block MB0 are coupled.
The ground potential G is also applied to the non-selected data lines B0 and B2 to Bn.
ND is supplied. In addition, all source lines SL0 to S
The ground potential GND is supplied to Ln.

From these things, first, the MOSFET Q1
And Q2 are turned on, the memory block MB0 is selected, and in the selected memory cell MD, the drain thereof is supplied with the positive potential VP5 and the control gate thereof is supplied with the negative potential VN10. The accumulated electrons are extracted to the drain side, and the threshold voltage is lowered. On the other hand, in a non-selected memory cell whose control gate is coupled to the selected word line W0 and its drain is coupled to the non-selected data line B0 or B2 to Bn, the drain is set to the ground potential GND, so that the FN tunneling phenomenon occurs. It does not occur and its threshold voltage does not change. Further, in a non-selected memory cell whose control gate is coupled to the non-selected word lines W1 to Wm and its drain is coupled to the non-selected data line, the control gate and the drain are set to the ground potential GND, so that the FN tunnel phenomenon also occurs. Does not occur.

However, in the non-selected memory cells ME to MF, the control gates of which are coupled to the non-selected word line W1 and the drains of which are coupled to the selected data line B1, the threshold voltage is low, that is, the write state. In this case, the drain coupling increases the potential of the floating gate to form a channel, the generated hot holes are injected into the floating gate, and the threshold voltage thereof is lowered. Further, when the threshold voltage is high, that is, in the erased state, electrons accumulated in the floating gate are extracted to the drain side by the FN tunnel phenomenon due to the potential difference between the drain and the floating gate. After all, the threshold voltage is lowered.

2.2.2. Measures by Applying Bias Voltage to Selected Source Line FIG. 40 shows a connection diagram of an embodiment in which measures are taken by applying a bias voltage to the selected source line in the write mode of the flash memory of FIG. ing. Based on the figure, the outline and the characteristics of the data disturb countermeasure of the flash memory to which the present invention is applied will be described.

In FIG. 40, in the write operation in the flash memory of this embodiment, the selected word line W0 connected to the control gate of the selected memory cell MD is
This is done by supplying a negative potential VN10 of 10V and a positive potential VP5 of + 5.0V to the selected data line B1 to which the drain is coupled. At this time, the ground potential GND is supplied to the non-selected data lines B0 and B2 to Bn. The positive potential VP is applied to both the block selection lines BSB0 and BSS0 of the selected memory block MB0.
15 are supplied.

However, in this embodiment, + is connected to the selected source line SL1 to which the source of the selected memory cell MD is coupled.
A bias voltage of 2V, that is, a positive potential VP2 is supplied.
The source of this bias voltage is the selected memory cell MD.
To increase the source potential of the non-selected memory cells ME to MF which are commonly coupled to each other to prevent a channel from being formed between the source and drain thereof and suppress the generation of hot holes,
It acts to suppress a decrease in the threshold voltage of these non-selected memory cells. As a result, the operation margin of the flash memory can be increased and its malfunction can be prevented.

As shown in the above embodiment, the present invention is applied to a semiconductor memory device such as a flash memory provided with a memory array in which floating gate structure cells are arranged in a grid pattern. The effect is obtained. That is, (1) In a flash memory or the like that includes a memory array in which floating gate structure cells are arranged in a grid pattern and the memory array is divided into blocks in the word line direction, the drain thereof is A first bias voltage whose absolute value is smaller than the selection level of the data line is applied to the source of the non-selected memory cell whose source is commonly coupled to the drain and whose source is not commonly coupled to the source of the selected memory cell. The effect of suppressing the data disturb and suppressing the decrease in the threshold voltage of the non-selected memory cell is obtained.

(2) In the flash memory of the above item (1), control of a non-selected memory cell whose drain is commonly coupled to the drain of the selected memory cell and whose source is not commonly coupled to the source of the selected memory cell during a write operation A region whose absolute value is smaller than the selected level of the data line and the gate current of the non-selected memory cell flows mainly under the influence of avalanche hot holes and the region where the gate current flows mainly under the influence of avalanche hot electrons. The second corresponding to the gate voltage that becomes the boundary value with
By applying the bias voltage of 1, the variation of the threshold voltage of the non-selected memory cell due to the data disturb between the memory blocks of different sizes can be suppressed. (3) In the flash memory according to the above item (1), at the time of an erase operation, the drain of the unselected memory cell whose drain is commonly coupled to the drain of the selected memory cell has an absolute value smaller than the selection level of the source line. By applying the third bias voltage, it is possible to obtain the effect of suppressing accelerated erase at the time of erase and suppressing erase variation of the memory cell.

(4) Both erase and write are FN
In a flash memory or the like performed by utilizing the tunnel phenomenon, during the write operation, the sources of the selected and non-selected memory cells and their control gates are not commonly coupled to the control gates of the selected memory cells. By providing the fourth bias voltage whose absolute value is smaller than the selection level of the data line, it is possible to suppress the data disturb during the write operation and suppress the decrease in the threshold voltage of the non-selected memory cell. can get. (5) In the above item (4), the drain of the memory cell is composed of a high-concentration diffusion layer, and at least the portion of the source immediately below the floating gate is composed of a low-concentration diffusion layer, whereby the selected and unselected memory cells are selected. Source disturbance due to the application of the fourth bias voltage to the source of the memory cell, and its control gate can be suppressed from lowering the threshold voltage of the non-selected memory cell coupled to the selected word line. can get.

(6) According to the above items (1) to (5), the block division unit of the memory array is compressed to improve the usability of the flash memory and reduce the average time required for writing, and Prevents inversion of retained information,
The effect that the reliability of the flash memory can be improved is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, in the sectional structure diagrams including FIG. 1, the specific device structure of the memory cell is not restricted by each embodiment. Further, in FIGS. 2 and 28, the logic levels of the retained information of the memory cells after erasing and after programming can be set by exchanging them with each other, and one or both of the threshold voltages of the memory cells can be set to a negative potential. It can also be set to. In FIG. 3, the number of word lines forming each memory block can be set arbitrarily, and the memory array MA
The RY may include a predetermined number of redundant word lines and redundant data lines. 4 and 30 and 38, the select and deselect levels of word and data lines and source lines are not constrained by these embodiments. In FIG. 5, the memory array MARY can be divided into memory blocks each having the same number of word lines as a unit. Further, the flash memory can input / output stored data in 1-bit units or 16-bit units, and the data input / output terminals D0 to D7 can be dedicated as data input terminals and data output terminals, respectively. The memory array MARY and its direct peripheral circuits can be divided into a plurality of memory mats. Furthermore, the block configuration of the flash memory, the combination of the activation control signal and the address signal, and the like can adopt various embodiments.

12 and 15 and 25, the specific level of the bias voltage applied to the non-selected source line, the non-selected word line and the data line can be set arbitrarily. In FIG. 33, the specific level of the bias voltage applied to the source line and the word line can also be set arbitrarily.

In the above description, the invention made by the present inventor was mainly applied to a flash memory incorporated in a single-chip microcomputer, which is the field of application of the background, but the invention is not limited thereto. Instead, for example, the present invention can be applied to a flash memory formed as a single unit or a gate array integrated circuit having a similar flash memory. The present invention can be widely applied to a semiconductor memory device including a memory array in which at least floating gate structure cells are arranged in a grid pattern, and a system including such a semiconductor memory device.

[0112]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a flash memory or the like that has a memory array in which floating gate structure cells are arranged in a grid pattern and the memory array is divided into blocks in the word line direction, its drain is shared by the drains of selected memory cells during a write operation. A source of an unselected memory cell that is coupled and whose source is not commonly coupled to the source of the selected memory cell is provided with a first bias voltage whose absolute value is less than the selected level of the data line, or its drain is the drain of the selected memory cell. A second bias voltage whose absolute value is smaller than the selected level of the data line is applied to the control gate of the non-selected memory cell whose common source is not commonly coupled to the source of the selected memory cell. Further, during the erase operation, a third bias voltage whose absolute value is smaller than the selection level of the source line is applied to the drain of the non-selected memory cell whose drain is commonly coupled to the drain of the selected memory cell. Furthermore, in a flash memory or the like in which both erasing and writing are performed by using the FN tunnel phenomenon, the sources of the selected and non-selected memory cells and their control gates are not commonly coupled to the control gates of the selected memory cells during the write operation. For the control gate of the selected memory cell,
A fourth bias voltage whose absolute value is smaller than the selection level of the data line is applied, the drain of the memory cell is composed of a high-concentration diffusion layer, and at least the part of the source immediately below the floating gate is composed of a low-concentration diffusion layer. To do. As a result, it is possible to suppress the data disturb during the write operation and the source disturb during the erase operation while compressing the block division unit of the memory array, and to suppress the decrease and variation in the threshold voltage of the memory cell. As a result, it is possible to improve the usability of the flash memory, shorten the average time required for writing, and prevent the inversion of the information held in the memory cell, thereby improving the reliability of the flash memory.

[Brief description of drawings]

FIG. 1 is a sectional structural view showing an embodiment of a floating gate structure cell that constitutes a memory array of a flash memory to which the present invention is applied.

FIG. 2 is a characteristic diagram showing an embodiment for explaining the relationship between the drain current and the gate-source voltage of the floating gate structure cell of FIG.

FIG. 3 is a partial circuit diagram showing an embodiment of a memory array including the floating gate structure cell of FIG.

FIG. 4 is a selection condition diagram before improvement of an erase mode and a write mode of the memory array of FIG.

5 is a block diagram illustrating an embodiment of a flash memory including the memory array of FIG.

FIG. 6 is a connection diagram when the source is grounded in the write mode of the flash memory of FIG.

FIG. 7 is a cross-sectional structure diagram for explaining the cause of data disturb in the flash memory of FIG.

8 is a connection diagram of the flash memory of FIG. 6 when a source is opened in a write mode.

9 is a cross-sectional structure diagram for explaining the cause of data disturb in the flash memory of FIG.

10 is a characteristic diagram for explaining the relationship between the leak current and the drain voltage when the source of the floating gate structure cell of FIG. 1 is grounded.

11 is a calculation diagram for explaining data disturb between memory blocks of different sizes in the flash memory of FIG. 5;

FIG. 12 is a connection diagram showing an embodiment after taking measures to apply a bias voltage to a non-selected source line in the write mode of the flash memory of FIG.

FIG. 13 is a cross-sectional structure diagram for explaining the effect of the measure in FIG.

FIG. 14 is a characteristic diagram for explaining the effect of the countermeasure of FIG.

FIG. 15 is a connection diagram showing an embodiment after taking measures to apply a bias voltage to a non-selected word line in the write mode of the flash memory of FIG.

16 is a cross-sectional structure diagram for explaining the effect of the measure in FIG.

FIG. 17 is a general characteristic diagram for explaining the relationship between the gate current and the gate voltage of a floating gate structure cell.

FIG. 18 is a sectional structural view for explaining a problem when the bias voltage of a non-selected word line is too low in the countermeasure of FIG.

FIG. 19 is a sectional structural view for explaining a problem when the bias voltage of a non-selected word line is too high in the countermeasure of FIG.

FIG. 20 is a characteristic diagram for explaining the effect of the countermeasure of FIG.

FIG. 21 is another characteristic diagram for explaining the effect of the measure in FIG.

22 is a connection diagram before improvement of the erase mode of the flash memory of FIG. 4. FIG.

FIG. 23 is a cross-sectional structural view for explaining the cause of erase disturb in the flash memory of FIG.

FIG. 24 is a characteristic diagram for explaining accelerated erase of the flash memory of FIG. 22.

25 is a connection diagram showing an embodiment after taking measures to apply a bias voltage to a data line in the erase mode of the flash memory of FIG. 4. FIG.

FIG. 26 is a cross-sectional structure diagram for explaining the effect of the measure in FIG. 25.

FIG. 27 is a cross-sectional structure diagram showing an example of a floating gate structure cell for erasing / writing by the FN tunnel phenomenon.

28 is a characteristic diagram showing an example for explaining the relationship between the drain current and the gate-source voltage of the floating gate structure cell of FIG. 27. FIG.

29 is a partial circuit diagram showing an embodiment of a memory array including the floating gate structure cell of FIG. 27. FIG.

30 is a selection condition diagram of the flash memory including the memory array of FIG. 29 before improvement of the erase mode and the write mode.

31 is a connection diagram of the flash memory of FIG. 30 in a write mode. FIG.

32 is a cross-sectional structural view for explaining the cause of data disturb in the flash memory of FIG.

33 is a connection diagram showing an embodiment after taking a measure to apply a bias voltage to a source line and a word line in a write mode of the flash memory of FIG. 30. FIG.

FIG. 34 is a cross-sectional structure diagram for explaining the effect of the measure in FIG. 33.

FIG. 35 is a cross-sectional structure diagram for describing problems when the measure of FIG. 33 is taken.

FIG. 36 is a cross-sectional structure diagram for explaining an effect when a measure for reducing the concentration of the source diffusion layer is applied to the flash memory of FIG. 35.

FIG. 37 is a partial circuit diagram showing one embodiment of a memory array including cross-point type cells.

38 is a selection condition diagram of a flash memory including the memory array of FIG. 37 before improvement.

39 is a connection diagram of the flash memory including the memory array of FIG. 37 before improvement of the write mode. FIG.

40 is a connection diagram after taking measures to apply a bias voltage to a selected source line in the write mode of the flash memory in FIG. 39. FIG.

[Explanation of symbols]

PSUB ... P-type semiconductor substrate, CG ... control gate, FG ... floating gate, IS1-
IS2 ... Insulating film, N ⁺ ... N-type high concentration diffusion layer, N
D1 to ND2 ... N type diffusion layer, S ... Source, D.
... drain, ^N - ··· ^N-type low-concentration diffusion layer, P ⁺ ··
-P-type high concentration diffusion layer. MARY ... Memory array, MBS0 to MBSp ...
・ Small capacity memory block, MBL0 to MBLq ... Large capacity memory block, MC ... Memory cell, WS00
~ WS015 to WSp0 to WSp15, WL00 to
WL01023 to WLq0 to WLq1023 ...
Word lines, B0 to Bn ... Data lines, SS0 to SS
p, SL0 to SLq ... Source lines. XD ... X address decoder, XB ... X address buffer, YS ... Y switch, YD ... Y address decoder, SS ... Source switch, YB ... Y
Address buffer, RW ... Read / write circuit, TG
... Timing generator circuit. MCA to MCH ... Memory cells. CH ・ ・ ・ Channel, Cs ・ ・ ・ Source capacity, Cd ・
..Drain capacitance IS3 to IS4 ... Insulating film, ND3 to ND4 ... N
Type diffusion layer. W0 to Wm ... word lines, SL0 to SLn ... source lines. DL ... Depletion layer. MB0 ... Memory block, D0-Dn ... Common drain region, S0-Sn ... Common source region, Q1-
Q2 ... N-channel MOSFET. MA to MF ... Memory cells.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical indication location H01L 29/792 7210-4M H01L 27/10 434 29/78 371 (72) Inventor Kenichi Kuroda Tokyo 5-20-1 Kamimizuhonmachi, Kodaira-shi Ltd. Within the Semiconductor Business Division, Hitachi, Ltd. (72) Inventor Masaaki Terasawa 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hitsuritsu Super S.I. Engineering Co., Ltd. In the company

Claims (10)

[Claims] 1. A non-volatile memory cell of floating gate structure type is provided with a memory array, which is arranged in a grid pattern, and the drain of which is commonly coupled to the drain of the selected memory cell and the source of which is the selected memory during a write operation. First to the sources of unselected memory cells that are not commonly coupled to the sources of the cells
A semiconductor memory device characterized by being supplied with a bias voltage. 2. The memory array is divided into a plurality of memory blocks in units of a predetermined number of memory cells coupled to a predetermined number of word lines, and a predetermined number of memories forming these memory blocks. The sources of the cells are commonly coupled to the corresponding source lines, and the selection level of the word line is the first level during the write operation.
And the selection level of the data line is a second positive potential whose absolute value is smaller than the first positive potential, and the selection level of the source line and the non-selection level of the word line and the data line are the ground potential. 2. The semiconductor according to claim 1, wherein the level of the first bias voltage is a third positive potential whose absolute value is smaller than the second positive potential. Storage device. 3. A non-volatile memory cell of floating gate structure type is provided with a memory array, which is arranged in a grid pattern, and has a drain commonly connected to a drain of a selected memory cell and a source thereof selected memory during a write operation. A semiconductor memory device, wherein a second bias voltage is applied to a word line of a non-selected memory cell which is not commonly coupled to a cell source. 4. The memory array is divided into a plurality of memory blocks in units of a predetermined number of memory cells coupled to a predetermined number of word lines, and a predetermined number of memories forming these memory blocks. The sources of the cells are commonly coupled to the corresponding source lines, and the selection level of the word line is the first level during the write operation.
Of the data line and the selection level of the data line is a second positive potential whose absolute value is smaller than the first positive potential, and the selection level of the source line and the memory block including the data line and the selected memory cell are The non-selection level of the other word lines is set to the ground potential, and the source line is opened in the non-selection state. The absolute value of the second bias voltage level is higher than that of the second positive potential. 4. The semiconductor memory device according to claim 3, wherein the semiconductor memory device has a small fourth positive potential. 5. The fourth positive potential is applied to a region in which a gate current of a non-selected memory cell is caused to flow mainly under the influence of avalanche hot holes and a region to be caused to flow mainly under the influence of avalanche hot electrons. 5. A gate voltage corresponding to a boundary value, which corresponds to the gate voltage.
Semiconductor memory device. 6. A non-selected memory cell having a memory array in which floating gate structure type non-volatile memory cells are arranged in a grid pattern, and the drain of which is commonly coupled to the drain of the selected memory cell during an erase operation. A semiconductor memory device, wherein a third bias voltage is applied to the drain of the. 7. The memory array is divided into a plurality of memory blocks in units of a predetermined number of memory cells coupled to a predetermined number of word lines, and a predetermined number of memories forming these memory blocks. The sources of the cells are those commonly coupled to the corresponding source lines,
The erase operation is performed in units of the memory block. During the erase operation, the source line selection level is set to the first positive potential, and the source line non-selection level and word line selection level The non-selection level is a ground potential, and the level of the third bias voltage is a fifth positive potential whose absolute value is smaller than the first positive potential. The semiconductor memory device according to claim 6. 8. A memory array comprising nonvolatile memory cells of a floating gate structure, which are erased and programmed by utilizing the Fowler-Nordheim tunnel phenomenon, are arranged in a grid pattern, and are selected during a write operation. A semiconductor memory device, wherein sources of memory cells and non-selected memory cells and control gates thereof are not commonly coupled to control gates of selected memory cells, and a fourth bias voltage is applied to the control gates of non-selected memory cells. 9. The control gates of the memory cells arranged in the same row of the memory array are commonly coupled to corresponding word lines, and the sources and drains of the memory cells arranged in the same column of the memory array are , The corresponding source line and the data line are commonly coupled, and the selection level of the word line is set to the first negative potential during the write operation, and the absolute value of the selection level of the data line is the above-mentioned first value. The sixth positive potential smaller than the negative potential of 1 is set, and the non-selection level of the data line is set to the ground potential.
9. The semiconductor memory device according to claim 8, wherein the level of the fourth bias voltage is set to a seventh positive potential whose absolute value is smaller than the sixth positive potential. 10. The drain of the memory cell comprises a high concentration diffusion layer, and the source thereof comprises a low concentration diffusion layer at least immediately below the floating gate. 9. A semiconductor memory device.