JPH0660679A - Nonvolatile semiconductor storage - Google Patents

Abstract

PURPOSE:To provide a nonvolatile semiconductor storage adapted to be highly integrated in which an erasing voltage can be applied at a byte column unit. CONSTITUTION:A plurality of byte columns 10 including predetermined number of storage cells are arranged in a cell array 201. A transistor 1 is connected between a source line 30 of each column 10 and a source potential generator 203 and is controlled to be conductive or non-conductive. The generator 203 generates an erasing voltage, applies the erasing voltage to the line 30 connected with the transistor 1 when the transistor 1 is conductive, and does not apply and voltage to the line 30 connected with the transistor 1 when the transistor 1 is non-conductive.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically erasable and writable nonvolatile semiconductor memory device (Electrically E
rasable and Programmable Read Only Memory: EE
PROM), and particularly to an EEPROM device capable of erasing data in byte units.

[0002]

2. Description of the Related Art EEPROM is an electrically erasable and writable read-only memory device.
A conventional flash type EEPROM (hereinafter referred to as a flash memory) will be described below.

FIG. 13 is a schematic block diagram of a general flash memory. The flash memory shown in FIG. 13 is equivalent to the IEEE Journal of Solid-State Circuits,
Vol.23, No.5, October 1988.p.1157 to 1163.

Referring to FIG. 13, memory cell array 30
1, the Y gate 302, the source line switch 30
3, an X decoder 304 and a Y decoder 305 are provided. Address registers 306, a write circuit 307, a sense amplifier 308, an input / output buffer 309, a program voltage generation circuit 310, a verify voltage generation circuit 311, and a command register 31 are further provided around them.
2, a command decoder 313 and a control circuit 314 are provided. Flash memory contains these circuits. The memory cell array 301 has a plurality of memory cells (not shown) arranged in a matrix therein. An X decoder 304 and a Y gate 302 are connected to the memory cell array 301. The Y decoder 3 connected to the X decoder 304 and the Y gate 302
Reference numeral 05 plays a role of selecting rows and columns of the memory cell array 301. A source line switch 303 is connected to the memory cell array 301. The source line switch 303 plays a role of applying an erase voltage when erasing a memory cell in the memory cell array 301. The Y-gate 302 is connected to a Y-decoder 305 that gives column selection information. X decoder 304
An address register 306 is connected to the Y decoder 305. The address register 306 plays a role of inputting an address signal externally input to the X decoder 304 and the Y decoder 305. A write circuit 307 and a sense amplifier 308 are connected to the memory cell array 301 via a Y gate 302. An input / output buffer 309 for temporarily storing input / output data is connected to the write circuit 307 and the sense amplifier 308. Program voltage generator 310 and the verify voltage generating circuit 311 generates a voltage different from the power supply V _cc, V _pp supplied from outside, forms a role of supplying this voltage such as Y gates 302, X decoder 304 There is. Command register 312 and command decoder 3
Reference numeral 13 serves to set the operation mode of the flash memory according to data input from the outside. The control circuit 314 uses external control signals / WE, / CE,
It plays the role of giving / OE. Regarding the description of / WE and the like, the symbol "/" indicates the inversion of the signal WE and the like. Hereinafter, “/” is used to indicate the inversion of the signal.

Next, the configuration of the memory cell array 301 provided in the above flash memory will be described in detail.

FIG. 14 is a diagram showing a structure of a memory cell array in a conventional flash memory. Referring to FIG. 14, the memory cell array 301 includes an X decoder 30.
4 to a predetermined number of word lines 340 are arranged in the column direction. Also, a predetermined number of bit lines 3 from the Y gate 302
50 are arranged in the row direction. A memory cell 320 is formed in the memory cell 301 near the intersection of the word line 340 and the bit line 350. The memory cell 320 is a floating gate type transistor (hereinafter referred to as a floating gate transistor). The floating transistor 320 has a control gate connected to the word line 340 and a drain connected to the bit line 350. The sources of the floating gate transistors 320 are connected to each other, bundled in the memory cell array, and connected to the source line switch 303.

A transistor 302a for selecting each bit line is provided in the Y gate 302. The source or drain of the transistor 302a is connected to each bit line 350. The gate of the transistor 302a is connected to the Y decoder 305. Each bit line 350 is connected to the write circuit 307 and the sense amplifier 308 via the transistor 302a.

Next, the structure of the memory cells arranged in the conventional memory cell array will be described in detail.

FIG. 15 shows a conventional flash memory.
The configuration of the memory cells arranged in the memory cell array
It is sectional drawing which shows schematically. Referring to FIG. 15, memory
The cell is a floating gate transistor. sand
That is, on the surface of the p-type silicon (Si) substrate 321,
n-type impurity region, for example n⁺Drain diffusion region 32
2 and n⁺Via the source diffusion region 323 with a predetermined distance
Has been formed. These n⁺Drain diffusion region 322
n⁺The channel region is formed in the region sandwiched by the source diffusion regions 323.
A floating gate electrode 325 to form a region
A control gate electrode 327 is formed. This
Floating gate electrode 325 and control gate
The gate electrode 327 is formed of a polycrystalline silicon layer.
Floating gate electrode 325 and silicon substrate 321
In between, a gate oxide film (SiO 2 ₂) 324 is formed
ing. The thickness of the gate oxide film 324 is about 100Å
Is. For this reason, the floating
The electrons of the long gate electrode 325 can move. Flow
Gate electrode 325 and control gate electrode
An oxide dielectric film 326 is formed between 327.
It This oxide dielectric film 326 allows the floating
The gate electrode 325 and the control gate electrode 327 are electrically
Are separated. Thus, the memory cell 320
It is configured.

Next, the operation of the memory cell 320 shown in FIG.
Describe the work. Referring to FIG. 15, first write
Sometimes n⁺About 6.5 V is applied to the drain diffusion region 322.
The program voltage is applied. Also, control game
V to the electrode 327_pp(12V) is given, n⁺Saw
The diffusion region 323 is grounded. This allows the memory
N is turned on,⁺Drain diffusion region 322
And n⁺A current flows between the source diffusion regions 323. this
When n⁺Avalanche near the drain diffusion region 322
The breakdown phenomenon is caused. Therefore, n
⁺Electron-hole pairs are generated near the drain diffusion region 322.
To live. The holes are at ground potential through the silicon substrate 321.
, The electrons flow in the channel direction and n⁺Drain diffusion
It flows into the area 322. Some of this electron is floating
Gate electrode 325 and n⁺Drain diffusion region 322
Floating gate electrode being accelerated by the electric field between
325. Floating like this
When electrons are accumulated in the gate electrode 325, the memory
Threshold voltage V of cell 320_thBecomes higher. This threshold
Value voltage V_thIs higher than the specified value, the
It is defined as a record of the state "0" that has been opened.

At the time of erasing, n⁺Drain diffusion region 3
22 is opened. Control gate
The electrode 327 is grounded and n⁺The source diffusion region 323 is electrically charged.
Pressure V _ppIs applied. This gives n⁺Source diffusion area
Potential between 323 and floating gate electrode 325
There is a difference. Due to this potential difference, a tunnel phenomenon occurs,
The attraction of electrons accumulated in the floating gate electrode 325
Withdrawal occurs. In this way, the memory cell 320
Threshold voltage V_thIs lower than a predetermined value. this
Threshold voltage V_thIs lower than the specified value,
It is defined as the memory of the erased state "1".

Further, at the time of reading, a voltage of about 5 V is applied to the control gate electrode 327 and a voltage of about 1 to 2 V is applied to the n ⁺ drain diffusion region 322. At this time, the determination of "1" or "0" is made depending on whether or not a current flows in the channel region of the memory cell 320, that is, whether the memory cell 320 is in the on state or the off state.

Next, the memory cell 3 which operates as described above
An operation of the conventional flash memory shown in FIG. 14 in which 20s are arranged will be described.

Referring to FIG. 14, the operation of writing data into the memory cell 320 surrounded by the dotted line will be described. According to the data input from the outside, the writing circuit 3
07 is activated and a program voltage is supplied to the I / O line 370. At the same time, the Y decoder 3 is driven by the address signal.
05 through X-decoder 304 and Y-gate 302
a, the word line 340 is selected. As a result, the voltage V _pp is applied to the control gate electrode of the memory cell 320 surrounded by the dotted line. A program voltage is applied to the drain of the memory cell 320 surrounded by the dotted line. The source line 330 is grounded by the source line switch 303. Therefore, the memory cell 3 surrounded by the dotted line
The source of 20 is grounded. In this way, a current flows only in the memory cell 320 surrounded by the dotted line, hot electrons are generated, the hot electrons are accumulated in the floating gate of the selected memory cell 320, and the threshold voltage V _th thereof is stored. Becomes higher. That is, the memory cell 320 is in the written state “0”.

Next, the operation for erasing data will be described. First, the X decoder 304 and the Y decoder 305 are deactivated. As a result, all memory cells are deselected. That is, the control gate of each memory cell is grounded and the drain is open. A high voltage is applied to the source line 330 by the source line switch 303. As a result, a tunnel phenomenon occurs, and the threshold voltage V of all memory cells is increased.
_th shifts to a lower value than a predetermined value. That is, all the memory cells 320 are in the erased state “1”. As described above, all the memory cells arranged in the memory cell array 301 share the source line 330, so that all the memory cells are collectively erased at the time of erasing.

Next, the operation of reading data from the memory cell 320 surrounded by the dotted line will be described. First, the address signal is decoded by the Y decoder 305 and the X decoder 304. As a result, the selected Y gate 302a and word line 340 become "H". At this time,
The source line 330 is grounded by the source line switch 303. In this state, the memory cell 320 surrounded by the dotted line
Is in a written state (that is, a state in which the threshold voltage V _th is high), the memory cell 320 surrounded by the dotted line.
Even if a "H" level signal is applied from the word line 340 to the control gate of the memory cell, the memory cell is not turned on. Therefore, no current flows from the bit line 350 to the source line 330. When the memory cell 320 surrounded by the dotted line is in the erased state (that is, the threshold voltage V _th is low), the control gate of the memory cell 320 surrounded by the dotted line extends from the word line 340 to “H”. When the level signal is given, the memory cell 320 surrounded by the dotted line is turned on. Therefore, a current flows from the bit line 350 to the source line 330. Thus, the memory cell 3 surrounded by the dotted line
Sense amplifier 308 determines whether or not a current flows through 20.
To detect. As a result, the memory cell 32 surrounded by the dotted line
Read data "1" or "0" of 0 is obtained.

As described above, the operations of the conventional flash memory at the time of writing, erasing and reading are performed.

[0018]

In the conventional flash memory as described above, the source lines of all the memory cells are bundled in the memory cell array 301. Therefore, even when rewriting a 1-byte memory cell, it is necessary to erase all the memory cells and then reprogram them. In this way, the conventional flash memory requires a long time even for slight rewriting,
Moreover, there is a problem that it requires a lot of labor.

A flash memory for solving the above problems is disclosed in Japanese Patent Laid-Open No. 61-127179. The above-mentioned patent documents disclose a technique capable of erasing the memory cell array in byte units in the erase operation. The configuration in the memory cell array disclosed in the above patent document will be described below.

FIG. 16 is a circuit diagram schematically showing the configuration in the memory cell array disclosed in the patent document. FIG.
Referring to FIG.
It consists of zero. In the memory cell array, a predetermined number of word lines 440 from the row address combiner 404 are arranged in each row. Also, a predetermined number of bit lines 450 from the column address decoding circuit 405 are arranged in each column. A memory cell 420 is formed near the intersection of the word line 420 and the bit line 450. This memory cell 420 is a floating gate transistor, and its structure is similar to that shown in FIG. The control gate of the memory cell 420 is the word line 440.
And the drains are connected to the bit lines 450, respectively. The sources of the memory cells 420 are connected to each other in units of two rows. That is, the sources of the plurality of memory cells 420 arranged in two adjacent rows are all commonly connected. The sources of the commonly connected memory cells 420 are connected to the source line 430 via the two transistors 431. One of the gates of the two transistors 431 has a pair of word lines 440.
Is connected to one side. Also, the other transistor 4
The gate of 31 is connected to the other of the pair of word lines 440. The source line 430 is connected to the source decoder 403.

A column address signal for selecting the bit line 450 is applied to the column address decoding circuit 405. The column address decoding circuit 405 for inputting or outputting data has an input buffer 4
18 or the sense amplifier 417 and the output buffer 416 are connected. The source decoder 403, the row address decoder 404, and the column address decoding circuit 405 are the source line switch 303 and the X decoder 30 shown in FIG. 12, respectively.
4 and Y gate 302.

Next, the operation of the flash memory having the memory cell structure shown in FIG. 16 will be described.

Referring to FIG. 16, when writing first,
According to the data input from the outside, the input buffer 41
8 is activated. At the same time, the column address decoding circuit 405 selects the bit line BL1. As a result, the program voltage is supplied to the selected bit line BL1. On the other hand, the row address signal selects the word line WL1 via the row address decoder 404. As a result, the program voltage is applied to the control gate of the floating gate transistor 420 located at the intersection of the bit line BL1 and the word line WL1. In addition, the transistor 431 arranged in the word line WL1 is also turned on. When the transistor 431 is turned on, the sources of the floating gate transistors 420 arranged in the word lines WL1 and WL2 are grounded by the source decoder 403 via the source line 430. Writing is performed by selecting a memory cell in this manner.

When erasing, the source decoder 4
An erase voltage is applied to the source line 430 by 03. A voltage is applied to word line WL2 through row address decoder 404. The word line WL1 is grounded. This turns on the transistor 431 whose gate is connected to the word line WL2. Therefore, the source line 430 is connected to the sources of the memory cells arranged on the word lines WL1 and WL2. Therefore, the erase voltage is applied to the sources of the memory cells arranged in the word lines WL1 and WL2. As a result, in the memory cells arranged on the word line WL1, the erase voltage is applied to the source, so that the data is erased.
On the other hand, the memory cells arranged on the word line WL2 are
Erase is blocked because a voltage is applied to the control gate. That is, the memory cell having the control gate connected to the word line WL1 is erased, but the memory cell having the control gate connected to the word line WL2 is not erased. In this way, by applying the voltage to only one of the pair of adjacent word lines,
The memory cell arranged on the other word line can be erased. Therefore, the memory cells can be erased in byte units.

Further, at the time of reading, the word line 440 is selected. As a result, the transistor 431 whose gate is connected to the word line 440 is turned on. Therefore, the sources of the memory cells arranged in the selected word line 440 are grounded, and the memory cells can be read.

As described above, the flash memory having the memory cell structure shown in FIG. 16 can erase the memory cells in byte units. However, this flash memory has the following problems.

Referring to FIG. 16, a signal applied from select line 490 generally controls whether source decoder 403 generates an erase voltage. However, in the above patent document, only one selection line 490 is shown, and only one source decoder 403 is shown. In this case, it can be considered that the source decoder 403 is not provided with the means for selecting each block 410 and applying the erase voltage, or is provided with the means. In this case, the source decoder 403 generates an erase voltage according to the signal supplied from the select line 490. This erase voltage will be applied to all blocks 410 connected to the source decoder 403. Here, a block is an aggregate of memory cells controlled by one source line. On the other hand, each block 410 shares a word line. That is, memory cells arranged in the same row of one block 410 and another block 410 are controlled by the same word line. Therefore, when the word line WL1 is selected while the erase voltage is applied, all the memory cells arranged on the word line WL2 paired with the word line WL1 are erased. That is, not all the memory cells arranged in the word line WL2 are erased in each block 410, but all the memory cells arranged in the word line WL2 are erased in all the blocks 410. As described above, when the number of the column selection lines 490 and the number of the source decoders 403 are each one, the memory cells arranged in the same word line cannot be selected in the unit of block 410 at the time of erasing.

In this case, even if the source decoder 403 selects each block 410 and applies the erase voltage, no means for realizing this is disclosed.

Next, a case will be described in which it is assumed that there are a plurality of selection lines 490 in the structure of the flash memory shown in FIG.

FIG. 17 is a schematic block diagram of the memory cell array and its peripheral portion in the case where the flash memory shown in FIG. 16 has a plurality of selection lines. Referring to FIG. 17, since there are a plurality of selection lines 490 corresponding to the number of blocks 410, it is possible to send a signal corresponding to each block 410. In order to select each block 410 according to such a plurality of signals and apply the erase voltage, it is necessary to provide the source decoder 403 corresponding to each block 410. As described above, by providing the selection lines 490 and the source decoders 403 by the number corresponding to the block 410, it becomes possible to select each block 410 and apply the erase voltage. However, in this case, the following adverse effects occur.

FIG. 18 is a schematic layout diagram of the memory cell array and its periphery corresponding to FIG. Referring to FIG. 18, generally, the source potential generating circuit such as the source decoder 403 is composed of a plurality of elements such as transistors. Therefore, the area occupied by the source decoder 403 is
It is almost the same as the area occupied by the Y gate 405a. That is, the source potential generation circuit formation region 503 has an area equal to that of the column address decoding circuit formation region 502, and the arrow M ₁
The dimension in the direction is equal to that of the memory cell array region 501, and the dimension in the direction of the arrow N ₁ is about 2% of the memory cell array region 501. The area of the Y gate 405a forming the column address decoding circuit formation area 502 is very dense with transistors for selecting each bit line. Therefore, the column address decoding circuit forming area 50
It is impossible to incorporate the source potential generation circuit formation region 503 in the second region. Therefore, the source potential generation circuit formation region 503 must be formed outside the column address decoding circuit formation region 502. Since the source potential generating circuit formation region 503 having such a region must be provided separately from the column address decoding circuit formation region 502, the memory cell array region 501 or other peripheral circuits are greatly restricted. Therefore, the memory cell array region 501
However, it is difficult to achieve high integration.

The present invention has been made to solve the above problems, and provides a non-volatile semiconductor memory device suitable for high integration in which an erase voltage can be applied in byte column (block) units. With the goal.

[0033]

A non-volatile semiconductor memory device of the present invention is a non-volatile semiconductor memory device in which data can be erased in units of bytes, and which can be electrically erased and written. A block selection means and an erase voltage generation means are provided. In the memory array, a plurality of memory blocks including a predetermined number of memory cells are arranged. The memory block selection means is connected to each of the memory blocks and has a conductive state and a non-conductive state for selecting one of the memory blocks. The erase voltage generating means applies the erase voltage to the memory block to which the erase voltage is generated and which is connected to the memory block selecting means in the conductive state, and is connected to the memory block selecting means in the non-conductive state. The memory block is connected to the memory block selection means so that the erase voltage is not applied to the memory block.

[0034]

In the nonvolatile semiconductor memory device of the present invention, the memory block selection means has a conductive state and a non-conductive state,
When in the conductive state, the erase voltage generated by the erase voltage generating means is applied to the memory block, and in the non-conductive state, the erase voltage is not applied to the memory block. In this way, the erase voltage generated by the erase voltage generating means can be selectively applied to the memory block. Therefore, the erase voltage is applied to the selected memory block, but the erase voltage is not applied to the non-selected memory block. Therefore, even if the bytes of each memory block share the word line, it is possible to erase only the bytes of the selected memory block. Thus, by providing the memory block selection means,
Even with one erase voltage generating means, it becomes possible to selectively apply the erase voltage to each memory block. Since the memory block selection means is controlled by the signal of the Y decoder which selects the bit line, it is not necessary to newly provide a signal for making the memory block selection means conductive or non-conductive. Further, since only one erase voltage generating means is required,
The formation area of the erase voltage generating means can be made smaller than in the case where a plurality of erase voltage generating means corresponding to each byte string are provided.

Further, in the present invention, the memory block selecting means is provided by the number corresponding to the memory blocks. This memory block selecting means can be composed of, for example, one transistor, and its structure is simple. Therefore, the memory block selection means can be formed in a smaller area than the erase voltage generation means composed of a plurality of elements such as transistors. Therefore, it can be formed in a region such as a Y gate.

As described above, since the erase voltage generating means is one and the memory block selecting means is provided instead, the area for forming these can be made small, and the memory area can be expanded by that amount to achieve high integration. Is possible.

[0037]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A flash memory according to an embodiment of the present invention will be described below.

FIG. 1 is a schematic layout diagram of a memory cell array and its periphery in one embodiment of the present invention. Referring to FIG. 1, the memory cell array region 201 includes a plurality of byte columns 10. A Y gate 60 is formed so as to correspond to each byte string 10 with a wiring region 201a interposed. Here, the wiring region is a region provided in consideration of forming a wiring for electrically connecting the elements. The region where the Y gate 60 is formed is the Y gate formation region 202. A transistor 1 which is a memory block selecting means is formed in or near the Y gate forming region 202 corresponding to each byte string 10. The source potential generating circuit 2 is provided with the transistor 1 and the wiring region 203a interposed therebetween.
03 are arranged. The region where the source potential generating circuit is formed is the source potential generating circuit forming region 203. The source potential generation circuit 203 is composed of a plurality of elements such as transistors. Therefore, the size of the source potential generation circuit formation region 203 is one byte string 1
It is about the same size as the Y gate 60 corresponding to 0. The dimension of the Y gate 60 in the arrow M ₂ direction is substantially the same as the dimension of the corresponding bit string 10 in the arrow M ₂ direction. The Y gate forming region 202 and the byte string 10
Corresponds to the column address decoding circuit forming area 502 and the block 410 in FIG.

FIG. 2 is a block diagram corresponding to the layout shown in FIG. Referring to FIG. 2, in each byte string 10,
It has a predetermined number of word lines arranged in each row and a predetermined number of bit lines arranged in each column. Each byte string 10 shares a word line. Ie 1
The memory cells arranged in the same row of the block 410 and another block 410 are controlled by the same word line. The bit line of each byte string 10 has a Y gate 6
It is connected to 0. The bit line of each byte string 10 is selected by the Y gate 60 and a Y decoder (not shown). The source line of each byte string 10 is connected to the source potential generation circuit 203 via the transistor 1. The gate of the transistor 1 is controlled by a signal controlling the Y gate 60. Source potential generation circuit 2
A selection line 290 is connected to 03. The source potential generating circuit 203 corresponds to the source decoder 403 in the case where the block selecting means is not included in FIG.

Next, the structure of the memory cell array employed in the flash memory in the embodiment of the present invention will be described.

FIG. 3 is a circuit diagram schematically showing the configuration of a memory cell array used in the flash memory in one embodiment of the present invention. FIG. 4 is a schematic view showing a state in which a plurality of byte strings shown in FIG. 3 are formed. Figure 3
4, the memory cell array is composed of a plurality of byte strings 10. The number of Y gates 60 corresponding to the byte string 10 is provided. In the byte string 10, a predetermined number of word lines 41 from the X decoder 204,
42 are arranged in each row. From the Y gate 60, a predetermined number, for example, eight bit lines 51 to 58 are arranged in each column. Further, one source line 30 is arranged for one byte string 10 in parallel with the bit line. The source line 30 includes eight bit lines 5
It is located in the center of 1-58. That is, the source line 3
Four bit lines are arranged on each of the left and right with 0 interposed therebetween.

Memory cells are formed near the intersections of a predetermined number of word lines 41, 42, ... And bit lines 51-58. This memory cell has the same structure as the floating gate transistor shown in FIG. The control gate of the memory cell is the corresponding word line 4
1, 42, ... The drain corresponds to the bit line 51
To 58 respectively. Further, the sources of the memory cells arranged in two adjacent rows are commonly connected by a sub-source line formed of a diffusion region. A pair of transistors 31 and 32 are interposed between the sub-source line and the source line 30 for the sources of the commonly connected memory cells. The gate of the transistor 31 is connected to the word line WL1. Also, the other transistor 3
The gate of 2 is connected to the word line WL2.

Each bit line 51-58 has a Y gate 6
It is connected to the corresponding I / O line (input / output line) 70 via the transistors 61 to 68 forming 0. Further, a predetermined number of transistors 61 forming the Y gate 60
The gates 68 to 68 are connected to each other by the wiring 105. The wiring 105 is connected to the Y decoder 205.
The wiring 105 is provided corresponding to each Y gate 60. The transistor 1 is interposed between the source line 30 and the source potential generation circuit 203. The transistor 1 is formed in the formation region of the Y gate 60. The gate of the transistor 1 has a wiring 105.
And is controlled by the Y decoder 205. The erase voltage generated by the source potential generation circuit 203 is applied to each byte string 10 forming the memory cell array by the global source line 80 via the transistor 1. That is, if the transistor 1 is conductive, the erase voltage is applied to the byte string 10 having the source line 30 to which the transistor 1 is connected. On the other hand, if the transistor 1 is non-conductive, the erase voltage is not applied to the byte string 10 having the source line 30 connected to the transistor 1. Also,
The source potential generation circuit 203 is controlled by the selection line 90 whether or not the erase voltage is generated. Note that the I / O lines are omitted in FIG. 4 for simplification.

FIG. 5 is a plan view schematically showing the structure of a memory cell array and a Y gate adopted in the flash memory in one embodiment of the present invention. Referring to FIG. 5, in Y gate 60, a predetermined number of transistors 1 and 61 to 68 are arranged on the left and right with wiring 105 interposed therebetween. In the byte string 10, the floating gate transistors 11 to 18, which are a predetermined number of memory cells,
21 to 28 and transistors 31 and 32 are word lines 4
1, 42 are arranged. The byte string 10
For the sake of simplicity, only a part is shown.

Next, the structure of the transistor 1 shown in FIG. 5 will be described in detail. FIG. 6 is a sectional view taken along the line AA of FIG. Referring to FIGS. 5 and 6, the silicon substrate 1
An isolation oxide film 102 is formed on the surface of 01.
Silicon substrate 1 separated by this separation oxide film 102
The transistor 1 is formed on the surface of 01. That is, on the surface of the silicon substrate 101, a pair of n ⁺ impurity nucleic acid regions 103 to become a source region and a drain region are formed.
Are formed with a predetermined interval. A gate electrode 105 is formed on the surface of the region sandwiched by the pair of impurity diffusion regions 103 with a gate oxide film 104 interposed. The pair of n ⁺ impurity diffusion regions 103, the gate insulating film 104, and the gate electrode 105 form the transistor 1
Is configured. To cover this transistor 1,
The interlayer insulating film 106 is formed. This interlayer insulating film 1
A contact hole 106a is formed at 06. From this contact hole 106a, a pair of n ⁺
Part of the surface of the impurity diffusion region 103 is exposed. A wiring layer 30 to be a source line is formed so as to contact a part of the surface of one exposed n ⁺ impurity diffusion region 103. Further, wiring layer 30a is formed in contact with the exposed surface of the other n ⁺ impurity diffusion region 103.

Next, the structure of the memory cell 16 shown in FIG. 5 will be described in detail. FIG. 7A is a sectional view taken along the line BB of FIG. Further, FIG. 7B shows CC of FIG.
It is sectional drawing which follows the line.

First, referring to FIGS. 5 and 7A, the n ⁺ drain diffusion region 11 is formed on the surface of the silicon substrate 101.
3a and n ⁺ source diffusion region 113b are formed with a predetermined interval. This n ⁺ drain diffusion region 113a
A floating gate electrode 115 is formed on the surface of the region sandwiched by the n ⁺ source diffusion region 113b with a gate oxide film 114 interposed. Control gate electrodes (word lines) 41, 42 are formed on the surface of the floating gate electrode 115 via an oxide dielectric film 116.
Are formed. Thus, the n ⁺ drain diffusion region 113a, the n ⁺ source diffusion region 113b, the floating gate electrode 115, the control gate electrodes 41, 4
Floating gate transistors 16 and 2
6 are configured. An interlayer insulating film 118 is formed so as to cover the floating gate transistors 16 and 26. A contact hole 118a is formed in the interlayer insulating film 118. Contact hole 118
From a, floating gate transistors 16 and 2
Part of the surface of the n ⁺ drain diffusion region 113a of No. 6 is exposed. A wiring layer (bit line) 56 is formed so as to contact a part of the exposed surface of the n ⁺ drain diffusion region 113a.

Next, referring to FIGS. 5 and 7B, an isolation oxide film 102 is formed on the surface of the silicon substrate 101. The surface of the silicon substrate 101 is separated by this separation oxide film 102. A gate oxide film 114 is formed on the surface of the silicon substrate 101 where the isolation oxide film 102 is not formed. A floating gate electrode 115 is formed on the surface of the gate electrode 114 so as to partially ride on the isolation oxide film 102.
A control gate (word line) 41 is formed on the surface of the floating gate electrode 115 with an oxide dielectric film 116 interposed. The layers above the control gate 41 are omitted for simplification.

Next, the transistors 31 and 32 shown in FIG.
The configuration will be described in detail. FIG. 8A is a sectional view taken along the line DD of FIG. Further, FIG. 8B is a sectional view taken along the line EE of FIG.

First, referring to FIGS. 5 and 8A, on the surface of silicon substrate 101, n ⁺ drain diffusion region 113 is formed.
The a and n ⁺ source diffusion regions 113b are formed with a predetermined interval. Gate electrodes (word lines) 41 and 42 are formed on the surface of the region sandwiched between n ⁺ drain diffusion region 113a and n ⁺ source diffusion region 113b with gate oxide film 114 interposed. The n ⁺ drain diffusion region 113a, the n ⁺ source diffusion region 113b, the gate oxide film 114, and the gate electrodes 41 and 42 form transistors 31 and 32. This transistor 31
An interlayer insulating film 118 is formed so as to cover the electrodes 32 and 32. In the interlayer insulating film 118, the contact hole 11
8b is formed. From the contact hole 118b to the n ⁺ drain diffusion region 1 of the transistors 31 and 32.
Part of the surface of 13a is exposed. A wiring layer (source line) 30 is formed so as to be in contact with a part of the exposed surface of n ⁺ drain diffusion region 113a.

Next, referring to FIGS. 5 and 8B, an isolation oxide film 102 is formed on the surface of the silicon substrate 101. A gate electrode (word line) 41 is formed on the surface of the silicon substrate 101 with a gate oxide film 114 interposed. The layers above the gate electrode 41 are omitted for simplification.

Next, the circuit configuration of the X decoder 204 shown in FIG. 3 will be described. FIG. 9 is a schematic circuit diagram of an X decoder used in a flash memory according to an embodiment of the present invention. Further, FIG. 10 shows the circuit portion 121 of FIG.
It is a circuit diagram corresponding to. First, referring to FIGS. 9A and 10, an EXOR (exclusive OR) gate 121a is formed to receive address signal a _i and erase control signal EL. The signal output from the EXOR gate 121a is output to the terminal A and to the terminal B via the inverter 121b. A NAND gate 122a is provided to receive the signal output from the terminal B and the address signal a _j . The NAND gate 122a outputs a signal / Xφ ₀ and an inverter 123.
The signals Xφ ₀ and are output via a. The signal output from the terminal A of the circuit unit 121 and the address signal a
NAND gate 122b is provided to receive _j . This NAND gate 122b outputs a signal / Xφ ₁
And the signal Xφ ₁ is output via the inverter 123b. The NAND gate 122 receives the signal output from the terminal B of the circuit unit 121 and the address signal a _j.
c is provided. This NAND gate 122c outputs a signal / Xφ ₂ and a signal X via an inverter 123c.
φ ₂ and are output respectively. A NAND gate 122d is provided to receive the signal output from the terminal A of the circuit unit 121 and the inverted signal / a _j of the address signal a _j .
The NAND gate 122d outputs the signal / Xφ ₃ and the signal Xφ ₃ via the inverter 123d.

Referring to FIG. 9B, a 3-input NAND gate 125 is provided to receive the predecode signals XA, XB and XC generated from the address signal. The signal output from the NAND gate 125 is input to the circuit surrounded by the alternate long and short dash line. The circuit surrounded by the alternate long and short dash line includes transistors 126 and 127, p-type transistors 128 and 129, and an n-type transistor 130. The signal output from the NAND gate 125 is given to the gates of the p-type transistor 129 and the n-type transistor 130 via the transistor 126. The gate of the transistor 126 is controlled by the signal Xφ ₀ . The gates of the p-type transistor 129 and the n-type transistor 130 are connected to the power source voltage V _cc via the transistor 127.
Is set to be applied. The gate of the transistor 127 is controlled by the signal / Xφ ₀ .
Furthermore, the p-type transistor 129 and the n-type transistor 1
The gate of 30 is connected via a transistor 128 to a voltage control circuit 132 that generates a high voltage during writing and erasing. The gate of this transistor 128 is p
It is controlled by the output signals of the type transistor 129 and the n-type transistor 130. The source or drain of the p-type transistor 129 is connected to the voltage control circuit 132. The signals output from the p-type transistor 129 and the n-type transistor 130 are applied to the word line 1. The region surrounded by the alternate long and short dash line has the same structure as that described above, and therefore its description is omitted.

The truth table of the X decoder is shown in Table 1 below.
Shown in.

[0055]

[Table 1]

The voltage applied to each word line is controlled by this X decoder. Next, the operation of the flash memory according to the embodiment of the present invention will be described.

First, the case of writing data in the memory cell 11 will be described with reference to FIG. In this case, the write circuit (not shown) of each I / O is activated according to the data input from the outside. This allows the desired I / O line 7
A program voltage 12V is supplied to 0. This program voltage is transmitted to bit line 51 through n-channel transistor 61. On the other hand, the word line 41 is selected through the X decoder 204 by the address signal. At this time, the erase control signal EL is set to "L". When the word line 41 is selected, the memory cells 11-18
A program voltage of 12 V is applied to the control gate of. At the same time, the n-channel transistor 31 is turned on, and the sources of the memory cells 11-18 and 21-28 are connected to the source line 30. The source line 30 is grounded by the source potential generation circuit 203. In this way, the memory cell 11 is selected and writing is performed. Similarly, with respect to the other memory cells, writing is performed by selecting the word line and the bit line in which the memory cells to be written are arranged.

Next, in the case of erasing, the sense amplifier and write circuit (not shown) of each I / O are disconnected from the I / O line 70. As a result, all I / O lines 70 are opened. With the source potential generation circuit 203,
An erase voltage of 7V is applied to the global source line 80.
This erase voltage is applied to the transistor 1 provided corresponding to each byte string 10. The transistor 1 is selected by the Y decoder 205, and the selected transistor becomes conductive. At this time, the n-channel transistor 1 selected by the Y decoder 205, that is, turned on (conducting state), transmits the erase voltage to the source line 30. That is, unless the n-channel transistor 1 is turned on, the erase voltage is not applied to the source line 30 of the byte string 12, and therefore the memory cells in the byte string 10 are not erased. Next, the erase block voltage 12V is applied to the word line WL2 through the X decoder 204. At this time, the erase control signal EL is set to "H". Since the erase block voltage is applied to the word line WL2, the voltage is applied to the gate of the n-channel transistor 32, and the n-channel transistor 32 is turned on. As a result, the erase voltage is introduced to the sources of the memory cells 11-18 and 21-28 via the n-channel transistor 32. At this time, the word line WL2
Since the erase blocking voltage is applied to the control gates of the memory cells 21 to 28 arranged in the above, these memory cells 21 to 28 are not erased. That is, since the erase blocking voltage is applied to the control gate, the electrons in the floating gate are not extracted even when the erase voltage is applied to the source. Therefore, only the memory cells 11-18 are erased. Therefore,
It is possible to erase in byte units.

Here, the reason why the stored contents of the memory cells 21 to 28 are not erased when the erase blocking voltage is applied to the control gates of the memory cells 21 to 28 will be described. In erasing, the high electric field between the control gate and the source causes the electrons in the floating gate to be extracted by the tunnel phenomenon as described with reference to FIG. At this time, if a high voltage is applied to the control gate, the tunnel phenomenon does not occur. Therefore,
Electrons are not extracted from the floating gate by this tunnel phenomenon. Therefore, the memory cell to which the high voltage is applied to the control gate is not erased even if the erase voltage is applied to its source.

Further, when reading the stored contents of the memory cell 11, a voltage is first applied to the selection line 105 by the Y decoder 205. As a result, a voltage is applied to the gates of the n-channel transistors 1, 61 to 68 arranged on the selection line 105. Therefore, the n-channel transistors 1 and 61 to 68 become conductive. Therefore, the source line 3
0 indicates the global source line 80, and bit lines BL1 to BL1
BL8 is connected to the corresponding I / O line 70. After that, the erase control signal EL is set to "L". As a result, the voltage is applied to the word line WL1. When the voltage is applied to the word line WL1, the voltage is applied to the gate of the n-channel transistor 31 arranged in the word line WL1. For this reason,
The n-channel transistor 31 becomes conductive, and the sources of the memory cells 11-18 and 21-28 are connected to the source line 30 via the n-channel transistor 31. The source line 30 is grounded during reading. Therefore,
The memory cells 11 to 11 arranged in the word line WL1
The source of 18 is grounded. As a result, a sense amplifier (not shown) determines whether the write state or the erased state depends on whether or not a current flows through the memory cell 11.

Next, in the case of collectively erasing all the memory cells, the erase blocking voltage 12V is applied to even-numbered rows (WL2, WL4, etc.) of two word lines forming a pair. In addition, odd-numbered word lines (WL1, WL3
Etc.) is zero. At this time, the address signals a _j ,
After all / a _j and a _i are set to "H", the erase control signal EL is set to "L". As a result, the n-channel transistors 32 and the like whose gates are connected to the even-numbered word lines are turned on, and the erase voltage is introduced to the sources of all memory cells. At this time, since the erase block voltage is applied to the even rows of the paired word lines, only the memory cells arranged in the odd-numbered word lines are erased.

Next, odd-numbered rows (W
An erase block voltage is applied to L1, WL3, etc.). The voltage of the even-numbered word lines (WL2, WL4, etc.) is zero. At this time, all the address signals a _j , / a _j , and a _i for word line selection are set to “H”, and then the erase control signal EL is set to “H”. The n-channel transistors whose gates are connected to the odd-numbered word lines are turned on, and the erase voltage is introduced to the sources of all the memory cells. At this time, since the erase block voltage is applied to the odd-numbered rows of the paired word lines, only the memory cells arranged in the even-numbered word lines are erased. In this way, the memory cells arranged in the odd-numbered rows and the even-numbered rows of the paired word lines are alternately erased, whereby the batch erase of the byte column is completed twice.

Next, the voltage application timing at the time of erasing will be described. FIG. 11 is a diagram showing the timing of applying a voltage to the word line and the source line during erase. Figure 11
5, the horizontal axis represents time and the vertical axis represents voltage applied to the word line WL2 and the source line. When the word line WL1 is erased, the erase voltage is applied to the word line WL2 and then the erase voltage is applied to the source line. Further, after the erase voltage of the source line is removed, the erase blocking voltage of the word line WL2 is removed. In this way, by controlling the voltage applied to the word line WL2 and the source line, the erase block voltage is always applied to the word line WL2 while the voltage is applied to the source line. While the erase blocking voltage is applied to the word line WL2, the memory cells arranged in the word line WL2 are not erased even if the erase voltage is applied to the sources of the memory cells arranged in the word lines WL1 and WL2.
This surely prevents the word line WL2 from being erased.

Next, a method of relieving the over-raise will be described. FIG. 12A is an equivalent circuit diagram in which a part of FIG. 3 is enlarged. Further, FIG. 12B is a diagram schematically showing the arrangement of word lines. With reference to FIGS. 12A and 12B, "overlay" means that a threshold value at the time of erasing is low and a current flows even if the word line is grounded. As shown in FIG. 12A, a voltage of about ₁ V is applied to the bit line BL ₁ and a voltage of about 5 V is applied to the selected word line WL ₁ . That is, the memory cell (1) is selected. Assuming this time, V _th of the memory cell (1) is a normal positive value, the non-selected memory cell (2) is Obairezu state, i.e. if a value of V _th is set to a negative To do.

When the above memory cell (1) is selected to read data, as described above,
Bit line BL ₁ has, for example, 1 V, word line WL
_1, for example by applying a voltage of 5V to determine whether a current flows through the memory cell (1). That is, if a current flows, it is determined that the erased state is "1", and if no current flows, it is determined that the written state is "0". However, even when the selected memory cell (1) is in the write state “0”, the value of V _th of the non-selected memory cell (2) is negative, so that no current _{flows in} the non-selected memory cell (2). Flowing. As described above, a current flows through the bit line BL ₁ regardless of whether the selected memory cell (1) is in the written state or the erased state. Therefore, the selected memory cell (1) is always considered to be in the erased state "1".

In order to prevent such an adverse effect, FIG.
As shown in FIG. 2 (b), the word line including the memory cell in which the overvization has occurred and the word line paired with the word line are always grounded. Further, by replacing the pair of grounded word lines with a spare word line pair, the memory cell in which the over-vization has occurred is separated from the source line, and the bit line in which the memory cell in which the over-vization occurs exists ( For example, the bit line BL ₁ ) is saved.

In the flash memory according to the embodiment of the present invention, the source line 30 is selected by the Y decoder 205 and the transistor 1 as shown in FIG.

In the flash memory according to the embodiment of the present invention, as shown in FIG.
Is located in the center of the bit lines 51 to 58. That is, it has a configuration in which four bit lines are arranged on the left and right sides of the source line 30. Therefore, the variation in the distance from the source line 30 to the source of each memory cell can be minimized. That is, it is possible to reduce the distance between the source line 30 and the source of the memory cell located closest to the source line and the position of the source of the memory cell located farthest away. Therefore, it is possible to minimize the variation in resistance that occurs between the source and the source line 30 of each memory cell.

If the variation in resistance can be minimized in this way, the maximum value of resistance can also be suppressed. Since the maximum value of the resistance can be suppressed, it is possible to reduce the consumption of current in this resistance portion and to allow a large amount of current to flow. As a result, the read circuit (sense amplifier) at the time of reading the memory cell
It is possible to minimize the decrease in the current driving capability of the memory cell, which is one of the factors that determine the operation speed and operation stability of the memory cell.

In the flash memory according to the embodiment of the present invention, the erase voltage generated in the source potential generating circuit 203 is selectively changed by the transistor 1 to the byte string 10.
Can be applied to. Therefore, only one source potential generation circuit 203 is required.

The signal of the Y decoder is originally necessary to select the bit line, and the signal is used to select the source line of each byte string. Therefore, a signal for controlling the transistor 1 in FIG. 3 is separately provided. There is no need, and it is possible to reduce the number of signals. Further, since only one source potential generating circuit 203 is required, the region where the source potential generating circuit 203 is formed may be smaller than the conventional one.

On the other hand, since the transistor 1 is formed in the region such as the Y gate, high integration can be achieved.

[0073]

In the non-volatile semiconductor memory device of the present invention, the erase voltage generated by the erase voltage generating means can be selectively applied to the memory block by the memory block selecting means. Therefore, the erase voltage is applied to the selected memory block, but the erase voltage is not applied to the non-selected memory block. Therefore, even if each memory block shares a word line (that is, the memory cells arranged in the same row of each memory block are controlled by the same word line), the word line of the selected memory block is It is possible to erase only the stored contents of the arranged memory cells. As described above, by providing the memory block selecting means, it becomes possible to selectively apply the erasing voltage to each memory block even with one erasing voltage generating means. Since the memory block selection means is controlled by the signal of the Y decoder which selects the bit line, it is not necessary to newly provide a signal for making the memory block selection means conductive or non-conductive.

Since only one erase voltage generating means is required, the formation area of the erase voltage generating means can be reduced as compared with the case where the erase voltage generating means is provided by the number corresponding to each byte string.

Further, in the present invention, as many memory block selecting means as the memory blocks are provided. This memory block selecting means can be composed of, for example, one transistor, and its structure is simple. Therefore, the memory block selection means can be formed in a smaller area than the erase voltage generation means composed of a plurality of elements such as transistors. Therefore, the memory block selection means can be formed in a region such as the Y gate. In this way, since the erase voltage generating means is one and the memory block selecting means is provided corresponding to the memory block instead, the area for forming these is small,
Higher integration can be achieved by expanding the memory area accordingly.

[Brief description of drawings]

FIG. 1 is a schematic layout diagram of a memory cell array of a flash memory and its periphery according to an embodiment of the present invention.

FIG. 2 is a block diagram corresponding to FIG.

FIG. 3 is a circuit diagram schematically showing a configuration of a memory cell array used in a flash memory according to an embodiment of the present invention.

FIG. 4 is a schematic view showing a state in which a plurality of byte strings shown in FIG. 3 are formed.

FIG. 5 is a plan view schematically showing a configuration of a memory cell array and a Y gate adopted in a flash memory according to an embodiment of the present invention.

6 is a cross-sectional view taken along the line AA of FIG.

7 is a sectional view (a) taken along the line BB of FIG. 5 and a sectional view (b) taken along the line CC of FIG.

8 is a cross-sectional view (a) taken along the line DD of FIG. 5 and a cross-sectional view (b) taken along the line EE.

FIG. 9 is a circuit diagram schematically showing a configuration of an X decoder used in a flash memory according to an embodiment of the present invention.

10 is a circuit diagram of the circuit unit 121 of FIG.

FIG. 11 is a diagram showing a timing of applying a voltage to a word line and a source line when erasing a word line WL1 of a flash memory according to an embodiment of the present invention.

FIG. 12 is an enlarged equivalent circuit diagram (a) of a part of FIG. 3 and a diagram (b) schematically showing an arrangement of word lines.

FIG. 13 is a schematic block diagram of a general flash memory.

FIG. 14 is a diagram showing a configuration of a memory cell array in a conventional flash memory.

FIG. 15 is a sectional view schematically showing a configuration of a floating gate transistor arranged in a memory cell array in a conventional flash memory.

FIG. 16 is a circuit diagram schematically showing a configuration of a memory cell adopted in the flash memory disclosed in the patent document.

FIG. 17 is a block diagram schematically showing a configuration of a memory cell array of a flash memory disclosed in Patent Document and its periphery.

FIG. 18 is a layout diagram corresponding to FIG. 1 schematically showing a configuration of a memory cell array adopted in the flash memory disclosed in the patent document and its periphery.

[Explanation of symbols]

 1 Transistor 10-byte column 11-18, 21-28 Memory cell 201 Memory cell array 203 Source potential generation circuit

Claims (1)

[Claims] 1. A non-volatile semiconductor memory device capable of erasing data byte by byte and electrically erasable and writable, comprising: a memory array in which a plurality of memory blocks each including a predetermined number of memory cells are arranged. Memory block selection means connected to each of the memory blocks and having a conductive state and a non-conductive state for selecting one of the memory blocks; and a memory block selection which generates an erase voltage and is in a conductive state. The erase voltage is applied to the memory block to which the means is connected, and the erase voltage is not applied to the memory block to which the memory block selecting means in the non-conductive state is connected. A non-volatile semiconductor memory device comprising: an erase voltage generating means connected to the.