JP2010079977A - Nonvolatile semiconductor memory device with constant current type power supply circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device of small variations by suppressing variations in load characteristics by a transistor in write operation and erase operation in a memory cell. <P>SOLUTION: The nonvolatile semiconductor memory device 10 includes a constant current circuit 500 to which write or erase is performed by a current which is subjected to constant current control in writing or erasure in electric processing to the memory cell Mmn in a memory cell array section 100. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention is characterized in that writing or erasing is performed with a constant current in a nonvolatile semiconductor memory capable of writing or erasing in a single-layer polysilicon cell structure that can be manufactured by a standard CMOS (Complementary Metal-Oxide Semiconductor) process. The present invention relates to a nonvolatile semiconductor memory device.

  Nonvolatile semiconductor memories represented by EEPROM (Electrically Erasable Programmable Read Only Memory) have been used in many applications because information is not lost even when the power is turned off. For example, a typical application of an EEPROM is an IC card. In addition, EEPROM or flash memory is used as a replacement for the mask ROM in the microcomputer because it can be rewritten at any time according to the application. Furthermore, in recent years, there has been a need for a so-called embedded logic memory (embedded type) in which a nonvolatile semiconductor memory is incorporated in a part of a system LSI or logic IC. Furthermore, a small-sized non-volatile semiconductor memory of several hundred bits to several K (kilo) bits is also required as an adjustment switch that is incorporated into an analog circuit and performs tuning of a high-precision analog circuit. ing.

As means for realizing a small-scale nonvolatile semiconductor memory, an EEPROM using single-layer polysilicon has been proposed (for example, see Patent Document 1). If this one-layer polysilicon EEPROM is used, the number of manufacturing steps can be reduced as compared with the two-layer polysilicon process in the conventional nonvolatile semiconductor memory.
JP-A-10-289959

By the way, write characteristics and erase characteristics of the nonvolatile semiconductor memory device based on the technology disclosed so far will be described.
FIG. 18 is a block diagram of a nonvolatile semiconductor memory device 60 based on the technology disclosed so far.
In the memory cell array unit 100 in the nonvolatile semiconductor memory device 60, memory cells M11 to Mmn are arranged on a matrix to form a memory cell array. These memory cells M11 to Mmn are nonvolatile semiconductor memory elements by a one-layer polysilicon process.
The memory cells M11 to Mmn are connected to word lines WL1, WL2, and WLm (hereinafter, the word lines WL1, WL2, and WLm are collectively referred to as word lines WLm) and are connected to input row addresses. In response, the row selection signal selected by the row decoder 200 is output to the connected word line WLm. A memory cell to be connected is selected, and the selected memory cell is connected to the bit lines Bit1 to Bitn.

A word line WLm is connected to the row decoder 200, and the row decoder 200 outputs a selected row selection signal to the word line WLm. The memory cell Mmn selected by the signal from the word line WLm is activated and connected to the bit lines Bit1, Bit2,.
The column selection circuit 300 includes NMOS transistors 301, 302, to 300n for column selection. The column decoder 400 generates a column selection signal according to the input column address, and controls the transistors 301, 302, and 300n of the column selection circuit 300 connected through the column lines C1, C2, and Cn. The constant voltage circuit 500e outputs a constant voltage power source for writing or erasing. The write control circuit 600 outputs a control signal to be written to the memory cell in accordance with the input signal. The sense amplifier unit 700 is a sense amplifier for reading data from the memory cell. The power supply circuit 800 is a power supply circuit that supplies power to each circuit in the nonvolatile semiconductor memory device 60.
As shown in the figure, the supply of power in the write / erase operations for the memory cells is controlled by a power source controlled at a constant voltage by a constant voltage control circuit 500e.

  FIG. 19 is a schematic block diagram showing a conventional write operation. A write voltage 7 V is output from the power supply circuit 800. Since the drain withstand voltage (breakdown voltage) of the memory cell M11 is 7V, in order to set the drain voltage of the memory cell M11 to 5V, 5V is output from the constant voltage circuit 500e and this becomes the first load. Input to the gate of the NMOS transistor T1. The transistor T1 is a transistor having a threshold value of 0V. Next, write data Din * is output from the write data write control circuit 600 and input to the NMOS transistor T2 serving as the second load. The transistor T2 is a switch intended to function as a transfer gate, and a voltage of 9 V is input to the gate. The output of the selected column decoder is input to the NMOS transistor 301 serving as a third load. Since the transistor 301 also functions as a switch, a voltage of 9 V is input to the gate. A write current to the memory cell M11 is supplied via each of the NMOS transistors of the transistor T1, the transistor T2, and the transistor 301. Since the transistor T2 and the transistor 301 function by a switching operation, they have a sufficiently small resistance value. At this time, the transistor T1 operates in the saturation region, and determines the load characteristic of this current path.

  FIG. 20 shows an example of a conventional constant voltage circuit. The constant voltage circuit 500e is a constant voltage circuit that outputs the output voltage Vconst. The output voltage detection circuit 501e in the constant voltage circuit 500e is composed of an operational amplifier and compares the reference voltage Vref with a feedback signal from the output voltage Vconst to output a deviation. The output voltage detection circuit 501e is connected to a regulator 502e that stabilizes and outputs a voltage input from the power supply circuit 800, and outputs a stabilized output voltage Vconst. The output of the regulator 502e is connected to a reference potential via a resistor Ra and a resistor Rb connected in series. The resistors Ra and Rb divide the output voltage Vconst. The divided voltage is input to the output voltage detection circuit 501e as a feedback signal.

FIG. 21 is a graph showing operating points during a write operation of the memory cell Mmn. This graph shows a graph of write characteristics of an NMOS (Negative channel Metal Oxide Semiconductor) load line 1, an NMOS load line 2, and a memory cell Mmn. The horizontal axis of this graph indicates the drain voltage of the memory cell, and the vertical axis indicates the drain current.
The operating point 1e and the operating point 2e are indicated by the intersections of the NMOS load line 1, the NMOS load line 2, and the write characteristic line of the memory cell Mmn.

The characteristic indicated by the write characteristic line of the memory cell Mmn is that injection of hot electrons occurs when a voltage of 3 V is applied to the drain voltage, and the threshold value of the memory cell Mmn increases, so that a drain current flows through the memory cell Mmn. As a static characteristic, the drain current rapidly decreases. When the drain voltage is further increased, breakdown (VBD) occurs when the drain voltage reaches 7 V, and a large current flows.
When the load characteristic line indicating the load characteristic when the gate voltage of the NMOS transistor T1, that is, the voltage Vconst is 5 V, is superimposed on the current path according to the block diagram shown in FIG. The characteristic is shown. At this time, the intersection of the write characteristic line of the memory cell Mmn and the NMOS load line 1 indicating the load characteristic is the operating point 1e.
Further, there is a setting method different from the setting method of the load characteristic described above. For example, assuming that the gate resistance of the NMOS transistor T1 is reduced to increase the load resistance and the constant voltage input to the gate of the NMOS transistor T1 is 9 V, the NMOS load line 2 shown in FIG. In addition, the operating point moves to the operating point 2e shown in the state where breakdown occurs in the write characteristics of the memory cell Mmn. A large current flows in the write current at this time, but the write characteristics to the memory cell Mmn are good.

FIG. 22 is a graph showing the difference in write time caused by different drain voltages for the write characteristics of the memory cell Mmn.
In this figure, two drain voltages indicated by “VD high” having a high drain voltage and “VD low” having a low drain voltage are set, and graphs showing changes in respective threshold voltages are shown. The horizontal axis of this graph represents elapsed time (logt), and the vertical axis represents the threshold voltage of the written memory cell Mmn.
The threshold potential rises faster when the drain voltage is higher (VD high) as shown in this figure than when the drain voltage is lower (VD low). Therefore, it is shown that the writing is completed earlier and the writing characteristics are better when the drain voltage is high (VD high).

However, when the drain voltage is high (VD high), there is a drawback that the load characteristics vary greatly as shown below.
FIG. 23 shows variations in load characteristics of the NMOS transistor T1. The characteristic variation indicated by the NMOS load lines 1 and 2 is superimposed on the graph shown in FIG. For each of the NMOS load lines 1 and 2, the lower limit value (indicated by the dotted line in the figure) and the upper limit value (indicated by the alternate long and short dash line in the figure) of the variation of each representative characteristic (indicated by the solid line) with respect to the voltage are shown. As shown in the figure, at the operating point 1e in the NMOS load line 1, in addition to variations in the output voltage of the constant voltage circuit 500e, variations in the characteristics of the transistor T1 (including variations in the substrate bias effect) are also added, and the memory cell Mmn. The drain voltage (operating point) varies greatly. On the other hand, at the operating point 2e in the NMOS load line 2 in which the conditions are changed, the drain current varies greatly, and it is difficult to secure a stable operating point regardless of which condition is selected. .

FIG. 24 is a block diagram showing a conventional erase circuit based on constant voltage control. The erase circuit shown in the figure is a circuit having a configuration in which erase is performed by an erase circuit connected to the drain side of the memory cell M11.
In order to perform the erase operation of the memory cell, it is necessary to set a voltage of 9V to the drain of the memory cell M11. Therefore, the erase voltage setting signal Erase output from the power supply circuit 500e in accordance with the input erase signal (Erase). * (9V) is input to the gate of the NMOS transistor T1. The drain voltage (12V) is controlled to a constant voltage of 9V of the erase voltage setting signal Erase * by the NMOS transistor T1, and supplied to the memory cell M11.
The gate of the transistor 301, which is the second NMOS load transistor, functions as a switch by the output C1 of the column decoder and receives 12V.

  FIG. 25 is a block diagram showing an erasing circuit by conventional constant voltage control having a configuration different from the above. FIG. 10 is a block diagram showing a configuration in which erasing is performed by an erasing circuit connected to the source side of the memory cell Mmn. The erasing NMOS load transistor T1 is connected to each memory cell via a source line S connected to the sources of the plurality of memory cells. The erase circuit shown in this figure is used in combination with the write circuit shown in FIG.

FIG. 26 shows an erase characteristic indicating a change in the current of the memory cell Mmn at the time of erase and an operating point thereof.
When a voltage is applied to the drain or source of the memory cell Mmn, first, electric field concentration in the depletion layer occurs in the vicinity of the drain, a so-called high energy band-to-band (BtoB) current flows, and a hole-electron pair is generated. appear. Some high-energy holes (hot holes) are taken into the floating gate. When the voltage is further increased and an over electric field is applied to the oxide film between the floating gate and the Fowler-Nordheim tunnel current, electrons flow from the floating gate FG to the drain D. When the voltage is further increased, a junction breakdown occurs and a large current flows through the substrate. This breakdown voltage is assumed to be VBD (= 8V).
The load characteristic of the NMOS transistor (T1 in FIG. 24 or FIG. 25) is displayed as an NMOS load line. The operating point is the intersection of the erase characteristic line indicating the erase characteristic and the NMOS load line.

FIG. 27 shows variations in load characteristics due to NMOS transistors. Taking into account variations in the erase characteristics of the memory cell and the load characteristics of the NMOS transistor, the range of movement of the operating point is widened, so that the erase current to the memory cell accompanying the movement of the operating point also varies greatly.
FIG. 28 shows variations in erase characteristics in the case of a load due to an NMOS transistor. Erasing characteristics in the Fowler-Nordheim region where a large amount of current flows can be erased quickly. On the other hand, in the erasing characteristic in the Band to Band area where a small amount of current flows, the erasing completion time is delayed because it takes erasing time.

As described above, in the EEPROM technology using one-layer polysilicon, the characteristics of the nonvolatile semiconductor memory cell vary in the writing process and the erasing process. In addition, the load characteristic due to the NMOS transistor in the voltage control circuit supplied to the nonvolatile semiconductor memory cell also varies.
Due to these factors, the operating points in the write processing characteristics and the erase processing characteristics in the nonvolatile semiconductor memory cell vary. The variation of the operating point for each nonvolatile semiconductor memory cell varies in characteristics in the writing process and the erasing process performed for each nonvolatile semiconductor memory cell. This is equivalent to meaning non-uniformity of storage characteristics in the nonvolatile semiconductor memory device, and a phenomenon that appears as non-uniformity of characteristics in the entire nonvolatile semiconductor memory device becomes a problem in quality. .

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a nonvolatile semiconductor memory device with less variation by suppressing variation in load characteristics due to transistors in a write operation and an erase operation in a memory cell. There is.

  In order to solve the above problems, the present invention outputs a plurality of nonvolatile semiconductor memory elements that can be written or erased by electrical processing, and a constant current controlled current for performing writing or erasing of the nonvolatile semiconductor memory elements. A non-volatile semiconductor memory device.

  According to the present invention, the bit line is set in a nonvolatile semiconductor memory element that is arranged at an intersection of a matrix composed of a word line, a source line, and a bit line and is selected by the word line and the bit line. A non-volatile semiconductor memory device in which writing or erasing is performed according to a signal, a constant current circuit disposed between a power supply and the bit line, and outputting a constant current controlled current to the bit line, and an input A selection element that selects whether or not to supply the output current of the constant current circuit to the nonvolatile semiconductor memory element during a write operation or an erase operation in accordance with a signal to be performed A semiconductor memory device.

  In the invention described above, the constant current circuit is provided for each bit line.

  In addition, according to the present invention, in the above invention, the constant current circuit outputs the current to a plurality of the bit lines selected simultaneously by a column control line, and performs writing or erasing to the plurality of selected memory cells. It is characterized by that.

  According to the present invention, the bit line is set in a nonvolatile semiconductor memory element that is arranged at an intersection of a matrix composed of a word line, a source line, and a bit line and is selected by the word line and the bit line. A nonvolatile semiconductor memory device in which writing or erasing is performed in response to a signal, the constant current circuit being arranged between a reference potential and the source line and outputting a constant current controlled current to the source line; A non-volatile semiconductor memory device comprising:

  According to the present invention, the bit line is set in a nonvolatile semiconductor memory element that is arranged at an intersection of a matrix composed of a word line, a source line, and a bit line and is selected by the word line and the bit line. A non-volatile semiconductor memory device in which writing or erasing is performed in response to a signal, the first constant current circuit being arranged between a power supply and the bit line and outputting a current subjected to constant current control to the bit line A selection element that selects supply of the output current of the constant current circuit to the nonvolatile semiconductor memory element during a write operation or an erase operation according to an input signal, a reference potential, and a source line And a second constant current circuit that outputs a constant current controlled current to the source line, wherein the first constant current circuit writes the memory cell Was carried out, the second constant current circuit is a nonvolatile semiconductor memory device characterized by erasing the memory cell.

  Also, the present invention is characterized in that, in the above-mentioned invention, the second constant current circuit erases the memory cell for each predetermined block including the memory cell connected to the source line. .

  Further, the present invention is the output current setting unit according to the above invention, wherein the constant current circuit sets a constant current controlled current value supplied to the memory cells according to the number of the memory cells selected simultaneously. It is characterized by providing.

  The present invention is also characterized in that, in the above invention, the nonvolatile semiconductor memory element has a floating gate type structure.

  Further, the present invention is characterized in that, in the above-mentioned invention, the nonvolatile semiconductor memory element has a MONOS type structure.

  The present invention is the above invention, wherein the nonvolatile semiconductor memory element has a nanocrystal type structure.

According to the present invention, in a nonvolatile semiconductor memory device, writing or erasing of a nonvolatile semiconductor memory element is performed by a current controlled at a constant current in a writing operation or an erasing operation by electrical processing.
As a result, as constant current control that is not easily affected by load fluctuations, it is possible to select an operation point in a write operation and an erase operation in a region where the current is constant current controlled. Further, in a region where the current is controlled at a constant current, the operating point fluctuation range can be limited without being affected by the load fluctuation. Even if a standard logic CMOS process that causes variations in the characteristics of the write operation and the erase operation is used, the influence of the variations in the characteristics can be reduced. Further, even when a standard logic CMOS process is used, a highly reliable nonvolatile semiconductor memory device can be realized, and a logic-embedded nonvolatile semiconductor memory device can be realized easily and inexpensively.

Embodiments of the present invention will be described below with reference to the drawings.
[Operation of Nonvolatile Semiconductor Memory Device]
A nonvolatile semiconductor memory element (also referred to as “memory cell”) used in the embodiment of the present invention will be described.
FIG. 1A shows a cross-sectional view of one transistor constituting a nonvolatile semiconductor memory element, and FIG. 1B shows an equivalent circuit diagram thereof. The nonvolatile semiconductor memory element shown in FIGS. 1A and 1B includes a transistor Tr, a drain D, a source S, a floating layer formed on a semiconductor substrate SUB (potential Vsub) using a single-layer polysilicon cell structure. The gate FG includes a control gate CG, and a capacitor C (FC) between the floating gate FG and the control gate CG. This floating gate FG becomes a charge holding region. The floating gate FG is not provided with an electrode to be directly connected, but is connected with a control gate CG via a capacitor C (FC), and a floating made of polysilicon on a gate insulating layer formed on the substrate SUB. A gate FG is formed.
The drain D and the source S are diffusion regions formed on the substrate SUB, and electrodes are provided through contacts.

  FIG. 2 shows an equivalent circuit of the capacitive coupling system of the nonvolatile semiconductor memory element shown in FIG. If there is a charge Q in the floating gate FG, the total charge of this system becomes Q, which can be expressed as equation (1).

  In Expression (1), VCG, VFG, VD, VS, and Vch are the control gate CG potential, floating gate FG potential, drain D potential, source S potential, and channel CH potential, respectively. C (FC) is a capacitance between the floating gate FG and the control gate CG, C (FD) is a capacitance between the floating gate FG and the drain D, C (FS) is a capacitance between the floating gate FG and the source S, C ( FB) is a capacitance between the floating gate FG and the substrate SUB. Here, if the sum of the capacities is defined as CT (total), the relationship between the capacities can be expressed by equation (2).

  Further, the relationship between the potentials can be expressed by Expression (3).

  In Equation (3), Q / CT represents the potential when charge is injected into the floating gate. Here, when VS = Vch = 0V (reference potential, the same applies hereinafter) and VD × C (FD) ≈0, it can be expressed by Expression (4).

Equation (4) shows that the potential VFG of the floating gate depends on the injected charge amount Q.
Further, when Q = 0, it can be expressed by Expression (5).

  The ratio of each capacity is roughly set to C (FC) /CT≈0.6, and can be expressed by Expression (6).

For example, the balance of each coupling capacity is set to C (FC): C (FD): C (FS): C (FB) = 1.6: 0.2: 0.2: 0.6.
In the case of the write operation, if VCG = 9V, VD = 5V, VS = 0V, Vch = 0.5VD, and Q = 0, the potential VFG of the floating gate at the time of the write operation is obtained by the equation (7).

As shown in the equation (7), the transistor constituting this memory cell operates in the saturation region, so that a large amount of hot electrons are generated, electrons are injected into the floating gate, and the write operation is performed. Is called.
In the case of the erase operation, if VCG = 0V, VD = 8V, VS = open, and Vch = 0V, the potential VFG of the floating gate at the time of the erase operation is obtained by Expression (8).

  As shown in Expression (8), since the potential of the floating gate is about 0.6 V, a potential of about 7.4 V is applied between the drain and the floating gate, and a tunnel current flows to perform the erase operation.

The transistor characteristics in the erased state and the written state will be described with reference to the drawings.
FIG. 3 is a graph showing changes in the threshold voltage of the floating gate type nonvolatile semiconductor memory device. In this figure, the horizontal axis is the control gate potential VCG, the vertical axis is the current Id of the drain D, and the floating gate potential VFG is changed in three states of the erased state, the neutral state and the written state. 4 schematically shows a change in drain current Id when the number of electrons in the inside is changed.
In the neutral state, the drain current Id rises in the vicinity of about 0.5 V, and the threshold value in the neutral state is shown. The characteristics of the erased state and the written state are obtained by translating the graphs showing the characteristics of the neutral state. Compared to the neutral state, the floating gate potential VFG is about 2.2 V lower in the erased state, and the floating gate potential VFG is about 2.0 V higher in the written state.

(First embodiment)
A nonvolatile semiconductor memory device using a constant current circuit will be described as a first embodiment of the present invention with reference to the drawings.
FIG. 4 is a block diagram showing the nonvolatile semiconductor memory device 10 in the first embodiment. The nonvolatile semiconductor memory device 10 shown in the figure includes a memory cell array unit 100, a row decoder 200, a column selection circuit 300, a column decoder 400, a constant current circuit 500, a write control circuit 600, a connection control circuit 601, a sense amplifier unit 700, Power supply circuit 800, word lines WL1, WL2,... WLm (hereinafter, word lines WL1, WL2,... WLm are collectively referred to as WLm), bit lines Bit1, Bit2, .about.Bitn (hereinafter, bit lines Bit1,. Bit2 and -Bitn are collectively expressed as Bitn), column lines C1, C2, and -Cn (hereinafter, when column lines C1, C2, and -Cn are collectively expressed are described as Cn), data line DL Source line S and control power supply line PS.

The memory cell array unit 100 in the nonvolatile semiconductor memory device 10 forms a memory cell array by arranging memory cells M11 to Mmn (referred to as Mmn when the memory cells M11 to Mmn are collectively shown) on a matrix. The memory cell Mmn is arranged at an intersection of a word line, a source line, and a bit line, and is selected by the word line and the bit line. These memory cells Mmn are floating gate type nonvolatile semiconductor memory elements.
A memory cell connected to the word line WLm connected to the row decoder 200 is selected, and the column line Cn is selected by the column decoder 400, and the selected memory cell is connected to the bit line Bitn.

  The control gate CG of the memory cells M11, M12,... M1n is connected to the word line WL1. Control gates CG of memory cells M21, M22,... M2n are connected to word line WL2. Similarly, control gates CG of memory cells Mm1, Mm2,... Mmn are connected to word line WLm. The drains D of the memory cells M11, M21, to Mm1 are connected to the bit line Bit1. The drains D of the memory cells M12, M22, to Mm2 are connected to the bit line Bit2. Similarly, drains D of the memory cells M1n, M2n, .about.Mmn are connected to the bit line Bitn. A source S of each memory cell Mmn is connected to the source line S.

The row decoder 200 decodes the input row address information and outputs a signal for selecting a row of the memory cell array unit 100 to the word line WLm.
The column decoder 400 decodes the input column address information and outputs a signal for selecting a column of the memory cell array unit 100 to the column line Cn.
The column selection circuit 300 includes transistors 301, 302, to 300n (hereinafter referred to as transistors 300n when the transistors 301, 302, to 300n are collectively shown). The transistor 300n in the column selection circuit 300 connects the bit line Bitn selected by a signal input via the column line Cn to the data line DL.

The write control circuit 600 includes an input circuit 602. When the input circuit 602 in the write control circuit 600 detects a signal input from the Din line, the input circuit 602 outputs a signal based on the input signal to the Din * line. The connection control circuit 601 connects the control power supply line PS from the power supply to the data line DL based on the signal output from the write control circuit 600 to the Din * line. The sense amplifier unit 700 detects the signal on the data line DL, performs necessary amplification, and outputs the amplified signal to the Dout line.
The power supply circuit 800 is a power supply that supplies power to each component such as the row decoder 200, the column decoder 400, the constant current circuit 500, and the write control circuit 600 that configure the nonvolatile semiconductor memory device 10. A constant current circuit 500 is connected to the power supply circuit 800, and the constant current circuit 500 supplies a required constant current to the control power supply line PS.

The constant current circuit 500 in the nonvolatile semiconductor memory device 10 includes a transistor 501, a transistor 503, a transistor 504, a transistor 505, and a resistor 502.
In the constant current circuit 500, the transistor 501 is a constant current load transistor for supplying a constant current to the memory cell array unit 100. The resistor 502 is a resistor that sets a current supplied to the load. The transistor 503 and the transistor 504 and the transistor 505 and the transistor 501 form a current mirror circuit, respectively.
An output current determined by the resistance value of the resistor 502 and the amplification factors of the transistors 503, 504, 505, and 501 is supplied from the transistor 501 to the control power supply line PS.

A write operation in the nonvolatile semiconductor memory device 10 will be described with reference to the drawings.
FIG. 5 is a schematic block diagram illustrating a write operation in the nonvolatile semiconductor memory device 10. In the constituent elements shown in this figure, the same constituent elements as those shown in FIG. 4 are denoted by the same reference numerals, and the above description is referred to.

  In this figure, the word line WL1 is selected by the row decoder 200 according to the input row address (control signal voltage 9V), and the column line C1 is selected by the column decoder 400 according to the input column address (control signal voltage). 9V). Thus, the bit line Bit1 is connected to the data line DL by the transistor 301 of the column selection circuit 300 connected to the column decoder 400. Further, the memory cell M11 of the memory cell array unit 100 connected to the row decoder 200 is selected, and the memory cell M11 is connected to the selected bit line Bit1. In this figure, components selected according to the above conditions from among a plurality of components are shown.

  In the write operation described here, a signal indicating the write operation is input to the write control circuit 600 as a control signal input from the Din line. When a signal indicating a write operation is detected by the input circuit 602 in the write control circuit 600, a control signal (control signal voltage 9 V) indicating the write operation is input to the connection control circuit 601. The connection control circuit 601 to which the control signal indicating the write operation is input is controlled so as to connect the data line DL and the control power supply line PS, and writing to the memory cell M11 is performed.

The current output from the constant current circuit 500 is determined by the following relationship.
The transistor 503 has a width W1 and a length L1, the transistor 504 has a width W2 and a length L2, the transistor 505 has a width W3 and a length L3, and the transistor 501 has a width W4 and a length L4. The current Iout flowing through the transistor 501 is expressed by Expression (9) based on the current IREF flowing through R.

  In the formula (9), α is represented by the formula (10).

  Since sufficiently high 9 V is input to the gates of the connection control circuit 601 (transistor) and the transistor 301, the load of the load current path connected to the memory cell via the transistor 501, the connection control circuit 601 (transistor) and the transistor 301 The current is determined by the current set by the transistor 501, and the constant current set to Iout flows.

FIG. 6 is a graph showing operating points during a write operation. This graph shows a graph of the write characteristics of the PMOS (Positive channel Metal Oxide Semiconductor) load line 1, the PMOS load line 2, and the memory cell M11. The PMOS load line 1 and the PMOS load line 2 show a lower limit value and an upper limit value indicating the fluctuation range, respectively. The horizontal axis of this graph represents the drain voltage Vd of the memory cell, and the vertical axis represents the drain current Id.
The operating point 1 to the operating point 3 indicated by the intersections of the PMOS load line 1, the PMOS load line 2, and the write characteristics of the memory cell M11 are shown.
As for the write characteristics of the memory cell M11, hot electron injection occurs when a drain voltage of 3 V is applied, and the threshold value of the memory cell M11 becomes high, so that it is difficult for a current to flow through the memory cell M11. The current decreases. When the drain voltage is further increased, breakdown (VBD) occurs when the drain voltage is 7V, and a large current flows.

Since the drain current characteristic of the transistor 501 which is a PMOS transistor indicated by the PMOS load line 1 and the PMOS load line 2 is controlled at a constant current, the fluctuation range of the drain current becomes narrow. The fluctuation range is indicated by a lower limit value (indicated by a dotted line in the figure) and an upper limit value (indicated by a one-dot chain line in the figure). Each graph is close to the representative characteristic (indicated by the solid line in the figure). The operating point of the current output from the PMOS transistor 501 is preferably arranged in a region where the constant current operation is stable, that is, a region where the PMOS load line is indicated by a straight line. Further, as indicated by the fluctuation range of the PMOS load line 1 and the PMOS load line 2, the range in which the operating point of the constant current operation in the transistor 501 varies can be narrowed. As a result, the operation can be stabilized.
In the case of the operation indicated by the PMOS load line 1, there is one operating point (operating point 1). However, when the current is reduced, the operation is indicated by the PMOS load line 2, and there are two operating points (operating point). 2. Operating point 3) will appear. When the two operating points indicated by the operating point 2 and the operating point 3 are compared, it is desirable that the operating point 2 has a higher drain voltage. In order to set the operating point 2, if the gate voltage is applied after the drain voltage is applied first, the operating point 2 having a high drain voltage can be stabilized. Thus, a stable operating point 2 can be selected by supplying a current with a stable constant current characteristic in a region where breakdown (VBD) occurs.

An erasing operation in the nonvolatile semiconductor memory device 10 will be described with reference to the drawings.
FIG. 7 is a schematic block diagram for explaining an erase operation in the nonvolatile semiconductor memory device 10. In the constituent elements shown in this figure, the same constituent elements as those shown in FIG. 4 are denoted by the same reference numerals, and the above description is referred to.
In the case of the erasing operation, unlike the case of the writing operation, there is no selection processing in the connection control circuit 601 unlike the processing in the writing operation, the connection control circuit 601 is unnecessary, and the control power supply line PS and the data line DL are directly connected. Connecting. In the figure, the connection control circuit 601 is indicated by a broken line and is directly connected.
In the figure, the word line WL1 is selected by the row decoder 200 according to the input row address (control signal voltage 0V), and the column line C1 is selected by the column decoder 400 according to the input column address (control signal voltage). 9V). Thus, the bit line Bit1 is connected to the data line DL by the transistor 301 of the column selection circuit 300 connected to the column decoder 400. Further, the memory cell M11 of the memory cell array unit 100 connected to the row decoder 200 is selected, and the memory cell M11 is connected to the selected bit line Bit1. In this figure, components selected according to the above conditions from among a plurality of components are shown.
The memory cell M11 is supplied with a current for performing an erasing operation from the constant current circuit 500, and an erasing process is performed. The operation at the time of erasing of the constant current circuit 500 is the same as the operation in the writing process shown in FIG.

FIG. 8 is a graph showing operating points during the erasing operation. This graph shows a graph of erase characteristics of the PMOS load line and the memory cell M11. In addition, the PMOS load line and the erasing characteristic have a lower limit value and an upper limit value indicating the fluctuation range, respectively. The horizontal axis of this graph represents the drain voltage Vd of the memory cell, and the vertical axis represents the drain current Id.
An operating point 1 and an operating point 2 indicated by the intersection of the PMOS load line and the erase characteristic of the memory cell M11 are shown.

Since the current output from the PMOS transistor 501 indicated by the PMOS load line is controlled at a constant current, the fluctuation range of the drain current becomes narrow. The fluctuation range is indicated by a lower limit value (indicated by a dotted line in the figure) and an upper limit value (indicated by a one-dot chain line in the figure). Each graph is close to the representative characteristic (indicated by the solid line in the figure). The operating point of the current output from the PMOS transistor 501 is located in a region where the constant current operation is stable, that is, a region where constant current control is performed in which the PMOS load line is indicated by a straight line. desirable. Further, as indicated by the fluctuation width of the PMOS load line, the fluctuation range in which the operating point of the constant current operation in the PMOS transistor varies can be narrowed.
The voltage fluctuation range of the erasing characteristic shown in the graph showing the erasing characteristic is indicated by a lower limit value (indicated by a dotted line in the figure) and an upper limit value (indicated by a dashed line in the figure). Each graph is close to the representative characteristic (indicated by the solid line in the figure). Thereby, the variation range of the operating point due to the variation in the erase operation indicated by the erase characteristic can be narrowed, and the influence due to the variation in the erase characteristic can be reduced.
Note that the operating point indicated by the intersection of the PMOS load line and the erasing characteristic is determined to be one point according to each characteristic. The determined operating point varies depending on variations in the PMOS load line and the erase characteristic. Even considering variations in the PMOS load line and the erasing characteristic, they are limited to the range of the minimum value of the memory cell current indicated by the operating point 1 and the maximum value of the memory cell current indicated by the operating point 2 shown in the drawing. Even if the operating point fluctuates due to variations in characteristics, the fluctuation range can be narrowed as shown in the figure, indicating that it is easy to stabilize the operating point.

(Second Embodiment)
A current setting and switching method in a constant current circuit will be described as a second embodiment of the present invention with reference to the drawings.
FIG. 9 is a block diagram showing the nonvolatile semiconductor memory device 20 in the second embodiment. The nonvolatile semiconductor memory device 20 shown in the figure includes a memory cell array unit 120, a row decoder 220, a column selection circuit 320, a column decoder 420, a constant current circuit 520, a write control circuit 600, a connection control circuit 601a, a sense amplifier unit 700, Power supply circuit 820, word line WL1, bit line Bit1, Bit2, to Bit8 (hereinafter, bit lines Bit1, Bit2, and Bit8 are collectively expressed as Bitn), column lines C1, C2, and C8 (hereinafter, Column lines C1, C2,..., C8 are collectively referred to as Cn), data line DL, source line S, and control power supply lines PS1, PS2.
In the nonvolatile semiconductor memory device 20, the memory cell array unit 120, the row decoder 220, the column selection circuit 320, the column decoder 420, the constant current circuit 520, the connection control circuit 601a, the power supply circuit 820, the word line WL1, the bit line Bitn, the column Since the configuration other than the line Cn and the control power supply lines PS1 and PS2 is the same as that of the nonvolatile semiconductor memory device 10 according to the first embodiment, the same reference numerals are given and the description in the first embodiment is referred to.
The memory cell array unit 120 in the nonvolatile semiconductor memory device 10 includes memory cells M11, M12, and M18 arranged on a matrix to form a memory cell array. These memory cells M11, M12 to M18 are floating gate type nonvolatile semiconductor memory elements.
Control gates CG of memory cells M11, M12,... M18 are connected to word line WL1. Sources of the memory cells M11, M12, to M18 are connected to the source line S.

  The drain D of the memory cell M11 is connected to the bit line Bit1. The drain D of the memory cell M12 is connected to the bit line Bit2. Similarly, the drain D of the memory cell M18 is connected to the bit line Bitn.

  A memory cell connected to the word line WL1 connected to the row decoder 220 is selected, and the selected memory cell is connected to the bit line Bitn.

The row decoder 220 decodes the input row address information and outputs a signal for selecting a row of the memory cell array unit 120 to the word line WL1.
The column decoder 420 decodes the input column address information and outputs a signal for selecting a column of the memory cell array unit 120 to the column line Cn. The number of column lines Cn from which a signal for selecting a column is output is specified by the input signal multi-select signals MS2, MS4, and MS8, and the number of column lines Cn corresponding to the input signals is selected. Further, the column decoder 420 outputs a switching signal SWn for controlling the output current of the constant current control circuit 520.
The column selection circuit 320 includes transistors 321, 322, and 328 (hereinafter referred to as a transistor 320 n when the transistors 321, 322, and 328 are collectively shown). The column selection circuit 320 connects a bit line Bitn selected by a signal input via the column line Cn to the data line DL via the transistor 320n.
The connection control circuit 601a connects the control power supply line PS from the power supply to the data line DL based on the signal output from the write control circuit 600 to the Din * line. The sense amplifier unit 700 detects a signal on the data line DL, performs necessary amplification, and outputs the amplified signal to the Dout line.
The power supply circuit 820 is a power supply that supplies power to each component constituting the nonvolatile semiconductor memory device 20.
A constant current circuit 520, a connection control circuit 601a, and the like are connected to the power supply circuit 820, and the constant current circuit 520 outputs a required constant current to the control power supply lines PS1 to PS2.

  The constant current circuit 520 in the nonvolatile semiconductor memory device 20 includes transistors 501-1 and 501-2, a transistor 503, a transistor 504, a transistor 505, transistors 507-1, 507-2, and 507-3, and a transistor. 508-1 and 508-2 and resistors 502-1, 502-2, and 502-3.

In the constant current circuit 520, transistors 501-1 and 501-2 are PMOS type constant current load transistors for outputting a constant current to the memory cell array unit 100. Further, the resistors 502-1, 502-2, and 502-3 are resistors that set the current flowing through the load.
A resistor 502-1 is connected in series to the output of the power supply circuit 820 through a transistor 507-1. The transistor 507-1 is a switching transistor that cuts off the current flowing through the resistor 502-1 by the switching signal SW1 input to the gate thereof. A resistor 502-2 is connected in series to the output of the power supply circuit 820 through a transistor 507-2. The transistor 507-2 is a switching transistor that blocks a current flowing through the resistor 502-2 by the switching signal SW2 input to the gate thereof. A resistor 502-3 is connected in series to the output of the power supply circuit 820 through a transistor 507-3. The transistor 507-3 is a switching transistor that cuts off the current flowing through the resistor 502-3 by the switching signal SW3 input to the gate thereof. The currents limited by the resistors 502-1 to 502-3 are combined and flow into the transistor 503.
Further, the transistor 503 and the transistor 504, the transistor 505 and the transistor 501-1, and the transistor 505 and the transistor 501-2 constitute a current mirror circuit, respectively.

  The output current is determined by the amplification factors of the resistors 502-1 to 502-3, the transistor 503 and the transistor 504, the transistor 505 and the transistor 501-1, and the transistor 505 and the transistor 501-2 according to the equation (10). The value is based on the output current value.

A constant current determined by values set in these transistors is output from the transistor 501-1 to the control power supply line PS1, and from the transistor 501-2 to the control power supply line PS2.
The current output to the control power supply lines PS1 and PS2 is output via the transistors 508-1 and 508-2 that control the current output of the constant current circuit 520.
The transistor 508-1 switches between energization and interruption of the current supplied to the control power supply line PS1 by the switching signal SWa input to the gate thereof. The transistor 508-2 switches between energization and interruption of the current supplied to the control power supply line PS2 by the switching signal SWb input to its gate.

For example, the memory cell array 120 has eight column selection lines including column lines C1 to C8.
As a first condition, in the normal mode in which one memory cell is selected, for example, only the column line C1 is selected, and the memory cell M11 is selected.
As a second condition, when two memory cells are selected at the same time, when the signal multi-select signal MS2 is input to the column decoder, two column lines are selected. For example, the column line C1 and the column line C2 are simultaneously selected, and the memory cells M11 and M12 are simultaneously selected.
As a third condition, when four memory cells are simultaneously selected, four column lines are selected when the signal multi-select signal MS4 is input. For example, the column lines C1 to C4 are simultaneously selected, and the memory cells M11 to M14 are simultaneously selected.
As a fourth condition, when eight memory cells are selected simultaneously, when the signal multi-select signal MS8 is input, all eight column lines are selected. In the figure, column lines C1 to C8 are simultaneously selected, and memory cells M11 to M18 are simultaneously selected.
In this way, when a plurality of conditions can be set, an increase in the number of memory cells that are simultaneously selected means that the set constant current value is distributed to each memory cell. That is, the constant current supplied per memory cell is proportional to the reciprocal of the number of memory cells connected at the same time, and the current value decreases as the number of distributions increases. Therefore, the constant current can be operated at a desired operating point. It will disappear.

As a coping method in such a case, it can be solved by combining the following two measures, and the constant current supplied per memory cell can be set to a desired value. The first method is a method of increasing the value of the reference current determined by the resistance value used as the reference of the constant current circuit 520. The second method is a method of enhancing the output circuit of the constant current circuit that outputs to the memory cell array unit 120.
In the following description, the four conditions described above are taken as an example, and writing, erasing of one, two, four, and eight memory cells are performed simultaneously. At that time, if the current of the constant current circuit 520 is an output current value of one circuit of the transistor 501-1, it is not possible to process eight memory cells at the same time, and up to four memory cells can be allowed simultaneously. Will be described.
From the above conditions, the constant current circuit 520 cannot supply a predetermined current only with the transistor 502-1 and simultaneously uses the transistors 502-2 connected in parallel when eight memory cells are used simultaneously.

FIG. 10 is a table showing the operation of each switching transistor in the constant current circuit 520. Hereinafter, the operation under each condition shown in the figure will be described.
Hereinafter, description will be made by associating each transistor operating as a current setting switch as a switch. In these correspondences, the transistors 507-1, 507-2, 507-3, 508-1 and 508-2 are switches SW1, SW2, SW3, SWa and SWb. In addition, the conduction state and the cutoff state of each transistor are indicated by “ON” indicating the conduction state of the corresponding switch and “OFF” indicating the cutoff state.
The state indicated by the condition 1 is a state where only one column line (for example, the column line C1) is selected in the column decoder 420. In the constant current circuit 520 in this state, when SW1 is turned on and SW2 and SW3 are turned off, the current flowing through the transistor 503 becomes IREF. At this time, SWa is on and SWb is off, the constant current αIREF flows through the constant current load transistor 501-1, and the constant current load transistor 501-2 is cut off.

 The state indicated by condition 2 is a state in which two column lines (for example, column lines C1 and C2) are selected in the column decoder 420. In the constant current circuit 520 in this state, when SW1 and SW2 are on and SW3 is off, the current flowing through the transistor 503 is 2IREF. At this time, SWa is on and SWb is off, the constant current 2αIREF flows through the constant current load transistor 501-1, and the constant current load transistor 501-2 is cut off.

 The state indicated by condition 3 is a state in which four column lines (for example, column lines C1 to C4) are selected in the column decoder 420. In the constant current circuit 520 in this state, when all of SW1, SW2, and SW3 are turned on, the current flowing through the transistor 503 is 4IREF. At this time, SWa is on and SWb is off, the constant current 4αIREF flows through the constant current load transistor 501-1, and the constant current load transistor 501-2 is cut off. Based on the assumptions made earlier, transistor 501-1 is at an acceptable limit under this condition.

 The state indicated by condition 4 is a state in which eight column lines (for example, column lines C1 to C8) are selected in the column decoder 420. In the constant current circuit 520 in this state, when all of SW1, SW2, and SW3 are turned on, the current flowing through the transistor 503 is 4IREF. When both SWa and SWb are turned on, the constant current 4αIREF flows through both the constant current load transistor 501-1 and the transistor 501-2. As described above, even when eight column lines are selected, it is possible to secure eight times as much current as in condition 1, and it is possible to output a current value suitable for each memory cell. .

 In addition, even when the current value set between the write operation and the erase operation is switched or when the current value is switched according to the characteristics of the memory cell, a resistor having a resistance value necessary for constant current control is provided. The current value can be switched by selecting with the switching means. As this switching means, the present embodiment can be applied and realized.

(Third embodiment)
With reference to the drawings, a mode in which a constant current circuit is provided for each bit line will be described as a third embodiment of the present invention.
FIG. 11 is a block diagram showing the nonvolatile semiconductor memory device 30 in the third embodiment. The nonvolatile semiconductor memory device 30 shown in the figure includes a memory cell array unit 100, a row decoder 230, a column selection circuit 300, a column decoder 430, a constant current circuit 530, a write control circuit 600, and connection control circuits 601-1 to 601-n. , Sense amplifier unit 700, power supply circuit 830, word lines WL1, WL2, .about.WLm (hereinafter, word lines WL1, WL2, .about.WLm are collectively expressed as WLm), bit lines Bit1, Bit2, .about.Bitn ( Hereinafter, the bit lines Bit1, Bit2,..., Bitn are collectively expressed as Bitn), the column lines C1 to Cn (hereinafter, the column lines C1 to Cn are collectively expressed as Cn), and the data line DL. The source line S is provided.
Of the nonvolatile semiconductor memory device 30, the row decoder 230, the column decoder 430, the constant current circuit 530, the connection control circuits 601-1, 601-2, to 601-n (hereinafter referred to as the connection control circuits 601-1 and 601-2). ˜601-n are collectively described as 601-n), except for the power supply circuit 830, since it has the same configuration as the nonvolatile semiconductor memory device 10 according to the first embodiment, the same reference numerals are given, Reference is made to the description in the first embodiment.

The row decoder 230 decodes the input row address information and outputs a signal for selecting a row of the memory cell array unit 100 to the word line WLn. The row decoder 230 outputs “0” to all the word lines WLn when erasing all the memory cells Mmn in the memory cell array unit 100 at a time.
The column decoder 430 decodes the input column address information and outputs a signal for selecting a column of the memory cell array unit 100 to the column line Cn. Further, when the page erase control signal Page is input, the column decoder 430 outputs a signal for selecting a column of the memory cell array unit 100 to all the column lines Cn.

The power supply circuit 830 is a power supply that supplies power to each component such as the row decoder 230, the column decoder 430, the constant current circuit 530, and the write control circuit 600 that constitute the nonvolatile semiconductor memory device 30. A constant current circuit 530 and a data line DL are connected to the power supply circuit 830, and a predetermined voltage is output during a write operation and an erase operation.
A constant current circuit 530 is connected to the power supply circuit 830. The constant current circuit 530 includes control power supply lines PS-1, PS-2, to PS-n (hereinafter referred to as control power supply lines PS-1, PS-2,. When PS-n is collectively expressed, it is described as a control power supply line PS-n.) A required constant current is output.
A connection control circuit 601-n is connected to the write control circuit 600. The connection control circuit 601-n connects the control power supply line PS-n from the constant current circuit 530 to each bit line Bitn based on the signal output from the write control circuit 600 to the Din * line.
The constant current circuit 530 in the nonvolatile semiconductor memory device 30 includes transistors 531-1, 531-2, to 531-n (hereinafter referred to as transistors 531 when the transistors 531-1, 531-2, to 531-n are collectively shown). -N), a transistor 503, a transistor 504, a transistor 505, a transistor 506, and a resistor 502 are provided.
In the constant current circuit 530, the transistor 531-n is a constant current load transistor for outputting a constant current to the memory cell array unit 100. The resistor 502 is a resistor that sets a current flowing through the load. The transistor 503 and the transistor 504, and the transistor 505 and the transistor 531-n constitute current mirror circuits, respectively.

The output current is output based on the output current determined by the amplification factors of the resistor 502, the transistor 503, the transistor 504, the transistor 505, and the transistor 531-n according to the equation (10). A constant current set by these combined transistors is supplied from the transistor 531-n to the control power supply line PS-n.
Note that the constant current supplied from the transistor 531-n can be released based on the signal state of the control signal line RW input to the transistor 506. A signal on the control signal line RW input to the transistor 506 is a status signal indicating a read operation from the memory cell array unit 100 or a write operation to the memory cell array unit 100. During a read operation and a write operation in which the signal of the control signal line RW becomes significant, the transistor 506 is turned on, the constant current supply to the memory cell array unit 100 is released, and the transistor 531 -n is turned on. .

  A constant current load transistor is connected to each of the transistors 531-1, 531-2, and 531-n for each bit line Bitn, and a constant current αIREF is output for each bit line Bitn. For example, if the word line WL1 and the column line C1 are selected by the row decoder 230 and the column decoder 430, the memory cell M11 is written and erased. At this time, when performing page erase or page write, if the column decoder 430 simultaneously selects the column lines C1 to Cn, simultaneous write and erase can be performed on all the memory cells M11 to M1n. In particular, at the time of erasing, if all WL1 to WLm are set to 0V, all the memory cells Mmn in the memory cell array unit 100 are erased. When page selection is performed, when the page selection signal Page is input to the column decoder 430, the column decoder enters the all selection mode, all the column lines C1 to Cn are selected, and a constant current is applied to each of the connection control circuits 601-n. Will flow.

(Fourth embodiment)
With reference to the drawings, a description will be given of a mode in which an erasing constant current circuit is provided on the source side of a memory cell as a fourth embodiment of the present invention.
FIG. 12 is a block diagram of the nonvolatile semiconductor memory device 40 in the fourth embodiment.
The nonvolatile semiconductor memory device 40 shown in the figure includes a memory cell array unit 100, a row decoder 230, a column selection circuit 300, a column decoder 400, a constant current circuit 500a, a write control circuit 600, a connection control circuit 601a, a sense amplifier unit 700, Power supply circuit 840, word lines WL1, WL2, .about.WLm (hereinafter, word lines WL1, WL2, .about.WLm are collectively described as WLm), bit lines Bit1, Bit2, .about.Bitn (hereinafter, bit lines Bit1,. Bit2 and ~ Bitn are collectively expressed as Bitn), column lines C1, C2 and ~ Cn (hereinafter, when column lines C1, C2 and ~ Cn are collectively expressed are denoted as Cn), data line DL The source line S is provided.
Since the nonvolatile semiconductor memory device 40 has the same configuration as the nonvolatile semiconductor memory device 10 according to the first embodiment except for the row decoder 230, the constant current circuit 500a, the connection control circuit 601a, and the power supply circuit 840, the same reference numerals are used. Reference is made to the description in the first embodiment. Further, since the connection control circuit 601a has the same configuration as that of the nonvolatile semiconductor memory device 20 according to the second embodiment, the same reference numerals are given and the description in the second embodiment is referred to. Moreover, since the row decoder 230 has the same configuration as that of the nonvolatile semiconductor memory device 30 according to the third embodiment, the same reference numerals are given and the description in the third embodiment is referred to.

The power supply circuit 840 in the nonvolatile semiconductor memory device 40 is a power supply that supplies power to each component that constitutes the nonvolatile semiconductor memory device 40. A constant current circuit 500a, a connection control circuit 601a, and the like are connected to the power supply circuit 840, and the constant current circuit 500a outputs a required constant current to the source line S.
The constant current circuit 500a includes a transistor 501, a transistor 503, a transistor 504, a transistor 505, a transistor 509, a transistor 510, and a resistor 502.
In the constant current circuit 500a, the transistor 501 is a constant current load transistor for outputting a constant current to the memory cell array unit 100. The resistor 502 is a resistor that sets a current flowing through the load. The transistor 503 and the transistor 504 and the transistor 505 and the transistor 501 form a current mirror circuit, respectively.

  Based on the output current determined by the amplification factor of the resistor 502, the transistor 503, the transistor 504, the transistor 505, and the transistor 501, a constant current determined by a set value in these transistors is supplied from the transistor 501 to the source line S. .

Note that the source line S is connected to the reference potential based on the signal state of the control signal line RW input to the transistor 509. At the same time, the constant current output supplied from the transistor 501 can be canceled. A signal on the control signal line RW input to the transistor 509 is a state signal indicating a read operation from the memory cell array unit 100 or a write operation to the memory cell array unit 100. The transistor 509 is turned on during a read operation and a write operation in which the signal of the control signal line RW becomes significant.
Further, the operation of the current mirror circuit constituted by the transistors 501, 503, 504, and 505 is stopped by the signal of the control signal line EB input to the transistor 510, and the constant current output from the constant current circuit 500a is stopped. be able to. That is, by stopping the constant current output and turning off the transistor 509 with the control signal line RW, the source line S can be in an OPEN (open) state.

  The configuration of the fourth embodiment is for performing an erasing operation of the nonvolatile semiconductor memory device 40. The constant current circuit 500 and the second current in the nonvolatile semiconductor memory device 10 according to the first embodiment performing a writing operation are the second and second configurations. A write operation can be performed by combining the constant current circuit 520 in the nonvolatile semiconductor memory device 20 according to the embodiment, the constant current circuit 530 in the nonvolatile semiconductor memory device 30 according to the third embodiment, and the like.

The erase operation in the nonvolatile semiconductor memory device 40 will be described with reference to the drawings.
FIG. 13 is a schematic block diagram for explaining an erase operation in the nonvolatile semiconductor memory device 40. In the components shown in this figure, the same components as those shown in FIG. 12 are denoted by the same reference numerals, and the above description is referred to.

  In this figure, the word line WL1 is selected (control signal voltage 0V) by the input row address, and the column line C1 is selected (control signal voltage 0V) by the input column address. As a result, the bit line Bit1 is cut off from the data line DL by the transistor 301 of the column selection circuit 300 connected to the column decoder 400. Further, the memory cell M11 of the memory cell array unit 100 connected to the row decoder 230 is selected, and the selected memory cell M11 is erased. In this figure, components selected according to the above conditions from among a plurality of components are shown.

The current output from the constant current circuit 500a is determined by the following relationship.
The transistor 503 has a width W1 and a length L1, the transistor 504 has a width W2 and a length L2, the transistor 504 has a width W2 and a length L2, and the transistor 501 has a width W4 and a length L4. The current Iout that flows through the transistor 501 is expressed by Expression (11) based on the current that flows through R as IREF.

  In the formula (11), α is represented by the formula (12).

(Fifth embodiment)
With reference to the drawings, as a fifth embodiment of the present invention, an embodiment in which a write constant current circuit and an erase constant current circuit are provided will be described.
FIG. 14 is a block diagram of the nonvolatile semiconductor memory device 50 in the fifth embodiment.
The nonvolatile semiconductor memory device 50 shown in the figure includes a memory cell array unit 150, a row decoder 230, a column selection circuit 300, a column decoder 400, a constant current circuit 550, constant current circuits 500a-1, 500a-2, to 500a-m. , Write control circuit 650, sense amplifier unit 700, power supply circuit 850, word lines WL1, WL2, .about.WLm (hereinafter, word lines WL1, WL2, .about.WLm are collectively referred to as WLm), bit lines Bit1, Bit2. , ~ Bitn (hereinafter, when the bit lines Bit1, Bit2, and ~ Bitn are collectively expressed as Bitn), column lines C1, C2, and ~ Cn (hereinafter, when the column lines C1, C2, and ~ Cn are collectively expressed) Is described as Cn), a data line DL, and source lines S1, S2, to Sm.
In the nonvolatile semiconductor memory device 50, the memory cell array unit 150, the row decoder 230, the constant current circuit 550, the constant current circuits 500a-1, 500a-2, to 500a-m (hereinafter, the constant current circuits 500a-1, 500a- 2 and ~ 500a-m are collectively described as 500a-m), write control circuit 650, power supply circuit 850, source lines S1, S2, ~ Sm (hereinafter, source lines S1, S2, ~ Sm collectively) Since the configuration is the same as that of the nonvolatile semiconductor memory device 10 according to the first embodiment except that it is expressed as Sm), the same reference numerals are given and the description in the first embodiment is referred to.
Moreover, since the row decoder 230 has the same configuration as that of the nonvolatile semiconductor memory device 30 according to the third embodiment, the same reference numerals are given and the description in the third embodiment is referred to.

In the memory cell array unit 150 in the nonvolatile semiconductor memory device 50, memory cells M11 to Mmn are arranged on a matrix to form a memory cell array. These memory cells M11 to Mmn are floating gate type nonvolatile semiconductor memory elements according to the present invention. The connection of the source line which is different from the memory cell array unit 100 shown in the first embodiment will be described, and the description of the same configuration will refer to the first embodiment.
In the memory cell array unit 150, the sources of the memory cells are connected in units of rows.
The source of the memory cells M11, M12,... M1n is connected to the source line S1. The source of the memory cells M21, M22,... M2n is connected to the source line S2. Similarly, the sources of the memory cells Mm1, Mm2,... Mmn are connected to the source line Sm.

Memory cells connected to the word lines WL1 to WLm connected to the row decoder 230 are selected, and the selected memory cells are connected to the bit lines Bit1 to Bitn.
The control gate CG of the memory cells M11, M12,... M1n is connected to the word line WL1. Control gates CG of memory cells M21, M22,... M2n are connected to word line WL2. Similarly, control gates CG of memory cells Mm1, Mm2,... Mmn are connected to word line WLm.
The drains D of the memory cells M11, M21, to Mm1 are connected to the bit line Bit1. The drains D of the memory cells M12, M22, to Mm2 are connected to the bit line Bit2. Similarly, drains D of the memory cells M1n, M2n, .about.Mmn are connected to the bit line Bitn.

The power supply circuit 850 includes each of the row decoder 230, the column decoder 400, the constant current circuit 550, the constant current circuits 500a-1, 500a-2 to 500a-m, the write control circuit 650, etc. that constitute the nonvolatile semiconductor memory device 50. A power source that supplies power to the components. A constant current circuit 550 and a write control circuit 650 are connected to the power supply circuit 850, and a predetermined voltage is output during a write operation.
A constant current circuit 550 is connected to the power supply circuit 850. The constant current circuit 550 outputs a required constant current to the control power supply lines PS-1, PS-2, to PS-n.
The data line DL is connected to the write control circuit 650, and a predetermined voltage is output during a write operation.

The constant current circuit 550 in the nonvolatile semiconductor memory device 50 includes transistors 531-1, 531-2, to 531-n (hereinafter referred to as transistors 531 when the transistors 531-1, 531-2, to 531-n are collectively shown). -N), a transistor 503, a transistor 504, a transistor 505, a transistor 506, and a resistor 502 are provided.
In the constant current circuit 550, the transistor 531-n is a constant current load transistor for outputting a constant current to the memory cell array unit 100. The resistor 502 is a resistor that sets a current flowing through the load. The transistor 503 and the transistor 504, and the transistor 505 and the transistor 531-n constitute current mirror circuits, respectively.

  Based on the amplification factors of the resistor 502, the transistor 503, the transistor 504, the transistor 505, and the transistor 531-n, an output current defined by the equation (11) is output. A constant current determined by a set value in these combined transistors is supplied from the transistor 531-n to the control power supply lines PS-1, PS-2, to PS-n. Note that the constant current supplied from the transistor 531-n can be released based on the signal state of the control signal line RW input to the transistor 506. A signal on the control signal line RW input to the transistor 506 is a status signal indicating a read operation from the memory cell array unit 150 or a write operation to the memory cell array unit 150. During a read operation and a write operation in which the signal of the control signal line RW becomes significant, the transistor 506 is turned on, the supply of constant current to the memory cell array unit 150 is released, and the transistor 531 -n is turned on. .

Transistors 531-1, 531-2, and 531-n are provided as constant current load transistors for each bit line Bitn, and a constant current αIREF is output for each bit line Bitn. For example, when the word line WL1 and the column line C1 are selected by the row decoder 230 and the column decoder 400, writing to the memory cell M11 is performed. At this time, when page erasing or page writing is performed, if the column decoder 430 simultaneously selects the column lines C1 to Cn, it is possible to simultaneously write in all the memory cells M11 to M1n.
The constant current circuit 550 has the same internal configuration as the constant current circuit 530 of the third embodiment, and supplies a current for the write operation of the memory cell array unit 150. The difference from the constant current circuit 530 is that no current is supplied during the erase operation.

  A plurality of constant current circuits 500a-m having the same configuration as the constant current circuit 500a of the fourth embodiment are provided. The constant current circuits 500a-m are connected to the respective source lines of the memory cell array unit 150, and output a constant current required for the erase operation to the connected source lines Sm of the memory cell array unit 150. The detailed operation of each of the constant current circuits 500a-m is the same as that of the constant current circuit 500a in the fourth embodiment. The difference in operating points is that the memory cell array unit 150 is divided and each constant current circuit 500a-m erases.

  As described above, the constant current circuit 550 disposed on the drain D side of the memory cell array unit 150 connected to the bit line Bitm, and the constant current circuit 500a-m disposed on the source S side of the memory cell array unit 150. Thus, the functions of the write operation and the erase operation can be distributed.

  Further, in the memory cell array unit 150, a plurality of source lines Sm are grouped and connected to each other, and the source lines Sm are connected to each other and connected to the constant current circuit 500a-m in units of the grouped source lines. The memory cells Mmn can be divided and erased for each range in which the lines Sm are grouped.

(Sixth embodiment)
With reference to the drawings, as a sixth embodiment of the present invention, application of a floating gate type nonvolatile semiconductor memory device not provided with a control gate terminal will be described.
FIG. 15 is a structural diagram of the nonvolatile semiconductor memory element described in the sixth embodiment.
The nonvolatile semiconductor memory element shown in this figure can be applied to the memory cell Mmn in each memory cell array portion of the nonvolatile semiconductor memory devices 10 to 50 described above.
This nonvolatile semiconductor memory element has a structure of a floating gate type nonvolatile semiconductor memory element that does not include a control gate terminal.
FIG. 15A is a plan view of one transistor constituting the nonvolatile semiconductor memory element used in the embodiment of the present invention, FIG. 15B is a sectional view, and FIG. 15C is an equivalent circuit diagram. Show. 15A to 15C are formed from a floating gate FG, a drain D, and a source S formed on a semiconductor substrate SUB (potential Vsub) using a single-layer polysilicon cell structure. Composed. This floating gate FG serves as a charge holding region, no electrode is provided, and a floating gate FG made of polysilicon is formed on a gate insulating layer formed on the substrate SUB.
The drain D and the source S are diffusion regions formed on the substrate SUB, and electrodes are provided through contacts.

  FIG. 16 shows an equivalent circuit of the coupling system of the nonvolatile semiconductor memory element shown in FIG. Assuming that the charge Q existing in the floating gate FG is contained, the total charge of this system becomes Q and can be expressed by the equation (13).

  In Expression (13), VFG, VD, VS, and Vch are the potential of the floating gate FG, the potential of the drain D, the potential of the source S, and the potential of the channel CH, respectively. C (FC) is a capacitance between the floating gate FG and the substrate SUB, C (FD) is a capacitance between the floating gate FG and the drain D, and C (FS) is a capacitance between the floating gate FG and the source S. , C (FB) is a capacitance between the floating gate FG and the channel CH. Here, if the sum of the capacities is defined as CT (total), the relationship between the capacities can be expressed by equation (14).

  Further, the relationship between the potentials can be expressed by Expression (15).

  In Equation (15), Q / CT represents the voltage VFG of the floating gate when charge is injected into the floating gate. Here, when VS = Vsub = 0 V (reference potential, the same applies hereinafter), it can be expressed by Expression (16).

  Further, when Q = 0, it can be expressed by Expression (17).

For example, the balance of each coupling capacity is set to C (FC): C (FD): C (FS): C (FB) = 0.1: 0.2: 0.2: 0.6.
In the case of the write operation, when VD = 6 V, VS = 0 V, and Vch≈0.5 VD, the voltage VFG at the time of the write operation of the floating gate is obtained by Expression (18).

As shown in the equation (18), the transistor constituting this memory cell operates in the saturation region, so that hot electrons are generated, electrons are injected into the floating gate, and writing is performed.
In the case of the erase operation, if VD = 9V, VS = open, and Vch = 0V, the voltage VFG at the time of the erase operation of the floating gate is obtained by Expression (19).

  As shown in Expression (19), a potential of about 7.4 V is applied between the source and the floating gate, and a tunnel current flows to perform an erase operation.

(Seventh embodiment)
A nonvolatile semiconductor memory device applicable as a seventh embodiment of the present invention will be described with reference to the drawings.
FIG. 17 is a structural diagram of the nonvolatile semiconductor memory element described in the seventh embodiment.
The nonvolatile semiconductor memory element shown in this figure can be applied to the memory cell Mmn in each memory cell array portion of the nonvolatile semiconductor memory devices 10 to 50 described above.
This non-volatile semiconductor memory element is a non-volatile semiconductor memory element having a structure different from the above-described floating gate type.
FIG. 17A is a cross-sectional view of one transistor constituting a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) type nonvolatile semiconductor memory element.
The memory cell shown in this figure includes a transistor Tr, a drain D, a source S, an insulating film N, and a gate G formed on a semiconductor substrate SUB. Electric charges are held by the insulating film N. As the insulating film N, there is a film using a nitride (for example, N ₃ H ₄ ). The drain D and the source S are diffusion regions formed on the substrate SUB, and electrodes are provided through contacts.

FIG. 17B is a cross-sectional view of one transistor constituting the nanocrystal type nonvolatile semiconductor memory element.
The memory cell shown in this figure includes a transistor Tr, a drain D, a source S, an oxide film NC, and a gate G formed on a semiconductor substrate SUB. The oxide film NC is provided with a nanodot crystal. The drain D and the source S are diffusion regions formed on the substrate SUB, and electrodes are provided through contacts.
Even in the nonvolatile semiconductor memory elements other than the floating gate type shown in the seventh embodiment, the current at the time of performing the write operation and the erase operation is controlled at a constant current, thereby stabilizing each operating point. Can do.

  According to the present invention, it is possible to set the operating point in the writing operation and the erasing operation by using the constant current control that is hardly influenced by the load fluctuation. In addition, it is possible to limit the fluctuation range of the operating point without being affected by the load fluctuation. Further, a highly reliable nonvolatile semiconductor memory device can be realized by a standard logic CMOS process, and a logic-embedded nonvolatile semiconductor memory device can be realized easily and inexpensively.

1 is a structural diagram showing a nonvolatile semiconductor memory element applied to the present invention. 3 is an equivalent circuit showing capacitive coupling of a floating gate type nonvolatile semiconductor memory element applied to the present invention. It is a graph which shows the change of the threshold value of the floating gate type non-volatile semiconductor memory element applied to this invention. 1 is a block diagram showing a nonvolatile semiconductor memory device according to a first embodiment of the present invention. FIG. 3 is a schematic block diagram (part 1) illustrating an operation of the nonvolatile semiconductor memory device according to the first embodiment. 3 is a graph showing operating points during a write operation of the nonvolatile semiconductor memory device of the first embodiment. FIG. 3 is a schematic block diagram (part 2) illustrating an operation of the nonvolatile semiconductor memory device according to the first embodiment. 3 is a graph showing operating points during an erasing operation of the nonvolatile semiconductor memory device of the first embodiment. It is a schematic block diagram which shows the non-volatile semiconductor memory device of 2nd Embodiment. 6 is an operation table showing an operation of the nonvolatile semiconductor memory device of the second embodiment. It is a schematic block diagram which shows the non-volatile semiconductor memory device of 3rd Embodiment. It is a schematic block diagram which shows the non-volatile semiconductor memory device of 4th Embodiment. It is a schematic block diagram which shows operation | movement of the non-volatile semiconductor memory device of 4th Embodiment. It is a schematic block diagram which shows the non-volatile semiconductor memory device of 5th Embodiment. FIG. 9 is a structural diagram illustrating a nonvolatile semiconductor memory device according to a sixth embodiment. 14 is an equivalent circuit showing capacitive coupling of a floating gate type nonvolatile memory device according to a sixth embodiment. FIG. 10 is a structural diagram illustrating various nonvolatile semiconductor memory devices according to a seventh embodiment. It is a block diagram which shows the conventional non-volatile semiconductor memory device. 6 is an equivalent circuit showing a write operation of a conventional nonvolatile semiconductor memory device. It is a block diagram which shows the conventional constant voltage circuit. 5 is a graph showing operating points at the time of writing by a constant voltage circuit of a conventional nonvolatile semiconductor memory device. 5 is a graph showing write characteristics of a conventional nonvolatile semiconductor memory device. 5 is a graph showing variations in load characteristics during writing by a constant voltage circuit of a conventional nonvolatile semiconductor memory device. 5 is an equivalent circuit showing an erase operation of a conventional nonvolatile semiconductor memory device. FIG. 10 is a block diagram showing an erasing circuit for erasing from a source side in a conventional nonvolatile semiconductor memory device. 6 is a graph showing operating points at the time of erasing of a conventional nonvolatile semiconductor memory device. 5 is a graph showing variations in load characteristics of a conventional nonvolatile semiconductor memory device. 5 is a graph showing variations in erase characteristics in the case of an NMOS load of a conventional nonvolatile semiconductor memory device.

Explanation of symbols

10 nonvolatile semiconductor memory device,
100 memory cell array, M11 to Mmn memory cells,
200 row decoder, 300, 301 to 300n column selection circuit, 400 column decoder,
500 constant current circuit, 501, 503-505 transistor, 502 resistance,
600 Write control circuit, 602 input circuit, 601 connection control circuit,
700 sense amplifier section, 800 power supply circuit,
WL1-WLm word line, Bit1-Bitn bit line, C1-Cn column line,
DL data line, S source line, PS control power line

Claims (11)

A plurality of nonvolatile semiconductor memory elements that can be written or erased by electrical processing;
A constant current circuit for outputting a constant current controlled current for writing or erasing the nonvolatile semiconductor memory element;
A non-volatile semiconductor memory device comprising: A word line, a source line, and a bit line are arranged at intersections of a matrix, and a nonvolatile semiconductor memory element selected by the word line and the bit line is written or written according to a signal set to the bit line. A non-volatile semiconductor memory device to be erased,
A constant current circuit disposed between a power source and the bit line, and outputting a constant-current controlled current to the bit line;
A selection element that selects whether or not to supply the output current of the constant current circuit to the nonvolatile semiconductor memory element during a write operation or an erase operation according to an input signal;
A non-volatile semiconductor memory device comprising: The constant current circuit is:
The nonvolatile semiconductor memory device according to claim 2, wherein the nonvolatile semiconductor memory device is provided for each bit line. The constant current circuit is:
The current is output to a plurality of the bit lines selected simultaneously by a column control line, and writing or erasing is performed on the plurality of selected nonvolatile semiconductor memory elements. The nonvolatile semiconductor memory device described. A word line, a source line, and a bit line are arranged at intersections of a matrix, and a nonvolatile semiconductor memory element selected by the word line and the bit line is written or written according to a signal set to the bit line. A non-volatile semiconductor memory device to be erased,
A constant current circuit disposed between a reference potential and the source line and outputting a constant current controlled current to the source line;
A non-volatile semiconductor memory device comprising: A word line, a source line, and a bit line are arranged at intersections of a matrix, and a nonvolatile semiconductor memory element selected by the word line and the bit line is written or written according to a signal set to the bit line. A non-volatile semiconductor memory device to be erased,
A first constant current circuit disposed between a power supply and the bit line, and outputting a constant-current controlled current to the bit line;
A selection element that selects to supply an output current of the constant current circuit to the nonvolatile semiconductor memory element during a write operation or an erase operation according to an input signal;
A second constant current circuit arranged between a reference potential and the source line and outputting a constant current controlled current to the source line;
With
The nonvolatile semiconductor memory device, wherein the first constant current circuit performs writing to the nonvolatile semiconductor memory element, and the second constant current circuit erases the nonvolatile semiconductor memory element. The second constant current circuit includes:
The nonvolatile semiconductor memory device according to claim 6, wherein the nonvolatile semiconductor memory element is erased for each predetermined block including the nonvolatile semiconductor memory element connected to the source line. The constant current circuit is:
3. An output current setting unit configured to set a constant current-controlled current value supplied to the nonvolatile semiconductor memory element according to the number of the nonvolatile semiconductor memory elements selected at the same time. The nonvolatile semiconductor memory device according to claim 7. The nonvolatile semiconductor memory element is
The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device has a floating gate type structure. The nonvolatile semiconductor memory element is
The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device has a MONOS type structure. The nonvolatile semiconductor memory element is
The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device has a nanocrystal type structure.

Images