JPH0817189A - Non-volatile semiconductor device - Google Patents

Abstract

PURPOSE:To stabilize the amount of injected electrons by limiting the amount of current flowing to a memory transistor in a non-volatile semiconductor storage (EPROM, flash memory, etc.) for injecting electrons to a floating gate utilizing the avalanche breakdown phenomenon. CONSTITUTION:Depletion-type transistors 23 and 24 where a source and a gate are connected are provided between an interface circuit 25 for converting the voltage amplitude input between VDD and GND to the voltage amplitude input between VPP and GND and transistors 5 and 6 for selecting a bit line. Also, a similar depletion-type transistor is provided between the drain of a bit-line selection transistor and that of a memory transistor, thus preventing the breakdown of a memory transistor due to overcurrent, latch-up phenomenon, etc. A stable writing is possible regardless of the fluctuation in a writing voltage and scattering in terms of process, thus reducing stress to gate oxide film, increasing number of rewriting times, and improving reliability.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly to a method for writing to a UV erasable writable read only memory (hereinafter referred to as EPROM) and a flash (collective erasing type) memory.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional writing circuit. Here, in order to simplify the explanation, a four-memory transistor configuration is adopted. However, in reality, a memory cell composed of this memory transistor is formed by arranging a desired number of memory transistors in a matrix. 1
4 are memory transistors, WL1 and 2 are word lines connected to the control gates of the memory transistors, and B
L1 and 2 are bit lines connected to the drains of the memory transistors, SL is a source line commonly connected to the sources of the memory transistors, and 5 and 6 are N channels for selecting the bit lines connected to the drains of the memory transistors. Transistors, 7 is a column decoder circuit that selects 5, 6 N-channel transistors, 8-10 are NAND circuits, 1
Reference numerals 1 to 16 are N-channel transistors, 17 to 22 are P-channel transistors, and 25 is an interface circuit. Here, the interface circuit 25 is VDD-GND.
Has the function of changing the voltage amplitude input of VPP-GND into the voltage amplitude output of VPP-GND. Further, hereinafter, the injection of electrons into the floating gate is referred to as writing.

A writing method will be described with reference to FIG. For example, when writing to the memory transistor 1, first, the output of the NAND circuit 9 is set to GND level (about 0V), NA
The output of the ND circuit 10 is set to VDD level (about 5V), and W
L1 is VPP1 level (about 12.5V), WL2 is GN
Set to D level. Next, the output of the NAND circuit 8 is set to the GND level, and the column decoder circuit 7 turns on the N-channel transistor 5 and turns off the N-channel transistor 6 to set BL1 to the VPP2 level (about 8 V) and BL2 to the open level. Source line SL and substrate are G respectively
It is at the ND level. Then, the memory transistor 1 is selected, the control gate of the memory transistor 1 is at VPP1 level, the drain is at VPP2 level,
The GND level is applied to the source and the substrate.

At this time, high-energy electrons (hot electrons) are generated near the drain due to the avalanche breakdown phenomenon, and these electrons are attracted by the electric field from the control gate to overcome the barrier of the gate oxide film from the substrate to the floating gate. Is injected. In this case, a channel current does not flow in the memory transistors 2 to 4, and avalanche breakdown does not occur, so that electrons are not injected into the floating gate. On the other hand, at the time of reading, by applying the VDD level to the control gate of the selected memory transistor, data "1" or "0" is determined depending on whether the memory transistor is turned on or off at that time. That is, the threshold voltage of the memory transistor after writing must be higher than the voltage VDD level applied to the control gate of the memory transistor during reading.

Next, FIG. 5 shows a static characteristic curve (a) and a write load transistor curve (b) of the memory transistor as an explanation of the operation of the memory transistor at the time of writing. When the drain voltage is increased in the curve (a), injection of electrons into the memory transistor begins to occur and the threshold voltage of the memory transistor increases, so that the amount of current flowing through the memory transistor decreases. Here, the drain voltage indicates the drain voltage of the memory transistor. When the drain voltage is further increased, the memory transistor causes a snapback phenomenon and a large current flows.

The operating point of the memory cell at the time of writing is the intersection (A) of the curves (a) and (b). In general, the write characteristics (relationship between the write time and the shift amount of the threshold voltage of the memory transistor) are much better in the snapback region than in the non-snapback region. Therefore, normally, in order to perform good writing, the relationship between the curves (a) and (b) is set such that the operating point is in the snapback region of the curve (a) with good hot electron generation efficiency.

[0007]

In the above-mentioned conventional example, the curve (b) becomes curves (c) and (d) due to variations in the write voltage VPP1 level, variations in the write load transistor due to the process, and the like. Things are not rare. If the write load transistor curve deviates as shown by the curve (c), the operating point enters the area between the five poles of the curve (a), the hot electron generation efficiency decreases, and the write characteristic deteriorates. On the contrary, when the write load transistor curve shifts as shown by the curve (d), the operating point is located above the snapback area of the curve (a), and an overcurrent exceeding the current capacity of the memory transistor flows in the memory transistor. This may lead to destruction of the memory transistor. Even if the memory transistor is not destroyed, the substrate current may increase and a latch-up phenomenon may occur. Since the curve (a) also changes due to process variations and the like like the curve (b), it is very difficult to set the operating point for obtaining good writing.

As a method of limiting the amount of current flowing through a memory transistor at the time of writing, Japanese Patent Application No. 63-599.
No. 10 shows an EPROM writing method using a P-channel transistor as a writing load transistor. However, although this method can certainly limit the amount of current flowing through the memory transistor at the time of writing, the voltage level applied to the bit line BL at the time of reading becomes the VDD level, and the floating gate of the memory transistor selected at the time of reading has an electron. There is a high possibility that an erroneous operation such as erroneous writing in which data is injected or erroneous erasing in which electrons are extracted from the floating gate of a non-selected memory transistor at the time of reading is caused. To prevent the occurrence of erroneous writing and erasing by this method, separate the bit line selection transistor used for writing from the bit line selection transistor used for reading, or clamp the bit line potential at some time during reading. Must.

An object of the present invention is to solve the above problems and to provide a semiconductor device in which electrons are injected into a floating gate.
It is to stabilize the injection amount of electrons.

[0010]

A nonvolatile semiconductor memory device according to the present invention comprises a floating gate and a control gate, and an operation of injecting electrons into the floating gate is performed by hot electrons generated at a drain end, and A non-volatile semiconductor memory device in which memory transistors for extracting electrons from the floating gate are arranged in a matrix, and the control gates of the memory transistors are connected to word lines, drains to bit lines, and sources to source lines. In (1), the amount of current flowing through the memory transistor during the operation of injecting electrons into the floating gate is limited.

The nonvolatile semiconductor memory device according to the present invention comprises a floating gate and a control gate, and the operation of injecting electrons into the floating gate is performed by hot electrons generated at the drain end, and the floating gate is controlled from the floating gate. In the nonvolatile semiconductor memory device, wherein the memory transistors that perform the operation of extracting electrons are arranged in a matrix, and the control gates of the memory transistors are connected to word lines, the drains are connected to bit lines, and the sources are connected to source lines. An interface circuit having a function of converting a voltage amplitude input of VDD-GND into a voltage amplitude input of VPP-GND when performing an operation of injecting electrons into the gate; and an interface circuit connected to the bit line for selecting the bit line. Transistor Between, characterized in that a depletion type transistor connected to the source and gate.

The nonvolatile semiconductor memory device according to the present invention comprises a floating gate and a control gate, and the operation of injecting electrons into the floating gate is performed by hot electrons generated at the drain end, In a nonvolatile semiconductor memory device in which memory transistors that perform an operation of extracting electrons are arranged in a matrix form, the control gates of the memory transistors are connected to word lines, the drains are connected to bit lines, and the sources are connected to source lines. A depletion type transistor having a source and a gate connected between a transistor connected to a line for selecting the bit line and a drain of the memory transistor is provided.

[0013]

According to the above means, it is possible to limit the amount of current flowing in the memory cell at the time of writing, and it is possible to prevent the destruction of the memory transistor and the latch-up phenomenon due to the overcurrent. In addition, it is less susceptible to fluctuations in writing voltage and variations in processes, stable writing can be performed, and unnecessary stress is not applied to the gate oxide film. It is possible to improve.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a write circuit according to a first embodiment of the present invention. Here, in order to simplify the explanation, a four-memory transistor configuration is adopted. However, in reality, a memory cell composed of this memory transistor is formed by arranging a desired number of memory transistors in a matrix. Reference numerals 23 and 24 denote depletion type transistors. The reference numerals are the same as those in FIG. 4 and are omitted. Further, hereinafter, the injection of electrons into the floating gate is referred to as writing.

A writing method will be described with reference to FIG. For example, when writing to the memory transistor 1, first, the output of the NAND circuit 9 is set to GND level (about 0V), NA
The output of the ND circuit 10 is set to VDD level (about 5V), and W
L1 is VPP1 level (about 12.5V), WL2 is GN
Set to D level. Next, the output of the NAND circuit 8 is set to the GND level, and the column decoder circuit 7 turns on the N-channel transistor 5 and turns off the N-channel transistor 6 to set BL1 to the VPP2 level (about 8 V) and BL2 to the open level. Source line SL and substrate are G
It is at the ND level. Then, the memory transistor 1 is selected, the control gate of the memory transistor 1 is at VPP1 level, the drain is at VPP2 level,
The GND level is applied to the source and the substrate.

At this time, high-energy electrons (hot electrons) are generated in the vicinity of the drain due to the avalanche breakdown phenomenon, and these electrons are attracted by the electric field from the control gate to overcome the barrier of the gate oxide film from the substrate and float on the floating gate. Is injected into. In this case, a channel current does not flow in the memory transistors 2 to 4, and avalanche breakdown does not occur, so that electrons are not injected into the floating gate.

On the other hand, at the time of reading, by applying the VDD level to the control gate of the selected memory transistor, data "1" or "0" is determined depending on whether the memory transistor is turned on or off at that time. That is, the threshold voltage of the memory transistor after writing must be higher than the voltage VDD level applied to the control gate of the memory transistor during reading.

Next, FIG. 3 shows a static characteristic curve (a) and a write load transistor characteristic (b) of the memory transistor as an explanation of the operation of the memory transistor at the time of writing of the present invention. When the drain voltage is increased in the curve (a), injection of electrons into the memory transistor begins to occur, and the threshold voltage of the memory transistor increases, so that the current flowing through the memory transistor decreases. Here, the drain voltage indicates the drain voltage of the memory transistor.

When the drain voltage is further increased, the memory transistor causes a snapback phenomenon and a large current flows. Curve (b) is a depletion type transistor having a source and a gate connected to a write load transistor and an N-channel transistor connected in series. When a depletion type transistor in which the source and gate of the write load transistor are connected to each other and an N-channel transistor are used, the write load transistor characteristic shows the same characteristic as the N-channel transistor in a high drain voltage region and a constant current in a low drain voltage region. Become.

The operating point of the memory transistor at the time of writing is the intersection of the curve (a) and the curve (b). In general, the write characteristics (relationship between the write time and the shift amount of the threshold voltage of the memory transistor) are much better in the snapback region than in the non-snapback region. Therefore, normally, in order to perform good writing, the relationship between the curve (a) and the curve (b) is set such that the operating point is in the snapback region of the curve (a) with good hot electron generation efficiency.

Here, like the conventional example, the curve (b) may become curves (c) and (d) due to variations in the write voltage VPP1 level, variations in the write load transistor due to the process, and the like. However, even if the write load transistor curve deviates from the curve (c), the curve (b) is set to have a constant current in the low drain voltage region, so the operating point does not fall within the 5-pole region. It remains in the snapback area. Therefore, the writing efficiency is not lower than that of the conventional example. On the contrary, even if the write load transistor curve deviates as shown in the curve (d), the curve (b) is set so as to have a constant current in the low drain region, so that the operating point is not so much in the snapback region. Not located on top.

Therefore, since the current exceeding the current capacity does not flow through the memory transistor, the memory transistor is not destroyed and the latch-up phenomenon does not occur. The curve (a) also changes due to process variations and the like as in the conventional example, but it is clear that the variation in the operating current of the memory transistor is smaller than in the conventional example. Therefore, the setting of the write load transistor becomes very easy, and the variation in the threshold voltage of the memory transistor after writing becomes small.

The threshold voltage of the memory transistor after writing takes into consideration the write voltage VPP1 level, process variations, etc., and the memory transistor having the worst write characteristic is at the voltage VDD level applied to the control gate of the memory transistor at the time of reading. Set higher. That is, the larger the variation in the write characteristics of the memory transistors in the memory cells arranged in a matrix, the more stress is applied to the memory transistors having good write characteristics, and the number of times of rewriting and the reliability are improved. Not preferred. Therefore, reducing the variation in the threshold voltage of the memory transistor after writing by the above method can improve the number of times of rewriting and further the reliability.

Further, Japanese Patent Application No. 63-5991 shown in the conventional example.
The potential of the bit line at the time of reading, which is a problem of No. 0, will be described. The potential of the bit line in the present invention is (1)
It can be represented by a formula.

VD = VDD− {Vth + γ (VDD + 2ψ) ^1/2 − (2ψ) ^1/2 } (1) where VD is the drain voltage of the memory transistor, Vd
th is the threshold voltage of the write load transistor, γ,
ψ is a constant. As is clear from the expression (1), the voltage VD applied to the drain of the memory transistor is lower than the power supply voltage VDD level by the threshold voltage of the write load transistor or more, and VDD = 5.
At 0V, VD = 1.0 to 2.0V. Therefore, malfunctions such as erroneous writing in which electrons are injected into the floating gate of the memory transistor selected at the time of reading and erroneous erasing such as electrons being drawn from the floating gate of the non-selected memory transistor at the time of reading do not occur.

FIG. 2 shows a write circuit according to the second embodiment of the present invention. The second embodiment is different from the first embodiment in the position of the depletion type transistors 23 and 24. The reference numerals are the same as those in FIG. 1 and are omitted.

Since the writing method is the same as that of the first embodiment, it will be omitted. With respect to the operation of the memory transistor at the time of writing, different parts from those of the first embodiment will be described. The difference between the second embodiment and the first embodiment is that
Although it is a write load transistor, the write load transistor curve is the same as the curve (b) of FIG. 3, and the operation is exactly the same as in the first embodiment.

Although the injection of electrons into the floating gate has been described as a write operation, the effect of the present invention does not change even if the injection of electrons into the floating gate is an erase operation. In the above explanation, E
Although the description has been given by taking the write circuit of the PROM as an example, this is the same effect for all memory transistors as long as it is a memory transistor (for example, flash memory) that injects hot electrons generated by avalanche breakdown into the floating gate. Can be obtained.

[0029]

According to the above structure, the amount of current flowing through the memory cell at the time of writing can be limited, and the destruction of the memory transistor due to overcurrent and the latch-up phenomenon can be prevented. In addition, it is less susceptible to fluctuations in writing voltage and variations in processes, stable writing can be performed, and unnecessary stress is not applied to the gate oxide film. It is possible to improve.

[Brief description of drawings]

FIG. 1 is a write circuit diagram according to a first embodiment of the present invention.

FIG. 2 is a write circuit diagram according to a second embodiment of the present invention.

FIG. 3 is a write operation characteristic diagram in the first and second embodiments of the present invention.

FIG. 4 is a conventional write circuit diagram.

FIG. 5 is a conventional write operation characteristic diagram.

[Explanation of symbols]

 1-4 memory transistors 5 and 6 N channel transistors 7 column decoder circuits 8 to 10 NAND circuits 11 to 16 N channel transistors 17 to 22 P channel transistors 23 and 24 depletion type transistors 25 interface circuits WL1 and 2 word lines BL1 and 2 bits line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 29/788 29/792 H01L 29/78 371

Claims (3)

[Claims] 1. A memory transistor comprising a floating gate and a control gate, wherein the operation of injecting electrons into the floating gate is performed by hot electrons generated at a drain end, and the operation of extracting electrons from the floating gate is a matrix. In a nonvolatile semiconductor memory device in which the control gates of the memory transistors are connected to word lines, the drains are connected to bit lines, and the sources are connected to source lines. A non-volatile semiconductor memory device characterized by limiting the amount of current flowing through it. 2. The nonvolatile semiconductor memory device according to claim 1, wherein a voltage amplitude input of VDD-GND is set to VPP- when performing an operation of injecting electrons into the floating gate.
A depletion type transistor having a source and a gate connected between an interface circuit having a function of converting to a voltage amplitude output of GND and a transistor connected to the bit line for selecting the bit line is provided. Nonvolatile semiconductor memory device. 3. The nonvolatile semiconductor memory device according to claim 1, wherein a source and a gate are connected between a transistor connected to the bit line for selecting the bit line and a drain of the memory transistor. A non-volatile semiconductor memory device comprising a depletion type transistor.