KR100192567B1 - Method of manufacturing semiconductor memory device - Google Patents

Abstract

1. The technical field to which the invention described in the claims belongs:

A program voltage generator for a memory in a nonvolatile peninsula.

2. The technical problem to be solved by the invention:

The present invention provides a program voltage generator, a program voltage generator method, and an erase voltage generator circuit of a nonvolatile semiconductor memory capable of performing a program regardless of a process change.

3. Summary of the solution of the invention:

A program voltage generator for a nonvolatile semiconductor memory, comprising: a trimming circuit for detecting program voltages of selected memory chips after a program, a trimming control circuit for arbitrarily controlling a change in a program voltage level of the trimming circuit, and the detected level. A comparison circuit for generating a comparison signal by comparing a reference voltage output from a reference voltage generator with a reference voltage generator, a pumping circuit for providing a boosted level of the program voltage level, and a fuse connected between the priming circuit and the trimming control circuit. It has a summary that it has a circuit part.

4. Important uses of the invention:

It is suitably used for a nonvolatile semiconductor memory device.

Description

Program voltage generator and erase voltage generator of a nonvolatile semiconductor memory device

1 is a diagram showing a program voltage generation circuit according to the prior art.

2 is a diagram showing a program voltage generation circuit according to the present invention.

3A and 3B are timing diagrams showing timing relationships of trimming signals for controlling program voltages.

The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a program generating device of a nonvolatile semiconductor memory.

A memory array of nonvolatile semiconductor memory (EEPROM) having NAND-structured memory arrays has multiple NAND arrays arranged in a matrix of rows and columns.

The erasing of the memory cells is accomplished by applying an erase voltage, such as a voltage of about 20 volts to the shaped well region of the memory cells, and applying a reference voltage, such as a ground voltage, to the word line. Therefore, the electrons stored in the floating gates exit through the tunnel wells into the type well region and the memory chips are changed into transistors in the depletion mode. Assume that erased memory cells are storing data one.

The writing of a program of memory cells connected to the selected word line, i.e., writing data 0, applies a program voltage, for example a voltage of 18 volts, on the selected word line and the sources and drains of the memory cells into which data 0 is written to a reference voltage, eg This is done by applying a ground voltage. The floating gate of the memory chips being programmed then accumulates electrons through the turnnel oxide films and these memory chips are converted to transistors in the enhancement mode.

After such a program, a program verifying operation is performed to check whether the selected memory cells were successfully programmed to have a predetermined constant threshold value. Such erasure, program and program verification techniques are disclosed in Korean Patent Application Publication No. 94-18870, assigned to the applicant and published on August 19, 1994.

In other words, the conventional NAND type nonvolatile semiconductor memory device refers to an operation of lowering a V element to a negative value by Fowler-Nordheim (F-N) tunneling of a cell. That is, the logic data 1 is written into a cell) and programmed. A program is applied through a conventional FN tunneling by applying a high voltage to the control gate of the EEPROM 구성된 consisting of a floating gate layer and a control gate layer. To make the Vth of 으로 a positive value. That is, the operation of writing data 0 into 쎌 is referred to. At this time, the degree of FN tunneling changes according to the level of the high voltage applied to the control gate, so that the Vth of the power is changed as much as possible. Therefore, the logic data 0 stores the Vth of the stored power within the specific range as much as possible. There are several ways to get Margin.

Conventionally, a method for operating Vth at one level during programming uses a program voltage output device for gradually increasing a program voltage level with a constant spatula, and an implementation thereof is illustrated in FIG.

1 shows a circuit diagram of a method of forming a program voltage level in a conventional NAND type EEPROM.

Referring to FIG. 1, a trimming circuit 20 for sequentially increasing a program voltage Vpgm during a program operation has resistors R1 to R10 and resistor R0 connected in series between a connecting node N2 and a node B. The connection node N1 between the resistor R0 and the resistor R10 and the connection node N2 between the resistor R1 and the NMOS transistor T16 are generally connected to the channel of the N-type transistor T14. The connection nodes between the resistors R10 to R1 and the connection node N2 are connected through the channels of the transistors T5 to T14, respectively. Trimming signals TRM1 to TRM10 are connected to the gates of the transistors T5 to T14, respectively. The transistors T5 to T14 are bypass means for sequentially bypassing the resistors R1 to R10.

The program circuit comprises a comparison circuit for comparing the trimming circuit 20, the voltage levels of the node B and the node A, and outputting a comparison voltage which is an output voltage to an output terminal OUT, and a reference voltage to the node A of the comparison circuit. A reference voltage generator 10 for providing an oscillator, an oscillator 11 for generating an oscillation signal at a constant oscillation cycle, a pumping circuit 13 for raising an output program voltage when an input signal oscillates, and the program voltage Vpgm level the trimming signal to control the providing TRM 1~TRM _{P P} 15 is composed of a decoder circuit 12. The comparison circuit is composed of transistors T1 to T4 and T15.

Referring to FIG. 1, the operation of forming a program voltage level according to the conventional art causes the program voltage to be programmed from the Vpgm initial level of FIG. 3B. After the program is executed, it goes through a process called program verification (same as general reading) that indirectly checks how small the minimum number is located within the desired range. At this time, if the program succeeds, the program operation is stopped, but if the program fails, the program voltage level increases by the increment ΔVpgm at the initial level of Vpgm, and the program is executed again.

If the program operation continues to fail, the program voltage Vpgm continues to increase to reach the maximum program voltage level. If this fails, the program operation continues until the maximum program number is reached without increasing the program voltage level. . For example, if the initial program voltage level is 15V, the maximum number of program repetitions is 20, and the increment △ Vpgm is increased when the program fails, the increment Vpgm is 0.5V and the program voltage level is 15V, 15.5V, 16V, It will increase to 20V and then repeat the program operation while keeping the program voltage level 20. Of course, 20 volts is maintained at a level that prevents destruction of the gate oxide and the gate line of the memory cells. In the prior art, by maintaining the step-by-step spacing in the same manner as above, it was possible to limit the Vth distribution width of 쎌 less than without the step function.

However, since the programmed behavior of the memory array can vary slightly during the process, it is a conventional step that always increases the program voltage level at regular intervals. There is a problem that requires taking levels.

In addition, when programming a NAND type nonvolatile semiconductor memory device in a conventional NAND type nonvolatile semiconductor memory device, when the user wants to program data into the array, the stepped interval of the conventional program voltage Vpgm may be high or low during programming, resulting in excessive program and program failure. have. That is, for example, if a program failure occurs as a result of performing a program operation at a program voltage Vpgm and performing program verification, the next program voltage Vpgm (= Vpgm initial level + ΔVpgm) is increased by a conventional step-by-step program voltage generation circuit. When the program operation is executed in the program verification, the program pass is shown as a program pass, but there is a fear that the actual programmed Vth is out of the desired distribution range. In addition, if there is a concern that this step is to reduce the step-by-step interval, there is a disadvantage in that the program failure occurs in spite of repeated program operation to take a number of step times.

Due to a number of process issues, the program voltage for V may be high or low due to the nature of the memory V array. In order to cope with these various situations, the program operation can be performed by changing the step by step option and changing the level change by step each time to increase or decrease gradually. There is a need for a circuit that can reduce the time programmed and improve the sensing characteristics of the fin by minimizing the Vth distribution width of the fin.

Accordingly, an object of the present invention is to provide a program voltage generator, a program voltage generator, and an erase voltage generator of a nonvolatile semiconductor memory capable of performing a program regardless of a process progress by varying the width of each level. Is in.

Another object of the present invention is to provide a program voltage generator, a program voltage generator method and an erase voltage generator of a nonvolatile semiconductor memory capable of executing a program regardless of changes in peripheral processes.

It is still another object of the present invention to provide a program voltage generator, a program voltage generator, and an erase voltage generator of a nonvolatile semiconductor memory capable of shortening a program time.

According to the technical idea of the present invention to achieve the above objects, a plurality of floating gate type memory cells, program means for programming a plurality of selected memory cells, and a plurality of memory cells selected at three times have been programmed successfully. A program voltage generating device of a nonvolatile semiconductor memory having program verifying means for determining a function, the program voltage being sequentially increased within a range of a predetermined voltage each time the selected memory cells are not successfully programmed after programming. A trimming circuit for detecting the level of the program voltage so as to detect the level of the program voltage or variably changing the change in the program voltage level, and to arbitrarily control the change in the program voltage level of the trimming circuit. A trimming control circuit for adjusting a resistance distribution ratio of the trimming circuit, a comparison circuit for comparing the detected level with a reference voltage generator and generating a comparison signal, and the trimming in response to the comparison signal from the comparison circuit. A pumping circuit for providing a boosted level of the program voltage level for controlling the circuit and the trimming control circuit, and the trimming circuit and the circuit for selecting one of sequential increase or variable increase of the program voltage. A program voltage generator for a nonvolatile semiconductor memory characterized by having a fuse circuit portion connected between trimming control circuits.

Hereinafter, the detailed description of the preferred embodiments of the present invention will be described with reference to the accompanying drawings.

It should be noted that like elements and parts in the drawings represent like reference numerals wherever possible.

2 is a diagram illustrating a program voltage generation circuit for increasing a program voltage according to the present invention.

Referring to FIG. 2, the trimming control circuit 21 for variably changing the increase in the preset program voltage of the trimming circuit 20 may include resistors r1 between the node B and the ground power supply of FIG. R15 and a resistor r0 are connected in series, and a connection node N3 between the resistor r0 and a resistor r15 and a connection node N4 between the resistor r1 and the enMOS transistor T36 are connected through a channel of the N-type transistor T31. Resistors r15-r! The connection nodes between the connection nodes and the connection node N4 are connected through the channels of the transistors T17 to T31, respectively. Trimming signals TRM _P 1 to TRM _P 15 are connected to the gates of the transistors T17 to T31, respectively. The transistors T17 to T31 are bypass means for sequentially bypassing the resistors r1 to r15.

Selection of the trimming circuit 20 to perform the sequential increase of the program voltage and the trimming control circuit 21 to perform the variable increase of the program voltage are made by the fuse circuit unit 23. The fuse circuit unit 23 includes a fuse F1, transistors T32 and T33, and an inverter G5.

Looking at the step-by-step generation of the program voltage, which is the core of the present invention through FIG. 2 as follows.

The comparison circuit, which is a differential amplifier, operates when the transistor T15 is on, that is, when the input signal IN is at a high level. At this time, when the input voltage level VA of the node A is greater than the level VB of the node B due to the characteristics of the differential amplifier, the output node OUT tries to maintain the high level. At this time, the output voltage of the oscillator 11 is controlled by the logic gates G1 to G4. Outputs this signal By boosting the program voltage Vpgm through the pumping action in the high voltage generation circuit, that is, the pumping circuit 13 as an input. In contrast, when the VB is greater than VA, the node OUT tries to maintain the low level. By this node level, the output voltage of the oscillator 11 can no longer be transferred to the input of the pumping circuit 13, which is a high voltage generating circuit, and as a result, the program voltage Vpgm no longer increases and stays. That is, the pumping circuit 13 is boosted only while the oscillation signal φR, is oscillated. Here, VB of the two input voltages of the comparison circuit is determined by the resistors R0 to R10, where the connected transistors T5 to T14 are all off, that is, if the trimming signals TRM _P 1 to TRM _P 10 are all at the logic low level, the voltage VB Can be expressed as below by the voltage distribution distribution principle.

Therefore, to increase the program voltage Vpgm level while maintaining VB in the above equation, the resistance R value can be reduced. That is, as described above, the circuit for reducing the resistance R is the trimming circuit 20 and is composed of the resistors R0 to R10 connected in series and the trimming signals TRM _P 1 to TRM _P 10 which are input signals of the transistor connected thereto. The resistors R1 to R10 are resistors for the step-by-step adjustment of the program voltage Vpgm level so that the resistance r value in the above equation can be changed by the trimming signals TRM _P 1 to TRM _P 10 which are input signals connected thereto. For example, when the level of the trimming signal TRM _P 1 output from the decoder 12 changes from a low level to a high level (the remaining input signals TRM _P 2 to TRM _P 10 remain low), the value of the resistance R in the above formula Is changed from R to R-R1, and as a result, the detected program voltage Vpgm level increases from the initial Vpgm level to the initial Vpgm level + DELTA Vpgm. That is, the program voltage Vpgm level can be changed at regular intervals by the step adjustment resistors and the trimming signals TRM _P 1 to TRM _P 10 connected thereto. If these inputs by converting the signal of the trimming signal TRM 1~TRM _{P P} 10 to high level one by one to increase the constant T5~T14 transistors connected to it in a stepwise manner. A timing diagram for this is shown in FIG. 3B.

That is, the program voltage may be increased when the program is executed through the trimming circuit 20. However, as previously mentioned, the programmed pulse characteristics of the memory array can vary slightly during the process, so conventional stepwise adjustments that always increase the program voltage level at regular intervals can cause excessive program and program failure. There is a problem that should take many step levels by reducing the step interval. That is, a large number of series-connected resistors and transistors connected thereto are required, and the program time is long. As part of the effort to improve this problem, it has been passively coped with the above problem by changing the initial level of the program voltage by changing the level of the input voltage of the comparator with the optional constant voltage generator in the reference constant voltage generator. Therefore, an improved method is needed. In the present invention, a method of processing a plurality of step by step options and a step-by-step step (by gradually increasing or decreasing the step change width) are solved.

In the present invention, in order to solve this problem, as shown in FIG. 2, the series-connected resistors r0 to r15 for step adjustment are connected in parallel (these resistance ratios for the program voltage Vpgm level step are different). As an example, one of the two cases can be selected and used to cope with the above-mentioned problems. When the fuse F1 is not blown by connecting the EnMOS transistors T34 and T36 to a series connected resistance connection, the transistor T34 is turned on to use the trimming circuit 20 as a step adjustment circuit and to blow the fuse F1. The transistor T36 is turned on so that the trimming control circuit 21 can be used as the step adjustment circuit.

In addition, if the trimming control retrospective 21 adjusts the program voltage Vpgm at regular intervals instead of stepwise adjusting the trimming control recall 21 at a variable interval (gradual increase or decrease). The large number of steps can be reduced, so that the circuit reduction effect and the program time can be reduced.

Although the present invention has been carried out mainly on the program voltage generation circuit, they may be also implemented on the erase voltage generation circuit within the range of obtaining the same effect. That is, it can be applied more suitably to the multi-state memory under development recently.

Therefore, as described above, the present invention has the effect of reducing the program time. In addition, the present invention has the effect that the program can be carried out irrespective of process changes.

Although the present invention described above is limited to, for example, the drawings, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the technical spirit of the present invention.

Claims (10)

A program of a nonvolatile semiconductor memory having a plurality of floating gate type memory chips, program means for programming a plurality of selected memory chips, and program verifying means for determining whether the selected plurality of memory chips have been successfully programmed. In the voltage generator, the program voltage is detected or the change width of the program voltage level is changed so that the program voltage is sequentially increased within a range of a predetermined voltage whenever the selected memory chips are not successfully programmed after the program. A trimming circuit for detecting the level of the program voltage so as to increase by increasing the value of the program voltage, and a trimming control circuit for adjusting the resistance distribution ratio of the trimming circuit to arbitrarily control a change in the program voltage level of the trimming circuit. And a comparison circuit for comparing the detected level with a reference voltage from a reference voltage generator and generating a comparison signal, and for controlling the trimming circuit and the trimming control circuit in response to the comparison signal from the fertilizer circuit. A pumping circuit for providing a boosted level of the program voltage level, and a fuse circuit section connected between the trimming circuit and the trimming control circuit for selecting one of two methods of sequential increase or variable increase of the program voltage. Programmable generator of memory on a nonvolatile peninsula characterized by having a. The trimming circuit of claim 1, wherein the trimming circuit comprises: a plurality of resistors connected in series between a program voltage generating terminal and a ground voltage; and a plurality of resistors for bypassing the plurality of resistors, respectively, in order to sequentially increase the program voltage. Program voltage generator of a nonvolatile semiconductor memory, characterized in that consisting of transistors. 3. The trimming control circuit according to claim 2, wherein the trimming control circuit comprises a plurality of resistors connected in series between a detection level terminal of the trimming circuit and a ground voltage, and the plurality of resistors for variably increasing the program voltage using resistance distribution. A program voltage generator of a nonvolatile semiconductor memory, characterized by comprising a plurality of transistors for bypassing resistors respectively. 4. The program voltage generation of a nonvolatile semiconductor memory according to claim 2 or 3, wherein the trimming circuit and the trimming control circuit have a plurality of bypass means to increase the program voltage to a voltage having a predetermined width. Device. 5. The program voltage generator of claim 4, further comprising a trimming signal generation circuit connected to the plurality of bypass means and sequentially increasing the program voltage. Erasing a nonvolatile semiconductor memory having a plurality of floating gate type memory chips, erasing means for erasing a plurality of selected memory cells, and erasing verification means for determining whether the selected plurality of memory cells have been successfully erased. In the voltage generator, the level of the erase voltage is detected or the change width of the erase voltage level is increased so that the erase voltage increases manually within a range of a predetermined voltage every time the selected memory cells are not successfully erased after the erase. A trimming circuit for detecting the level of the erase voltage so as to variably change and increasing; a trimming control circuit for adjusting a resistance distribution ratio of the trimming circuit to arbitrarily control a change width of the erase voltage level of the trimming circuit; Detected level and reference voltage from the reference voltage generator A comparison circuit for comparing and generating a comparison signal, and a pumping circuit for providing a boosted level of the erase voltage level for controlling the trimming circuit and the trimming control circuit in response to the comparison signal from the comparison circuit; And a fuse circuit portion connected between the trimming circuit and the trimming control circuit to select one of two methods of sequentially increasing or erasing the erase voltage. 7. The trimming circuit of claim 6, wherein the trimming circuit comprises a plurality of resistors connected in series between an erase voltage generation terminal and a ground voltage, and a plurality of resistors for bypassing the plurality of resistors, respectively, in order to sequentially increase the erase voltage. An erase voltage generator of a nonvolatile semiconductor memory, characterized by comprising transistors. 8. The trimming control circuit according to claim 7, wherein the trimming control circuit comprises a plurality of resistors connected in series between a detection level terminal of the trimming circuit and a ground voltage, and the plurality of resistors for variably increasing the erase voltage using resistance distribution. An erase voltage generator of a nonvolatile semiconductor memory, characterized in that it comprises a plurality of transistors for bypassing resistors respectively. 9. The generation of an erase voltage of a nonvolatile semiconductor memory according to claim 7 or 8, wherein the trimming circuit and the trimming control circuit have a plurality of bypass means to increase the erase voltage to a voltage having a predetermined width. Device. 10. The erase voltage generator of claim 9, further comprising a trimming signal generation circuit connected to the plurality of bypass means and sequentially increasing the erase voltage.