KR100572332B1 - Non-volatile memory device and program method thereof - Google Patents

Abstract

A method of programming a nonvolatile memory device disclosed herein includes: applying a word line voltage and a bulk voltage to a memory cell according to a predetermined program condition during an Nth program period; Detecting whether the bulk voltage is higher than a detection voltage during the Nth program period; And determining a program condition of the (N + 1) th program section according to the detection result.

Description

Non-volatile memory device and its program method {NON-VOLATILE MEMORY DEVICE AND PROGRAM METHOD THEREOF}

1 shows a change in word line voltage and a change in threshold voltage during programming;

2 is a block diagram schematically illustrating a nonvolatile memory device according to the present invention;

3 is a block diagram showing the step hold circuit shown in FIG. 2 in accordance with an embodiment of the present invention;

4 is a timing diagram illustrating a program operation of a nonvolatile memory device according to the present invention; And

5 and 6 are block diagrams illustrating the step hold circuit shown in FIG. 2 in accordance with other embodiments of the present invention.

Explanation of symbols on the main parts of the drawings

100 nonvolatile memory device 110 memory cell array

120: row selection circuit 130: column selection circuit

140: sense amplifier circuit 150: write driver circuit

160: bit line voltage generation circuit 170: step hold circuit

180: pass / fail check circuit 190: control logic

200: step control circuit 210: word line voltage generation circuit

The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile memory device.

Semiconductor memories are generally the most essential microelectronic devices of digital logic designs, such as computers and applications based on microprocessors, which range from satellite to consumer electronics technology. Therefore, advances in the manufacturing technology of semiconductor memories, including process improvement and technology development, achieved through scaling for high integration and high speed, help to establish performance criteria for other digital logic families.

The semiconductor memory device is largely divided into a volatile semiconductor memory device and a nonvolatile semiconductor memory device. In a volatile semiconductor memory device, logic information is stored by setting a logic state of a bistable flip-flop in the case of static random access memory or through charging of a capacitor in the case of dynamic random access memory. In the case of a volatile semiconductor memory device, data is stored and read while power is applied, and data is lost when power is cut off.

Nonvolatile semiconductor memory devices such as MROM, PROM, EPROM, and EEPROM can store data even when the power is cut off. The nonvolatile memory data storage state is either permanent or reprogrammable, depending on the manufacturing technique used. Nonvolatile semiconductor memory devices are used for the storage of programs and microcode in a wide range of applications such as the computer, avionics, telecommunications, and consumer electronics industries. The combination of volatile and nonvolatile memory storage modes on a single chip is also available in devices such as nonvolatile RAM (nvRAM) in systems that require fast and reprogrammable nonvolatile memory. In addition, specific memory structures have been developed that include some additional logic circuitry to optimize performance for application-oriented tasks.

In the nonvolatile semiconductor memory device, the MROM, PROM and EPROM are not free to erase and write in the system itself, so that it is not easy for ordinary users to update the storage contents. On the other hand, since EEPROMs can be electrically erased and written, applications to system programming or auxiliary storage devices requiring continuous updating are expanding.

As an example of a nonvolatile memory device, a flash memory device is a kind of EEPROM in which a plurality of memory areas are erased or programmed in one program operation. A typical EEPROM allows only one memory area to be erased or programmable at a time, which allows the flash memory device to operate at a faster and more efficient speed when systems using the flash memory device read and write to other memory areas at the same time. It means that there is. All forms of flash memory and EEPROM are worn out after a certain number of erase operations due to the wear of the insulating film surrounding the charge storage means used to store the data.

Flash memory devices store information on the silicon chip in a manner that does not require a power source to maintain the information stored on the silicon chip. This means that if the power to the chip is interrupted, the information is maintained without consuming power. In addition, flash memory devices provide physical shock resistance and fast read access times. Because of these features, flash memory devices are commonly used as storage devices for devices powered by batteries. There are two types of flash memory devices, NOR flash memory devices and NAND flash memory devices, depending on the type of logic gate used for each storage element.

Flash memory devices store information in an array of transistors called cells, with each cell storing one-bit information. Newer flash memory devices, called multi-level cell devices, can store more than one bit per cell by varying the amount of charge placed on the floating gate of the cell.

In a NOR flash memory device, each cell is similar to a standard MOSFET transistor except that it has two gates. The first gate is a control gate (CG) as in other MOS transistors, but the second gate is an insulated floating gate (FG) surrounded by an insulating film. The floating gate is between the control gate and the substrate (or bulk). Since the floating gate is insulated by the insulating film, electrons placed in the floating gate are trapped and thus store information. When the electrons lie in the floating gate, the electric field from the control gate is changed (partially canceled) by the electrons, which causes the cell's threshold voltage (Vt) to change. Thus, when a cell is read by applying a specific voltage to the control gate, current may or may not flow depending on the threshold voltage of the cell. This is controlled by the amount of charge in the floating gate. The presence or absence of a current is detected and interpreted as 1 or 0, so the stored data is reproduced. In multi-level cell devices that store more than 1-bit per cell, the amount of current flowing rather than the presence or absence of current will be sensed to determine the amount of electrons stored in the floating gate.

The NOR flash cell is programmed (set to a specific data value) by applying a program voltage on the control gate and a high voltage of 5-6V to the drain with the source grounded. According to this bias condition, a large amount of cell current flows from the drain to the source. This programming approach is called hot-electron injection. A large voltage difference is applied between the control gate and the substrate (or bulk) to erase the NOR flash cell, which causes electrons to escape from the floating gate through F-N tunneling. The components of a NOR flash memory device are divided into erase segments, commonly referred to as blocks or sectors. All memory cells in a block are erased at the same time. NOR programming, however, may be performed in bytes or words.

In order to tightly and accurately control the threshold voltage distribution (distribution) of programmed memory cells, an incremental step pulse programming (ISPP) scheme has generally been used. According to the ISPP scheme, as shown in FIG. 1, the program voltage V _WL applied to the word line is increased step by step as program loops of a program cycle are repeated. Each program loop, as is well known, consists of a program interval and a program verify interval, and the program voltage V _WL increases by a predetermined increment ΔV. As the program operation proceeds, the threshold voltage Vt of the cell to be programmed increases by a predetermined increment DELTA V in each program loop. Therefore, in order to narrow the width of the threshold voltage distribution of the finally programmed cell, the increment (ΔV) of the program voltage should be set small. The smaller the increase in program voltage, the larger the number of program loops in the program cycle. Thus, the number of program loops will be determined to obtain an optimal threshold voltage distribution without limiting the performance of the memory device.

An exemplary program method of a nonvolatile memory device using the ISPP method is U.S. Patent No. 6,266,270 entitled "NON-VOLATILE SEMICONDUCTOR MEMORY AND PROGRAMMING METHOD OF THE SAME." Exemplary circuits for generating a program voltage according to an ISPP scheme are described in U.S. patent No. 5,642,309 titled "AUTO-PROGRAM CIRCUIT IN A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE" and Korean Patent Publication No. 2002-39744 entitled "FLASH MEMORY DEVICE CAPABLE OF PREVENTING PROGRAM DISTURB AND METHOD OF PROGRAMMING THE SAME" have.

When programming a NOR flash memory device using an ISPP scheme, as mentioned above, a word line voltage of 10V is applied to the control gate of the flash cell, a bit line voltage of 5V-6V to its drain, and a flash cell. The bulk (or substrate) of is applied with a voltage lower than zero (e.g., -1V). In general, the cell current Icell flowing through the memory cell is proportional to (V _GS -Vt) ² (Vt is the threshold voltage of the memory cell and V _GS is the gate-source voltage of the memory cell). The bit line voltage is generated / maintained by a charge pump (not shown) for the bit line voltage. If the amount of cell current flowing through the memory cell exceeds the capacity of the charge pump for the bulk voltage, the bulk voltage rises above the specified voltage. As the bulk voltage is lowered, as indicated by the dashed line in FIG. 1, the threshold voltage of the flash cell does not increase by the desired voltage within any program loop. In particular, when programming using the ISPP scheme, the difference between the word line voltage and the threshold voltage of the flash cell increases more and more as the program loops are repeated, resulting in further deterioration of program characteristics and ultimately program failure.

Therefore, there is an urgent need for a new technology that can prevent program failure due to an increase in bulk voltage during programming.

It is an object of the present invention to provide a nonvolatile memory device and a program method thereof that can improve program characteristics.

Another object of the present invention is to provide a nonvolatile memory device and a program method thereof for controlling an increase in a word line voltage of a next program loop according to a change of a bulk voltage of a current program loop.

It is still another object of the present invention to provide a nonvolatile memory device and a program method thereof that can prevent program failure due to a drop in bulk voltage during programming.

According to one aspect of the present invention for achieving the above-mentioned objects, a method of programming a nonvolatile memory device includes the steps of applying a word line voltage and a bulk voltage to a memory cell in accordance with a predetermined program condition during the N-th program period; ; Detecting whether the bulk voltage is higher than a detection voltage during the Nth program period; And determining a program condition of the (N + 1) th program section according to the detection result.

In a preferred embodiment, the program condition includes an incremental step pulse programming scheme.

In an exemplary embodiment, the determining of the program condition may include setting the program condition of the (N + 1) th program period when the bulk voltage is higher than the detection voltage during the Nth program period. Maintaining the same as the condition.

In an exemplary embodiment, the determining of the program condition may include setting the program condition of the (N + 1) th program period to the Nth program when the bulk voltage is maintained higher than the detection voltage during the Nth program period. And setting differently from the program condition of the interval.

In a preferred embodiment, when the bulk voltage is higher than the detection voltage during the Nth program period, the word line voltage of the (N + 1) th program period is maintained to be the same as the wordline voltage of the Nth program period. do.

In a preferred embodiment, when the bulk voltage is maintained lower than the detection voltage during the Nth program period, the word line voltage of the (N + 1) th program loop is predetermined than the word line voltage of the Nth program period. Is increased by.

In a preferred embodiment, the detecting step is performed during the supply period of the bit line voltage. Alternatively, the detecting step is performed for every program period.

According to another aspect of the present invention, a method of programming a nonvolatile memory device according to an incremental step pulse programming scheme includes supplying a word line voltage and a bulk voltage to a memory cell during an Nth program period; Detecting whether the bulk voltage is higher than a detection voltage; And when the bulk voltage is higher than the detection voltage in the Nth program period, the word line voltage having the same level as the Nth program period during the (N + 1) th program period together with the bulk voltage. Applying to the cell.

In an exemplary embodiment, when the bulk voltage is lower than the detection voltage in the N-th program period, the word line voltage that is increased by a predetermined increase from the word line voltage of the N-th program period is the (N + 1) th program. The bulk voltage is applied to the memory cell during the period.

In a preferred embodiment, the detecting step is performed during the supply period of the bit line voltage. Alternatively, the detecting step is performed for every program period.

According to still another aspect of the present invention, a nonvolatile memory device includes: a first voltage generation circuit for generating a first program voltage to be supplied to a memory cell; A second voltage generator circuit for generating a second program voltage to be supplied to the memory cell; And a control circuit for controlling the first voltage generation circuit according to whether the second program voltage is higher than the detection voltage, and when the second program voltage is higher than the detection voltage in an Nth program loop, The control circuit controls the first voltage generation circuit such that the first program voltage of the (N + 1) th program loop is kept equal to the first program voltage of the Nth program loop.

In a preferred embodiment, when the second program voltage is lower than the detection voltage in the Nth program loop, the control circuitry is further configured such that the first program voltage of the (N + 1) th program loop is equal to the Nth program loop. The first voltage generating circuit is controlled to be higher by a predetermined increment than the first program voltage.

In a preferred embodiment, the first program voltage is a word line voltage and the second program voltage is a bulk voltage.

In a preferred embodiment, the control circuit further comprises: control logic for generating a step-up pulse signal in every program loop; A step hold circuit for activating a step hold signal depending on whether the second program voltage is higher than the detected voltage; And a step control circuit for controlling the first program voltage generation circuit in response to the step-up pulse signal and the step hold signal.

In a preferred embodiment, when the step hold signal is activated in the N-th program period, the step control circuit is configured such that the first program voltage of the (N + 1) -th program loop is equal to the first program of the N-th program loop. The first program voltage generation circuit is controlled to remain the same as the voltage.

In a preferred embodiment, when the step hold signal is deactivated in the N-th program period, the step control circuit is configured such that the first program voltage of the (N + 1) -th program loop is equal to the first program of the N-th program loop. The first program voltage generation circuit is controlled to increase by a predetermined voltage rather than a voltage.

In a preferred embodiment, the step hold circuit detects the second program voltage under the control of the control logic during the program period of every program loop.

In a preferred embodiment, the step hold circuit detects the second program voltage under the control of the control logic during the supply period of the second program voltage in every program loop.

Exemplary embodiments of the invention will be described in detail below on the basis of reference drawings. The nonvolatile memory device according to the present invention is a NOR flash memory device. However, it will be apparent to those skilled in the art that the present invention can be applied to other memory devices (eg, MROM, PROM, FRAM, NAND type flash memory devices, etc.). In a nonvolatile memory device, a program cycle includes a plurality of program loops, each program loop including a program section and a program verify section. As is well known, input data is programmed in selected memory cells in a program section, and whether or not selected memory cells are correctly programmed in a program verify section. In the case of a nonvolatile memory device using an ISPP scheme, the word line voltage will gradually increase by a predetermined value as the program loops are repeated.

2 is a block diagram schematically illustrating a nonvolatile memory device according to the present invention. Referring to FIG. 2, a nonvolatile memory device 100 according to the present invention includes a memory cell arranged in a matrix of rows (or word lines) WL0-WLm and columns (or bit lines) BL0-BLn. Memory cell array 110 having the same. The row select circuit 120 selects one of the word lines WL0-WLm according to the row address information, and drives the selected word line to the word line voltage V _WL from the word line voltage generation circuit 210. . The column select circuit 130 selects the bit lines BL0-BLn in a predetermined unit (for example, a word unit or a byte unit) according to the column address information. The sense amplifier circuit 140 senses data bits from memory cells of the selected word line and bit lines. The data bits read by the sense amplification circuit 140 may be output externally or passed to the pass / fail check circuit 180 depending on the mode of operation. For example, in the read operation mode, data bits read by the sense amplifier circuit 140 are output to the outside. During the program verification period in the program operation mode, the data bits read by the sense amplifier circuit 140 are output to the pass / fail check circuit 180.

The write driver circuit 150 operates in response to the bit line enable signal BLEN in the program operation mode, and selects the bit lines selected from the bit line voltage generation circuit 220 according to the data to be programmed. To drive. For example, when the data to be programmed is program data, the write driver circuit 150 drives the bit line selected by the column select circuit 130 to the bit line voltage VBL. If the data to be programmed is program-inhibited data, the write driver circuit 150 drives the bit line selected by the column select circuit 130 to a voltage lower than the bit line voltage VBL (eg, ground voltage). . The bulk voltage generator circuit 160 generates the bulk voltage VBULK as a program voltage in response to the control of the control logic 190. The step hold circuit 170 is configured to operate in response to the bit line enable signal BLEN, and detects whether or not the bulk voltage VBULK is higher than a set detection voltage during the program period. The step hold circuit 170 generates a step hold signal STEP_HOLD according to the detection result. For example, if the bulk voltage VBULK is kept lower than the set detection voltage for every program period, the step hold circuit 170 causes the step hold signal STEP_HOLD to be deactivated. When the bulk voltage VBULK becomes higher than the detection voltage set for every program period, the step hold circuit 170 causes the step hold signal STEP_HOLD to be activated.

Subsequently, the pass / fail check circuit 180 determines whether all of the data bits output from the sense amplifying circuit 140 have a program state during the program verification interval, and outputs the pass / fail signal PF as the determination result. Output The control logic 190 is configured to control the overall operation of the nonvolatile memory device in accordance with the operation mode. The control logic 190 activates the bit line enable signal BLEN in every program period of the program cycle. During every program verify interval of the program cycle, control logic 190 determines the end of the program cycle in response to the pass / fail signal PF. For example, when the pass / fail signal PF indicates a program pass, control logic 190 ends the program cycle. When the pass / fail signal PF indicates a program fail, the control logic 190 controls the program cycle so that the next program loop is executed. For example, the control logic 190 generates a step-up pulse signal STEP_UP every time a program verify operation ends.

The step control circuit 200 operates in response to the step-up pulse signal STEP_UP and the step hold signal STEP_HOLD, and the word line voltage generation circuit 210 so that the word line voltage V _WL is gradually increased during the program cycle. ). When the step-up pulse signal STEP_UP is generated with the step hold signal STEP_HOLD deactivated, the step control circuit 200 causes the word line to increase by a predetermined value from the value of the previous program loop without increasing the word line voltage. The voltage generator circuit 210 is controlled. When the step-up pulse signal STEP_UP is generated with the step hold signal STEP_HOLD enabled, the step control circuit 200 causes the word line voltage generator circuit (B) to maintain the word line voltage at the value of the previous program loop. 210 is controlled. The word line voltage generation circuit 210 generates the word line voltage V _WL in response to the control of the step control circuit 200. An exemplary word line voltage generator circuit 210 using an ISPP scheme is described in US Pat. 5,642,309 and Korean Patent Publication No. 2002-39744, which are incorporated by reference herein.

As can be seen from the above description, when the bulk voltage VBULK becomes higher than the set detection voltage in the program section of the N-th program loop, the step hold signal STEP_HOLD is activated. When the step hold signal STEP_HOLD is activated, the word line voltage generation circuit 210 maintains the word line voltage equal to the previous program loop in the program section of the step control circuit 200 (N + 1) th program loop. To control. That is, in the nonvolatile memory device using the ISPP scheme, when the bulk voltage VBULK becomes higher than the set detection voltage in the program section of the N-th program loop, the N-th and (N + 1) -th program loops have the same level. The word line voltage is supplied to the selected word line. This means that memory cells are programmed two or more times under the same program condition.

In this embodiment, the step hold circuit 170, the control logic 190, and the step control circuit 200 may determine the word line voltage generation circuit 210 depending on whether the bit line voltage VBL is lower than the detected voltage. Configure the control circuit to control.

FIG. 3 is a block diagram showing the step hold circuit shown in FIG. 2 in accordance with a preferred embodiment of the present invention.

Referring to FIG. 3, the step hold circuit 170 according to the present invention includes a detector 171, a pulse generator 172, and a latch 173. The detector 171 operates in response to the bit line enable signal BLEN and detects whether the bulk voltage VBULK is higher than the set detection voltage. The detector 171 generates a detection signal DET as a detection result. The detector 171 operates during the activation period of the bit line enable signal BLEN. However, the detector 171 can be implemented to operate for every program period. The pulse generator 172 generates an initialization pulse signal RST in response to the low-high transition of the bit line enable signal BLEN. The latch 173 includes an input terminal D for receiving a bit line enable signal BLEN, a clock terminal CLK for receiving a detection signal DET, and an output terminal Q for outputting a step hold signal STEP_HOLD. Has

In circuit operation, when the bit line enable signal BLEN transitions from low level to high level, the pulse generator 172 generates an initialization pulse signal RST. The step hold signal STEP_HOLD is initialized low by the initialization pulse signal RST. At the same time, when the bit line enable signal BLEN transitions from low level to high level, the detector 171 detects whether the bulk voltage VBULK is higher than the set detection voltage. If the bulk voltage VBULK is higher than the set detection voltage, the detection signal DET transitions from the low level to the high level. The latch 173 latches the bit line enable signal BLEN in response to the low-high transition of the detection signal DET. Since the bit line enable signal BLEN remains high within the program period, the step hold signal STEP_HOLD becomes high in synchronization with the low-high transition of the detection signal DET. The detector 171 is initialized upon deactivation of the bit line enable signal BLEN, and as a result, the detection signal DET is initialized to low every time the program section ends.

4 is a timing diagram illustrating a program operation of a nonvolatile memory device according to the present invention. Hereinafter, the program operation of the nonvolatile memory device according to the present invention will be described in detail with reference to the accompanying drawings.

As the program command is input, the bulk voltage generator circuit 160, the word line voltage generator circuit 210, and the bit line voltage generator circuit 220 are controlled to the bulk voltage VBULK, the word under the control of the control logic 190. Start generating the line voltage, and the bit line voltage VBL. After the word line voltage, bulk voltage, and bit line voltage are generated, the program operation of the first program loop will be performed under the control of control logic 190. For example, the control logic 190 controls the row select circuit 120 so that the word line voltage is supplied to the selected word line and activates the bit line enable signal BLEN. As the bit line enable signal BLEN is activated, the write driver circuit 150 supplies the bit line voltage VBL to the bit line (s) selected by the column select circuit 130. In addition, a bulk voltage VBULK is supplied to the memory cell array 110. Under this program condition, the selected memory cell (s) begin to be programmed.

At the same time, the latch 173 of the step hold circuit 170 is initialized at the low-high transition of the bit line enable signal BLEN, and as a result, the step hold signal STEP_HOLD is initialized to low. During the activation period of the bit line enable signal BLEN, the detector 171 detects whether the bulk voltage VBULK has risen above the set detection voltage Vt. The detection voltage Vt is higher than the target voltage of the bulk voltage VBULK (for example, -1 V) and lower than the ground voltage. As shown in FIG. 4, since the bulk voltage VBULK is kept lower than the detection voltage Vt during the first program period, the detection signal DET is kept low. That is, in the first program section, the step hold signal STEP_HOLD is kept low. Thereafter, the bit line enable signal BLEN is deactivated low and the voltage on the word line is discharged. That is, the first program section ends.

After the first program interval ends, the program verify operation of the first program loop will be performed. In the program verification interval, whether the selected memory cells are correctly programmed will be determined by the sense amplifier circuit 140, the pass / fail check circuit 180, and the control logic 190 according to a well-known method. If the pass / fail signal PF indicates a program fail, the control logic 200 generates a step-up pulse signal STEP_UP. The step control circuit 200 controls the word line voltage generation circuit 210 in response to the step-up pulse signal STEP_UP and the step hold signal STEP_HOLD. Since the step hold signal STEP_HOLD indicates that the bulk voltage VBULK is kept lower than the detection voltage in the first program section, the step control circuit 200 sets the word line voltage V _WL by a predetermined value ΔV. The word line voltage generation circuit 210 is controlled to be increased.

When the second program loop begins, the program operation will be performed in the same manner as described above. While the program operation of the second program loop is performed, as in the above description, the detector 171 detects whether the bulk voltage VBULK has risen above the set detection voltage Vt. If the bulk voltage VBULK rises above the detection voltage Vt, the detection signal DET is activated from the low level to the high level, as shown in FIG. At this time, the output signal of the latch 173, that is, the step hold signal STEP_HOLD transitions from the low level to the high level in synchronization with the low-high transition of the detection signal DET. Under these conditions, the program operation of the second program loop will be terminated. The detection signal DET is inactivated low when the bit line enable signal BLEN is inactivated, as shown in FIG. 4.

After the second program interval ends, the program verify operation of the second program loop will be performed. In the program verification interval, whether the selected memory cells are correctly programmed will be determined by the sense amplifier circuit 140, the pass / fail check circuit 180, and the control logic 190 according to a well-known method. If the pass / fail signal PF indicates a program fail, the control logic 200 generates a step-up pulse signal STEP_UP. The step control circuit 200 controls the word line voltage generation circuit 210 in response to the step-up pulse signal STEP_UP and the step hold signal STEP_HOLD. As described above, since the step hold signal STEP_HOLD indicates that the bulk voltage VBULK has risen above the detection voltage in the second program period, the step control circuit 200 may increase the word line voltage V _WL . The word line voltage generation circuit 210 is controlled to be maintained at the voltage level of the previous program section without increasing the predetermined value ΔV.

When the third program loop starts, the program operation will be performed in the same manner as described above. The program condition of the third program section is the same as the program condition of the second program section. That is, as shown in FIG. 4, the word line voltage V _WL of the third program period is kept the same as the word line voltage of the second program period without increasing the predetermined value ΔV. Except for this, the program operation of the third program loop will be performed as described previously. However, as shown in FIG. 4, the step hold signal STEP_HOLD is initialized to low when the bit line enable signal BLEN is activated in the third program period. Thereafter, the program loops will be repeated within a predetermined number of program loops until the selected memory cells have the required threshold voltage.

In conclusion, the program condition of the next program loop is determined according to whether or not the bulk voltage VBULK is higher than the set detection voltage Vt in the program period of any program loop. According to this programming method, the program condition of the next program loop is controlled to be the same as or different from the program condition of the previous program loop according to the change of the bulk voltage VBULK, thereby preventing program fail due to the drop of the bulk voltage VBULK. can do.

In the above, the configuration and operation of the circuit according to the present invention has been shown in accordance with the above description and drawings, but this is only an example, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Of course.

As described above, according to the change of the bulk voltage of the current program loop, by controlling the program condition of the next program loop the same or differently than the program loop of the previous program loop, it is possible to prevent program fail due to the drop of the bulk voltage. . Therefore, the program characteristic can be improved.

Claims (20)

How to program a nonvolatile memory device: Applying a word line voltage and a bulk voltage to a memory cell according to a predetermined program condition during an Nth program period; Detecting whether the bulk voltage is higher than a detection voltage during the Nth program period; And And determining a program condition of the (N + 1) th program section according to the detection result. The method of claim 1, The program condition comprises an incremental step pulse programming scheme. The method of claim 1, Determining the program condition is And maintaining the program condition of the (N + 1) th program period equal to the program condition of the Nth program when the bulk voltage becomes higher than the detection voltage during the Nth program period. Way. The method of claim 1, Determining the program condition is And setting the program condition of the (N + 1) th program section different from the program condition of the Nth program section when the bulk voltage is maintained higher than the detection voltage during the Nth program section. How to. The method of claim 4, wherein When the bulk voltage is higher than the detection voltage during the Nth program period, the word line voltage of the (N + 1) th program period is maintained to be the same as the wordline voltage of the Nth program period. . The method of claim 4, wherein When the bulk voltage is maintained lower than the detection voltage during the Nth program period, the word line voltage of the (N + 1) th program loop is increased by a predetermined increase from the wordline voltage of the Nth program period. How to feature. The method of claim 1, And said detecting step is performed during the supply period of the bit line voltage. The method of claim 1, The detecting step is performed during every program period. In a method of programming a nonvolatile memory device according to an incremental step pulse programming scheme: Supplying a word line voltage and a bulk voltage to a memory cell during an Nth program period; Detecting whether the bulk voltage is higher than a detection voltage; And When the bulk voltage is higher than the detection voltage in the Nth program section, the word line voltage having the same level as the Nth program section during the (N + 1) th program section together with the bulk voltage is the memory cell. Applying to the method. The method of claim 9, When the bulk voltage is lower than the detection voltage in the N-th program period, a word line voltage that is increased by a predetermined increase from the word line voltage of the N-th program period is the bulk voltage during the (N + 1) th program period. And to the memory cell. The method of claim 9, And said detecting step is performed during the supply period of the bit line voltage. The method of claim 9, The detecting step is performed during every program period. A first voltage generator circuit for generating a first program voltage to be supplied to the memory cell; A second voltage generator circuit for generating a second program voltage to be supplied to the memory cell; And A control circuit for controlling the first voltage generating circuit in accordance with whether the second program voltage is higher than a detection voltage, When the second program voltage is higher than the detection voltage in the Nth program loop, the control circuit is configured such that the first program voltage of the (N + 1) th program loop is equal to the first program voltage of the Nth program loop. And control the first voltage generator circuit to be maintained. The method of claim 13, When the second program voltage is lower than the detection voltage in the N-th program loop, the control circuit determines that the first program voltage of the (N + 1) -th program loop is less than the first program voltage of the N-th program loop. And controlling the first voltage generator circuit to be increased by an increment of. The method of claim 14, And wherein the first program voltage is a word line voltage and the second program voltage is a bulk voltage. The method of claim 13, The control circuit Control logic for generating a step-up pulse signal in every program loop; A step hold circuit for activating a step hold signal depending on whether the second program voltage is higher than the detected voltage; And And a step control circuit for controlling the first program voltage generation circuit in response to the step-up pulse signal and the step hold signal. The method of claim 16, When the step hold signal is activated in the Nth program period, the step control circuit is configured such that the first program voltage of the (N + 1) th program loop is kept equal to the first program voltage of the Nth program loop. And a nonvolatile memory device controlling the first program voltage generation circuit. The method of claim 16, When the step hold signal is deactivated in the Nth program period, the step control circuit increases the first program voltage of the (N + 1) th program loop by a predetermined voltage than the first program voltage of the Nth program loop. And control the first program voltage generation circuit to enable. The method of claim 16, And the step hold circuit detects the second program voltage according to control of the control logic during a program period of every program loop. The method of claim 16, And the step hold circuit detects the second program voltage according to control of the control logic during the supply period of the second program voltage in every program loop.

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