KR100648249B1 - Erase method of non-volatile memory device capable of reducing erase time - Google Patents

Abstract

An erase method of a nonvolatile memory device disclosed herein includes: simultaneously erasing memory cells of an array; Simultaneously selecting some of the rows in a post-program operation; And post-programming the erased memory cells of the selected rows simultaneously without a verify operation.

Description

ERASE METHOD OF NON-VOLATILE MEMORY DEVICE CAPABLE OF REDUCING ERASE TIME}

1 is a block diagram schematically showing a nonvolatile memory device according to the present invention;

FIG. 2 shows an output of the address generating circuit shown in FIG. 1; FIG.

3A is a block diagram schematically showing a local word line selection circuit shown in FIG. 1 in accordance with a preferred embodiment of the present invention;

3B is a circuit diagram showing the decoder shown in FIG. 3A in accordance with a preferred embodiment of the present invention; And

4 is a flowchart illustrating an erase procedure of a nonvolatile memory device according to the present invention.

Explanation of symbols on the main parts of the drawings

100 nonvolatile memory device 110 memory cell array

120: column selection circuit 130: write driver circuit

140: bit line voltage generation circuit 150: control logic

160: address generating circuit 170: word line voltage generating circuit

180: global word line selection circuit 190: local word line selection circuit

200: word line driving circuit

The present invention relates to a semiconductor memory device, and more particularly to a method of erasing a nonvolatile memory device.

A flash memory device is a kind of EEPROM in which a plurality of memory areas are erased or programmed in one program operation. A typical EEPROM allows only one memory area to be erased or programmable at a time, which allows the flash memory device to operate at a faster and more efficient speed when systems using the flash memory device read and write to other memory areas at the same time. It means that there is. All forms of flash memory and EEPROM are worn out after a certain number of erase operations due to the wear of the insulating film surrounding the charge storage means used to store the data.

Flash memory devices store information on the silicon chip in a manner that does not require a power source to maintain the information stored on the silicon chip. This means that if the power to the chip is interrupted, the information is maintained without consuming power. In addition, flash memory devices provide physical shock resistance and fast read access times. Because of these features, flash memory devices are commonly used as storage devices for devices powered by batteries. There are two types of flash memory devices, NOR flash memory devices and NAND flash memory devices, depending on the type of logic gate used for each storage element.

Flash memory devices store information in an array of transistors called cells, with each cell storing one-bit information. Newer flash memory devices, called multi-level cell devices, can store more than one bit per cell by varying the amount of charge placed on the floating gate of the cell.

In a NOR flash memory device, each cell is similar to a standard MOSFET transistor except that it has two gates. The first gate is a control gate (CG) as in other MOS transistors, but the second gate is an insulated floating gate (FG) surrounded by an insulating film. The floating gate is between the control gate and the substrate (or bulk). Since the floating gate is insulated by the insulating film, electrons placed in the floating gate are trapped and thus store information. When the electrons lie at the floating gate, the electric field from the control gate is changed (partially canceled) by the electrons, which causes the cell's threshold voltage (Vt) to change. Thus, when a cell is read by applying a specific voltage to the control gate, current may or may not flow depending on the threshold voltage of the cell. This is controlled by the amount of charge in the floating gate. The presence or absence of a current is detected and interpreted as 1 or 0, so the stored data is reproduced. In multi-level cell devices that store more than 1-bit per cell, the amount of current flowing rather than the presence or absence of current will be sensed to determine the amount of electrons stored in the floating gate.

The NOR flash cell is programmed (set to a specific data value) by applying a program voltage on the control gate and a high voltage of 5-6V to the drain with the source grounded. According to this bias condition, a large amount of cell current flows from the drain to the source. This programming approach is called hot-electron injection. A large voltage difference is applied between the control gate and the substrate (or bulk) to erase the NOR flash cell, which causes electrons to escape from the floating gate through F-N tunneling. The components of a NOR flash memory device are divided into erase segments, commonly referred to as blocks or sectors. All memory cells in a sector are erased at the same time. NOR programming, however, may be performed in bytes or words.

The erase procedure of the NOR flash memory device is largely composed of a pre-program interval, a main erase inverval, and a post-program interval. The pre-program operation is performed using the same bias condition as the normal program operation in order to prevent the occurrence of over erased memory cells during the next main erase. At this time, all of the memory cells to be erased are pre-programmed. Then, a main erase operation is performed so that all memory cells in the sector have an on-cell state. When the main erase operation starts, all memory cells in the sector are erased simultaneously. Finally, in order to heal excessively erased memory cells in the main erase period, a post-program operation is performed. The post-program operation is performed the same as the pre-program operation except for the bias condition. That is, memory cells connected to each word line (or row) are post / soft-programmed in byte or word units.

As mentioned above, NOR programming is performed in bytes or words. For that reason, a disadvantage of the NOR flash memory device using the erase procedure described above is that the time taken to perform pre-program and post-program operations takes up a significant portion of the total time required for the erase procedure.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of erasing a nonvolatile memory device capable of shortening an erase time.

According to one aspect of the present invention for achieving the above objects, there is provided an erase method of a nonvolatile memory device comprising an array of memory cells arranged in rows and columns. According to the present invention, an erase method includes: simultaneously erasing memory cells of the array; Simultaneously selecting some of the rows in a post-program operation; And post-programming erased memory cells of the simultaneously selected rows.

In this embodiment, the verify operation on the programmed memory cells is not performed during the post-program operation.

In this embodiment, the erased memory cells of the simultaneously selected rows are programmed in predetermined column units.

In this embodiment, the method further includes repeating the selection and program steps until all the memory cells of the array are programmed.

In this embodiment, the method further includes pre-programming the memory cells to be in an off state before the erase step.

In this embodiment, the verify operation on the programmed memory cells is not performed in the pre-program step.

Exemplary embodiments of the invention will be described in detail below on the basis of reference drawings.

1 is a block diagram schematically illustrating a nonvolatile memory device according to the present invention. The nonvolatile memory device according to the present invention is a NOR flash memory device. However, it will be apparent to those skilled in the art that the present invention can be applied to other memory devices (eg, FRAM, NAND type flash memory devices, etc.).

Referring to FIG. 1, a nonvolatile memory device 100 according to the present invention includes a memory cell array 110 that stores N-bit data information (N = 1 or larger integer). The memory cell array 110 is composed of memory cells (denoted by circles in the figure) arranged in a matrix of word lines (or rows) WL0-WLm and bit lines (or columns) BL0-BLn. . The column select circuit 120 selects the bit lines BL0-BLn in a preset unit (for example, byte or word unit). The write driver circuit 130 is controlled by the control logic 150 and drives the selected bit lines to the bit line voltage VBL from the bit line voltage generation circuit 140. The bit line voltage generation circuit 140 is controlled by the control logic 150. The control logic 150 is configured to control the overall operation of the memory device 100 according to each operation mode. In particular, the control logic 150 activates the control signal ACC_POST_PGM in the post-program period of the erase mode of operation. The control signal ACC_POST_PGM is activated during the post-program period.

The address generation circuit 160 generates row address signals RAi and RAj in response to the control of the control logic 150 during the pre-program / post-program operation period. In particular, the address generation circuit 160 is configured such that the generation of the row address RAj is changed depending on whether the control signal ACC_POST_PGM is activated. For example, suppose the row address RAj is a 3-bit address. When the control signal ACC_POST_PGM is deactivated, the 3-bit address will be incremented / decremented sequentially. When the control signal ACC_POST_PGM is activated, only some of the 3-bit addresses (e.g., upper 2-bits) are sequentially increased / decreased while the rest (e.g., lower 1-bits) are not changed. . This will be explained in detail later. The word line voltage generation circuit 170 is controlled by the control logic 150 and generates a word line voltage V _WL to be supplied to the word line.

1, a nonvolatile memory device 100 according to the present invention may include a global word line selector circuit 180, a local word line selector circuit ( 190, and a word line driver circuit 200.

The global word line select circuit 180 selects one of the global word line select signals GWLx in response to the row address RAi from the address generation circuit 160. The local word line select circuit 190 operates in response to the control signal ACC_POST_PGM from the control logic 150, and local word line select signals PWLy in accordance with the row address RAj from the address generation circuit 160. ) (Eg, one or more signals). For example, when the control signal ACC_POST_PGM is deactivated, the local word line select circuit 190 activates one of the local word line select signals PWLy in response to the row address RAj. When the control signal ACC_POST_PGM is activated, the local word line select circuit 190 simultaneously activates a pair of local word line select signals of the local word line select signals PWLy in response to the row address RAj. The nonvolatile memory device 100 according to the present invention has a well-known hierarchical word line structure in which one global word line corresponds to a plurality of word lines. The word line driver circuit 200 selects some of the word lines in response to the global word line select signals and the local word line select signals, and drives the selected word line (s) to the word line voltage V _WL . do. For example, when one global word line select signal is activated and one local word line select signal is activated (or when the control signal ACC_POST_PGM is deactivated), the word line driving circuit 200 is one word. Drive the line to the word line voltage (VWL). When one global word line select signal is activated and two local word line select signals are activated (or when the control signal ACC_POST_PGM is activated), the word line driving circuit 200 is capable of simultaneously wording two word lines. Drive to line voltage VWL.

In conclusion, the nonvolatile memory device 100 according to the present invention selects and drives two word lines at the same time when the control signal ACC_POST_PGM is activated and selects one word line when the control signal ACC_POST_PGM is deactivated. Configured to be driven. As mentioned above, the control signal ACC_POST_PGM is activated in the post-program period of the erase operation mode, and this post-program operation is referred to as "accelerated post-program operation" hereinafter. Thus, since two word lines are selected at the same time in the post-program period, the time taken to perform the post-program operation is reduced by approximately half.

FIG. 2 is a diagram illustrating an output of the address generation circuit shown in FIG. 1. Referring to FIG. 2, the address generation circuit 160 is implemented such that address signals RA0-RA2 are sequentially increased / decreased during normal operation or when the control signal ACC_POST_PGM is deactivated. The address generating circuit 160 may sequentially increase / decrease the two upper address signals RA1 and RA2 of the address signals RA0-RA2 during the acceleration post-program operation or when the control signal ACC_POST_PGM is activated. Is implemented. At this time, the address signal RA0 is don't care.

3A is a block diagram illustrating a local word line selection circuit and a word line driving circuit shown in FIG. 1 according to a preferred embodiment of the present invention. The local word line selection circuit and the word line driver circuit are partially shown in FIG. 3A.

Referring to FIG. 3A, the local word line selection circuit 190 includes a plurality of, for example, eight decoders 191-198, with one global word line in each of the decoders 191-198. The row address signals RA0-RA2 and the control signal ACC_POST_PGM for selecting word lines (in this embodiment, eight word lines) corresponding to are applied. Each of the decoders 191-194 decodes input address signals RA0-RA2 to generate local word line select signals PWL0-PWL7, respectively. Decoder 198 according to an exemplary embodiment consists of a NAND gate G1 and NOR gates G2 and G3, as shown in FIG. 3B. When the control signal ACC_POST_PGM is deactivated, one local word line select signal is activated according to the input address signals RA0-RA2. When the control signal ACC_POST_PGM is activated, as mentioned above, the lower address signal R0 is ignored, so that each decoder generates a corresponding local word line signal in response to the upper address signals RA1, RA2. Activate it. That is, when the control signal ACC_POST_PGM is activated, two local word line signals are simultaneously activated. For example, when the address signals RA1RA2 are "00", the decoders 191, 192 simultaneously activate the corresponding local word line select signals PWL0, PWL1. When the address signals RA1RA2 are "10", the decoders 193 and 194 simultaneously activate the corresponding local word line select signals PWL2 and PWL3. That is, in the acceleration post-program operation or when the control signal ACC_POST_PGM is activated, two local word line select signals are simultaneously activated.

3A, the word line driving circuit 200 corresponds to one global word line GWL0, and the global word line selection signal GWL0 and the local word line selection signals PWL0-PWL7 are described. Drive some of the word lines to the word line voltage V _WL . For example, when one local word line select signal is activated, only one word line is activated according to the activation of the global word line select signal. Alternatively, when two local word line select signals are activated, two word lines are activated according to the activation of the global word line select signal.

4 is a flowchart illustrating an erase procedure of a nonvolatile memory device according to the present invention. Hereinafter, an erase procedure of the nonvolatile memory device according to the present invention will be described in detail with reference to the accompanying drawings. Prior to the description, the erase procedure of the nonvolatile memory device according to the present invention is largely composed of a pre-program interval, a main erase interval, and a post-program interval.

In the pre-program period, all memory cells are pre-programmed under the same bias condition as in a normal program operation in order to prevent generation of memory cells that are excessively erased during the next main erase (S100). According to the pre-program operation of the present invention, in a state in which one row is selected, memory cells of the selected row are pre-programmed in predetermined units (for example, byte or word units). If all the memory cells of the selected row are pre-programmed, the next row is selected. By repeating this process, all of the memory cells are pre-programmed. The verification operation is not performed in the pre-program section. That is, all memory cells are pre-programmed to have an off state without a program verify operation. Thereafter, all of the memory cells are simultaneously erased in a well-known manner so as to have an on state (S110). After the erase operation is completed, the acceleration post-program operation according to the present invention is performed (S160). Accelerated post-program operations in accordance with the present invention will be described in detail below.

The control logic 150 activates the control signal ACC_POST_PGM after the erase operation is terminated (S120). The address generating circuit 160 generates the row addresses RAi and RAj under the control of the control logic 150. Here, when the control signal ACC_POST_PGM is activated, as described above, only some of RA1 and RA2 of the address signals RA0-RA2 are variable. The global word line select circuit 180 activates one of the global word line select signals GWLx (eg, GWL0) in response to the row address RAi. At the same time, the local word line select circuit 190 simultaneously activates a pair of select signals of the local word line select signals PWL0-PWL7 in response to the control signal ACC_POST_PGM and the row addresses RA1 and RA2. For example, when the address signals RA1RA2 are "00", the decoders 191, 192 simultaneously activate the corresponding local word line select signals PWL0, PWL1. This means that as described above, the two word lines WL0 and WL1 are simultaneously driven to the word line voltage VWL. That is, in an accelerated post-program operation, two word lines are activated at the same time. In this state, the column select circuit 120 sequentially selects columns or bit lines BL0-BLn in predetermined units, and the selected columns are driven to the bit line voltage VBL by the write driver circuit 130. . That is, memory cells connected to the selected word lines WL0 and WL1 are post-programmed (S140).

In a next step S150, it is determined whether all the cells of the memory cell array have been post-programmed. If all cells of the memory cell array have not been post-programmed, the procedure proceeds to step S130. Thereafter, the above-described steps S130-S150 are repeated until all global word lines are selected (or until all word lines are selected). If all cells of the memory cell array have been post-programmed, the erase procedure is terminated. According to the accelerated post-program operation of the present invention, like the pre-program operation, all memory cells are post-programmed without the program verify operation.

In the above, the configuration and operation of the circuit according to the present invention has been shown in accordance with the above description and drawings, but this is only an example, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Of course.

As described above, the post-program time can be shortened by performing a post-program operation with two word lines simultaneously selected. As a result, it is possible to reduce the erase time.

Claims (6)

A method of erasing a nonvolatile memory device comprising an array of memory cells arranged in rows and columns: Simultaneously erasing memory cells of the array; Simultaneously selecting at least two of the rows in a post-program operation; And Post-programming erased memory cells of the simultaneously selected rows. The method of claim 1, And wherein the verify operation is not performed on the programmed memory cells during the post-program operation. The method of claim 1, And erased memory cells of the simultaneously selected rows are programmed in units of a predetermined column. The method of claim 1, And repeating the selection and program steps until all the memory cells in the array are programmed. The method of claim 1, And pre-programming the memory cells to have an off state prior to the erasing step. The method of claim 5, And the verify operation is not performed on the programmed memory cells in the pre-program step.

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