KR100784864B1 - Nand flash memory device performing pre-program operation after erease operation and erase method thereof - Google Patents

Abstract

A NAND flash memory device performing post-program operation after erase operation and an erase method thereof are provided to prevent over-erase by performing the post-program operation after the erase operation. A NAND flash memory includes a plurality of word lines, a plurality of memory cells and an erase controller(140). The plurality of memory cells is connected to each word line. The erase controller post-programs the plurality of memory cells, after erasing the plurality of memory cells. The erase controller post-programs only a memory cell connected to one or more than one word line among the plurality of word lines selectively.

Description

NAND flash memory performing a post program operation after an erase operation and a method of erasing thereof NAND FLASH MEMORY DEVICE PERFORMING PRE-PROGRAM OPERATING AFTER EREASE

1 is a circuit diagram illustrating a cell string structure of a general NAND flash memory.

2 shows a process in which 2-bit data is programmed in one memory cell.

FIG. 3 is a timing diagram illustrating a bias condition during a program operation of the NAND flash memory of FIG. 1.

4 illustrates a case where all memory cells connected to the program inhibit bit line IHB_BL are in an erase state 11.

FIG. 5 shows a case in which all memory cells connected to the program inhibit bit line IHB_BL are in a program state (00).

6 shows a NAND flash memory using a local boosting scheme.

FIG. 7 illustrates threshold voltage distributions of the memory cell illustrated in FIG. 6.

8 is a block diagram illustrating a NAND flash memory according to the present invention.

9 illustrates a first bias condition during a post program operation of a NAND flash memory according to the present invention.

10 illustrates a second bias condition during a post program operation of the NAND flash memory according to the present invention.

11 illustrates a third bias condition during post program operation of the NAND flash memory according to the present invention.

12 illustrates a fourth bias condition during post program operation of a NAND flash memory according to the present invention.

13 is a flowchart illustrating a first embodiment of an erase operation of a NAND flash memory according to the present invention.

14 is a flowchart illustrating a second embodiment of an erase operation of a NAND flash memory according to the present invention.

15 is a flowchart illustrating a third embodiment of an erase operation of a NAND flash memory according to the present invention.

* Description of symbols on the main parts of the drawings *

100; NAND flash memory 110; Memory cell array

120; Decoder 130; Page buffer

140; Erase controller

The present invention relates to a semiconductor memory device, and more particularly, to a NAND flash memory that performs a post program operation before an erase operation.

A semiconductor memory device is a memory device that stores data and can be read out when needed. The semiconductor memory device may be largely divided into a random access memory (RAM) and a read only memory (ROM). RAM is a volatile memory device in which stored data is lost when power is lost. ROM is a nonvolatile memory device in which stored data is not destroyed even when a power supply is cut off. RAM includes Dynamic RAM (DRAM), Static RAM (SRAM), and the like. The ROM includes a programmable ROM (PROM), an erasable PROM (EPROM), an electrically EPROM (EPROM), a flash memory, and the like. Flash memory is divided into NOR type and NAND type.

1 is a circuit diagram illustrating a cell string structure of a general NAND flash memory. Referring to FIG. 1, one cell string 10 includes a ground selection transistor (GST), a plurality of memory cells MC0 to MC31, and a string selection transistor (SST). Are connected in series. The ground select transistor GST is connected to a common source line CSL, and the string select transistor SST is connected to a bit line BL.

The word lines WL0 to WL31 are connected to gates of the memory cells MC0 to MC31, the string selection line SSL is connected to the gate of the string select transistor SST, and the ground select transistor GST is connected to the gate of the string select transistor SST. A ground selection line (GSL) is connected to the gate of the gate.

The memory cells MC0 to MC31 store data 1 or 0 according to the distribution of threshold voltages. Here, the memory cell storing the data 0 is called a program cell, and the memory cell storing the data 1 is called an erase cell. The memory cells are erased and then programmed. Referring to FIG. 1, 0V is applied to a bit line PGM_BL to which a program cell (for example, MC28) is connected, and a power supply voltage is applied to a bit line IHB_BL to which a program inhibit cell MC28 'is connected. Vcc) is applied.

In the program operation, a program voltage Vpgm is applied to the select word lines WL28 and a pass voltage Vpass is applied to the unselected word lines WL0 to WL27 and WL29 to WL31. In this case, the program cell MC28 'has a threshold voltage corresponding to the data' 0 ', and the program inhibiting cell MC28 has an erase state, that is, a threshold voltage corresponding to the data' 1 '.

Meanwhile, multi bit data may be stored in one memory cell. Such memory cells are commonly referred to as multi level cells (MLCs). FIG. 2 shows a process in which a least significant bit (LSB) and a most significant bit (MSB), that is, two bit data, are programmed in one memory cell.

Referring to FIG. 2, a memory cell is programmed to have one of four states 11, 10, 00, and 01 according to a threshold voltage distribution. The memory cell having the 11 state is maintained in the 11 state or programmed to the 10 state according to the low bit (LSB) data (Program1). The memory cell having the 10 state is maintained in the 10 state or programmed to the 00 state according to the upper bit MSB (Program2). Meanwhile, the memory cell having the 11 state is programmed to maintain the 11 state or have the 01 state according to the upper bit MSB (program3).

FIG. 3 is a timing diagram illustrating a bias condition during a program operation of the NAND flash memory of FIG. 1. When the program operation starts, the program bit line PGM_BL is set to 0V and the program prohibition bit line IHB_BL is set up to the power supply voltage Vcc, respectively.

At t1, a power supply voltage Vcc is applied to the string select line SSL. At this time, the channel voltage of the program inhibiting cell MC28 is (Vcc-Vth). Here, Vth is a threshold voltage of the string select transistor SST. The string select transistor SST is in a cut-off state.

At t2, the voltage applied to the string select line SSL is lowered to a voltage Vsel that is higher than the threshold voltage Vth and lower than the power supply voltage Vcc. This is to make the string select transistor SST to a stronger cut-off state.

At t3, a high voltage corresponding to about 8V is applied to the select word lines WL28 and the unselected word lines WL0 to WL27 and WL29 to WL31. The high voltage applied at this time is called a pass voltage Vpass. When the pass voltage Vpass is applied to the gate of the program inhibiting cell MC28 through the selection word line WL28, a capacitance coupling phenomenon occurs between the gate and the channel of the program inhibiting cell MC28. Due to the capacitance coupling phenomenon, the channel voltage rises to the boost voltage Vboost. This phenomenon is called self-boosting. Here, the boost voltage Vboost prevents F-N tunneling from occurring in the program inhibiting cell MC28.

At t4, when the program voltage Vpgm is applied to the select word line WL28, the program cell MC28 'is programmed by the F-N tunneling phenomenon. That is, electrons in the channel are injected into the floating gate of the program cell MC28 '. Since the F-N tunneling does not occur in the program inhibiting cell MC28, electrons of the channel are not injected into the floating gate.

Referring back to FIG. 1, a NAND flash memory typically programs sequentially from word lines WL0 to WL31. This method is commonly referred to as the 'min-max method'. In the NAND flash memory performing a program operation by the min-max method, a charge sharing phenomenon may occur between the selected memory cell MC28 and its lower memory cells MC0 to MC27. That is, the channel voltage of the program inhibiting cell MC28 is lowered, so that the program inhibiting cell MC28 can be programmed by F-N tunneling. This is described in detail with reference to FIGS. 4 and 5.

4 illustrates a case where all memory cells connected to the program inhibit bit line IHB_BL are in an erase state 11. Referring to FIG. 4, 0 V is applied to a bulk of a program cell B cell through a bit line PGM_BL, and a program voltage Vpgm is applied to a gate through a selection word line WL28. do. The program cell (B cell) is programmed by F-N tunneling under these bias conditions.

Meanwhile, the bulk of the program inhibiting cell A cell connected to the same word line WL28 rises to the boost voltage Vboost by self boosting. As a result, F-N tunneling does not occur in the program inhibited cell A cell. That is, the program inhibit cell A cell is not programmed. As shown in FIG. 4, when all the lower cells of the program inhibited cell A cell are in an erased state, the boosting efficiency of the program inhibited cell A cell is increased. Therefore, the bulk of the program inhibit cell A generates a voltage high enough that F-N tunneling does not occur.

FIG. 5 shows a case in which all memory cells connected to the program inhibit bit line IHB_BL are in a program state (00). Referring to FIG. 5, if the lower memory cell of the program inhibit cell C cell is in a program state, that is, in a 00 state, the boosting efficiency of the program inhibit cell C cell may be lowered.

Referring to FIG. 5, all of the memory cells connected to the lower word lines WL0 to WL27 of the select word line WL28 are programmed to a 00 state. When the pass voltage Vpass is applied to the lower memory cell, a low boosting voltage is generated in the bulk of the lower memory cell. As a result, the program boosting voltage of the program inhibiting cell C cell connected to the select word line WL28 is lowered due to the charge sharing effect with the lower memory cells.

As a result, the bulk voltage of the program inhibit cell C cell is lowered, and F-N tunneling occurs in the program inhibit cell C cell. This phenomenon is called program disturbance. If it is assumed that the NAND flash memory is programmed by the min-max method, the closer the selected word line is to WL31, the more severe the program disturbance due to charge sharing becomes.

6 shows a NAND flash memory using a local boosting scheme. Referring to FIG. 6, a pass voltage Vpass or a local voltage Vlocal is applied to the lower word lines WL0 to WL27 of the select word line WL28.

The local voltage Vlocal is applied to the word line adjacent to the select word line WL28 (two word lines in FIG. 6). The local voltage (Vlocal, for example 2V) is lower than the pass voltage (Vpass, for example 8V). The reason why the local voltage Vlocal is applied to the word lines WL26 and WL27 adjacent to the selected word line WL28 is to prevent the program disturbance phenomenon by blocking the charge sharing path.

That is, the local boosting scheme is for blocking charge sharing between the program inhibiting cell (E cell) and the lower memory cell. The memory cell must be completely off to block charge sharing. However, when the memory cell to which the local voltage Vlocal is applied is an erase cell, the memory cell may not be completely turned off. This is described in detail with reference to FIG. 7.

FIG. 7 illustrates threshold voltage distributions of the memory cell illustrated in FIG. 6. Fig. 7 (a) shows the state before erasing, and Fig. 7 (b) shows the state after erasing. In Fig. 7A, the E cell is the program inhibiting cell shown in Fig. 6. As shown in Fig. 7A, the E cell is already in the erased state before the erase operation.

When the E cell already erased is erased again, the threshold voltage of the E cell becomes lower. This means that it can be switched from the off cell to the on cell according to the voltage applied to the gate of the E cell. When the E cell is turned on due to over erase, the channel voltage of the raised E cell due to the program voltage Vpgm may decrease due to charge sharing. As a result, the E cell is a program inhibited cell, but can be programmed.

The NAND flash memory does not detect the presence of an erase cell during an erase operation. That is, the erase operation is collectively performed on all the cells in the memory block. When the cell already in the erased state is erased again, the threshold voltage of the memory cell becomes lower. As a result, the memory cell to which the local voltage is applied may change from the off state to the on cell. That is, the conventional NAND flash memory reduces the effect of the local boosting scheme due to the over-erasing of memory cells.

The present invention has been proposed to solve the above problems, and an object of the present invention is to provide a NAND flash memory that prevents over erase by performing a post program operation after an erase operation.

Another object of the present invention is to provide a NAND flash NAND flash memory that prevents charge sharing during a post program operation performed after an erase operation.

A NAND flash memory device according to the present invention includes a plurality of word lines; A plurality of memory cells connected to each word line; And an erase controller for erasing the plurality of memory cells and then post programming the plurality of memory cells, wherein the erase controller selectively selects only memory cells connected to one or more word lines of the plurality of word lines. Post program.

In example embodiments, the erase controller post-programs only memory cells connected to an upper word line among the plurality of word lines. The upper word line is provided with the same level of post program voltage. However, other levels of post program voltage may be provided to the upper word line. The erase controller provides a post program voltage to the upper word line at one time. However, the erase controller may provide the upper word line in steps of increasing the post program voltage.

In another embodiment, the erase controller provides a pass voltage to an unselected word line for which no post program voltage is provided. The pass voltages provided to the unselected word lines are at the same level. However, the pass voltage provided to the unselected word lines may be at different levels.

In another embodiment, after the post program operation, the program verify operation is performed individually for each word line. However, after the post program operation, the program verify operation may be simultaneously performed for all word lines.

The present invention relates to a method of erasing a NAND flash memory. The NAND flash memory includes a plurality of word lines; And a plurality of memory cells connected to each word line. The erase method of the NAND flash memory may include erasing the plurality of memory cells; And post-programming the plurality of memory cells, wherein the post-programming step selectively post-programs only memory cells connected to one or more word lines of the plurality of word lines.

In an embodiment, only a memory cell connected to an upper word line is post-programmed among the plurality of word lines. The upper word line is provided with the same level of post program voltage. However, other levels of post program voltage may be provided to the upper word line. Post program voltage is provided to the upper word line at one time. However, the post program voltage may be provided to the upper word line in increments.

In another embodiment, a pass voltage is provided to an unselected word line where no post program voltage is provided. The pass voltages provided to the unselected word lines are at the same level. However, the pass voltage provided to the unselected word lines may be at different levels.

In another embodiment, after the post program operation, the program verify operation is performed individually for each word line. However, after the post program operation, the program verify operation may be simultaneously performed for all word lines.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

8 is a block diagram illustrating a NAND flash memory according to the present invention. Referring to FIG. 8, the NAND flash memory 100 includes a memory cell array 110, a decoder 120, a page buffer 130, and an erase controller 140. The NAND flash memory 100 according to the present invention executes a post program after an erase operation, thereby preventing over erase of memory cells.

The memory cell array 110 is composed of a plurality of memory blocks (not shown). Each memory block consists of a plurality of pages (for example, 32 pages, 64 pages), and each page includes a plurality of memory cells (for example, 512 bytes and 2K bytes) sharing one word line WL. It is composed of In the case of NAND flash memory, erase operations are performed in units of memory blocks, and read and write operations are performed in units of pages.

The decoder 120 is connected to the memory cell array 110 through a string select line SSL, a word line WL, and a ground select line GSL. Decoder 120 is controlled by erase controller 140. The decoder 120 receives an address ADDR from a memory controller (not shown) during a program operation, selects one word line (eg, WL28), and selects a program voltage Vpgm with the selected word line. to provide.

The page buffer 130 is connected to the memory cell array 110 through the bit line BL. The page buffer 130 stores data loaded from a buffer memory (not shown). One page of data is loaded into the page buffer 130, and the loaded data is simultaneously programmed into the page selected during the program operation.

The erase controller 140 receives a control signal CTRL from a memory controller (not shown) and controls an internal operation of the NAND flash memory 100. The erase controller 140 generates a post program voltage Vpgm, a pass voltage Vpass, a program verification voltage Vvfy, and an erase voltage Verase during an erase operation.

The NAND flash memory 100 according to the present invention prevents over erase of memory cells by performing a post program operation after an erase operation. In the NAND flash memory 100 which performs a program operation according to the min-max method, the closer the string select line SSL is, the more severe the program disturbance phenomenon is. If memory cells connected to all word lines are post-programmed at the same time, it becomes difficult to control the threshold voltages of the memory cells connected to each word line. Accordingly, the NAND flash memory 100 according to the present invention selectively performs a post program only on memory cells connected to upper word lines (upper WLs).

Here, the upper word lines Upper WLs mean some of the word lines on the string select line SSL side of all the word lines. On the contrary, the lower word lines WLs mean some word lines on the ground select line GSL side. For example, suppose the word lines are WL0 to WL31. Upper word lines are WL25 to WL30, and lower word lines are WL0 to WL24.

Even though the memory cells connected to the lower word line are all programmed to be in a 00 state, the selected memory cell (see FIG. 5, C cell) has a relatively low charge sharing effect. Therefore, the program inhibit cell (C cell) is not programmed due to the program disturbance effect. Therefore, the NAND flash memory 100 according to the present invention post-programs only memory cells connected to the upper word lines (upper WLs) during a post program operation performed after an erase operation.

9 illustrates a first bias condition during a post program operation of a NAND flash memory according to the present invention. Here, the post program operation is performed after the erase operation. In the following, it is assumed that the upper word line is WL25 to WL30.

9, a program voltage Vpgm is provided to the upper word lines WL25 to WL30 and a pass voltage Vpass is provided to the remaining word lines WL0 to WL24 and WL31 during a post program operation. Here, the program voltage Vpgm provided to the upper word lines WL25 to WL30 has the same voltage level. The pass voltages Vpass provided to the remaining word lines WL0 to WL24 and WL31 have the same voltage level.

In FIG. 9, the reason why the program voltage is provided only to the upper word lines WL25 to WL30 is that the program inhibiting cell connected to the upper word lines WL25 to WL30 is severely affected by the program disturbance due to charge sharing. to be. Program inhibit cells connected to the remaining word lines WL0 to WL24 and WL31 are relatively less affected by program disturbance.

10 illustrates a second bias condition during a post program operation of the NAND flash memory according to the present invention. Referring to FIG. 10, the program voltages Vpgm provided to the upper word lines WL25 to WL30 have different voltage levels Vpgm1 to Vpgmi. The pass voltages Vpass provided to the remaining word lines WL0 to WL24 and WL31 have the same voltage level.

The NAND flash memory illustrated in FIG. 10 provides a program voltage Vpgm to the upper word lines WL25 to WL30 during a post program operation after an erase operation. The program voltage Vpgm has different voltage levels. According to the NAND flash memory shown in FIG. 10, the influence of program disturbance can be controlled to match each word line.

11 illustrates a third bias condition during post program operation of the NAND flash memory according to the present invention. Referring to FIG. 11, the program voltages Vpgm provided to the upper word lines WL25 to WL30 have the same voltage level. The pass voltage Vpass provided to the remaining word lines WL0 to WL24 and WL31 has different voltage levels Vpass1 to Vpassj.

12 illustrates a fourth bias condition during post program operation of a NAND flash memory according to the present invention. Referring to FIG. 12, the program voltage Vpgm and the pass voltage Vpass are alternately provided to the upper word lines WL25 to WL30. The pass voltages Vpass provided to the remaining word lines WL0 to WL24 and WL31 have the same voltage level. Here, the pass voltage Vpass provided to the remaining word lines WL0 to WL24 and WL31 may have different voltage levels.

13 is a flowchart illustrating a first embodiment of an erase operation of a NAND flash memory according to the present invention. According to the erase method of the NAND flash memory according to the first embodiment of the present invention, the NAND flash memory is connected to the upper word lines (upper WLs) after performing erase and erase verification operations on all memory cells (S110). Post-program the memory cell (S120).

14 is a flowchart illustrating a second embodiment of an erase operation of a NAND flash memory according to the present invention. According to the erase method of the NAND flash memory according to the second embodiment of the present invention, first, erase and erase verification operations are performed on all memory cells (S210). Next, the NAND flash memory post-programs the upper word lines upper WLs (S220). Finally, the NAND flash memory independently performs a program verify operation on each upper word line (S230).

15 is a flowchart illustrating a third embodiment of an erase operation of a NAND flash memory according to the present invention. According to the erase method of the NAND flash memory according to the third embodiment of the present invention, first, erase and erase verification operations are performed on all memory cells (S310). Next, the NAND flash memory post-programs the upper word lines upper WLs (S320). Finally, the NAND flash memory simultaneously performs a program verify operation on memory cells connected to all upper word lines (S330).

The NAND flash memory according to the present invention performs a post program operation after an erase operation in order to prevent over erasure. The NAND flash memory according to the present invention performs a post program operation only on memory cells connected to some word lines in consideration of program disturbance effects.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present invention as well as the following claims.

As described above, the NAND flash memory device according to the present invention selectively performs a post program operation on memory cells connected to some word lines after an erase operation. According to the present invention, a phenomenon in which a program inhibiting cell is programmed can be prevented because memory cells that are already erased are erased in duplicate.

Claims (22)

A plurality of word lines; A plurality of memory cells connected to each word line; And And an erase controller to erase the plurality of memory cells and then post program the plurality of memory cells. And the erase controller selectively post-programs only memory cells connected to one or more word lines of the plurality of word lines. The method of claim 1, And the erase controller post-programs only memory cells connected to an upper word line among the plurality of word lines. The method of claim 2, NAND flash memory is provided with the same level of the post program voltage to the upper word line. The method of claim 2, And a different level of post program voltage on the upper word line. The method of claim 2, And the erase controller provides a post program voltage to the upper word line at one time. The method of claim 2, And the erase controller provides the upper word line to the post word voltage in steps. The method of claim 1, And the erase controller provides a pass voltage to an unselected word line to which no post program voltage is provided. The method of claim 7, wherein NAND flash memory, characterized in that the pass voltage provided to the unselected word line is the same level. The method of claim 7, wherein NAND flash memory, characterized in that the pass voltage provided to the unselected word line is a different level. The method of claim 1, NAND flash memory that performs a program verify operation individually for each word line after a post program operation. The method of claim 1, A NAND flash memory that performs a program verify operation at the same time after a post program operation. In the erase method of a NAND flash memory, The NAND flash memory includes a plurality of word lines; And A plurality of memory cells connected to each word line, The erase method of the NAND flash memory Erasing the plurality of memory cells; And Post-programming the plurality of memory cells; And in the post program step, selectively post-program only memory cells connected to one or more word lines of the plurality of word lines. The method of claim 12, An erase method of post programming only memory cells connected to an upper word line among the plurality of word lines. The method of claim 13, And the upper word line is provided with the same level of post program voltage. The method of claim 13, The upper word line is provided with a different level of post program voltage. The method of claim 13, An erase method providing a post program voltage to said upper word line at a time. The method of claim 13, And erasing a post program voltage to the upper word line in increments. The method of claim 12, An erase method for providing a pass voltage to an unselected word line where no post program voltage is provided. The method of claim 18, And pass voltages provided to the unselected word lines have the same level. The method of claim 18, And pass voltages provided to the unselected word lines have different levels. The method of claim 12, An erase method for performing a program verify operation separately for each word line after a post program operation. The method of claim 12, An erase method for simultaneously performing a program verify operation after a post program operation.

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