JP2007095233A - Nonvolatile memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make undesired change, in read logic value for stored information, held by a nonvolatile memory cell hardly occur, even when a parallel number for the memory bank, in which operation is designated by a command, is not coincide. <P>SOLUTION: The device has a plurality of memory banks (MBNK0-MBNKn), capable of memory operation independently for each of them, and a control part (2) for controlling the memory operation for the above plurality of memory banks. The memory bank has a large number of the nonvolatile memory cells electrically rewritable. The control part responds the command externally given and can perform the parallel operation for the above plurality of memory banks. When there is at least one memory bank for responding the above command and performing read for the memory information, the control part makes the remaining memory banks perform the dummy read for the memory information in parallel to its read, and invalidates the read result by the above dummy read. This makes overall power consumption state in the all memory banks approximately constant regardless of the state of instruction of the read operation by the command. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an electrically rewritable nonvolatile memory having a plurality of memory banks that can operate independently, and relates to a technique effective when applied to, for example, a flash memory having multiple banks.

  Patent Document 1 relating to a flash memory having a plurality of independently operable memory banks describes that one or more memory banks are operated by a command. For example, regarding the data read operation, there are a read operation specifying one memory bank and a parallel read operation specifying a plurality of memory banks. As for writing, an operation is described in which write data is taken into a data buffer and an operation of writing the data to a nonvolatile memory is parallelized for a plurality of memory banks. As for erasing, an operation mode is shown in which one memory bank is selected or a plurality of memory banks are parallelized.

Japanese Patent Laid-Open No. 2003-223792

  In the multi-bank flash memory, the present inventor has found that there is a change in the read logical value of the stored information held in the nonvolatile memory cell in accordance with the parallel number of operating memory banks. The cause is considered to be a change in the internal voltage due to a load change according to the number of parallel memory banks, the combination of parallel operations, and the like. However, it has been found by the present inventor that it is difficult to precisely grasp which voltage is changed by how many parallel operations of the memory banks. Under such circumstances, it is not possible to expect an effect if halfway measures are taken for some circuits. Therefore, the present inventor has recognized that it is necessary to take comprehensive measures without specifying individual causes.

  An object of the present invention is to provide a non-volatile memory that hardly causes an undesired change in a read logical value of stored information held in a non-volatile memory cell even if the number of parallel memory banks whose operation is specified by a command is different. There is.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  The non-volatile memory according to the present invention includes a plurality of memory banks (MBNK0 to MBNKn) each capable of independently operating a memory, and a control unit (2) that controls memory operations of the plurality of memory banks. The memory bank has a large number of electrically rewritable nonvolatile memory cells (MC). The controller can operate the plurality of memory banks in parallel in response to a command given from the outside. When there is at least one memory bank that reads stored information in response to the command, the control unit causes the remaining memory banks to perform dummy reading of the stored information in parallel with the reading.

  According to the above-described means, the dummy reading is performed in the remaining memory banks regardless of the number of memory banks in which the reading operation is instructed by the command. The overall power consumption state in the bank is constant. As a result, even if the number of parallel memory banks whose operation is specified by the command is different, an undesired change in the read logical value of the stored information held in the nonvolatile memory cell is unlikely to occur.

  As one specific form of the present invention, the control unit invalidates the read result of the dummy read by blocking a transmission path of the read result of the dummy read.

  As another specific form of the present invention, the memory bank includes a nonvolatile memory unit (11, 12, 16) having the nonvolatile memory cells, and a data buffer buffer connected to the nonvolatile memory unit. Part (15). The data buffer unit temporarily holds data read from the nonvolatile memory unit and can output the data to the outside, and temporarily holds write data supplied from the outside and can supply the data to the memory unit. . At this time, the control unit does not transfer the data read from the nonvolatile memory unit by the dummy reading to the data buffer unit. As a result, the reading result by the dummy reading is invalidated. The reason why the data that has been subjected to dummy reading is not transferred to the data buffer unit is that the data buffer unit has already been read and there may be data that has not been output to the outside. Therefore, it is necessary to hold the data, and power consumption is increased by storing the data in the data buffer.

  Further, at this time, the nonvolatile memory unit is connected to a plurality of bit lines connected to the data terminals of the nonvolatile memory cells, a sense latch connected to each of the bit lines, and a selection terminal of the nonvolatile memory cells. A plurality of word lines. The control unit causes the sense latch to latch data read from the nonvolatile memory cell to the bit line by the dummy read. The overall power consumption state in all memory banks including the operation of the sense latch can be made constant. In the operation of latching the data read from the bit line in the sense latch, it is necessary to determine the potential of the bit line or the amount of current flowing through the bit line, and the determination operation is an analog operation. During the period, the fluctuation of the voltage level and the amount of current when charging the bit line to a predetermined voltage level or passing a current through the bit line is suppressed, and the power consumption state is kept constant in the judgment by the sense latch Is necessary for proper reading. On the other hand, it is necessary to reduce power consumption in a period other than the determination operation period.

  As yet another specific form of the present invention, the control unit is associated with an operation in response to a read command for reading storage information of a nonvolatile memory cell from a nonvolatile memory unit to a data buffer unit. Perform a dummy read. Further, when the control unit responds to a write command for setting a threshold voltage of a nonvolatile memory cell in a corresponding nonvolatile memory unit in accordance with the write data held by the data buffer unit, the control unit accompanies a write verify operation, Read is executed. In addition, when responding to an erase command that initializes the threshold voltage of the nonvolatile memory cell, the control unit causes the dummy read to be executed in association with the erase verify operation.

  As another specific form of the present invention, a power supply circuit for supplying operation power to the plurality of memory banks is provided. The control unit controls the supply state of operation power by the power supply circuit according to the number of memory banks whose operation is designated by a command. The controller increases the power supply voltage of the operation power supply as the number of memory banks designated for operation increases, or increases the current supply capability of the operation power supply as the number of memory banks designated for operation increases. Even when the number of parallel memory banks whose operation is specified by a command is different in the operation other than the read operation, the change in the operating voltage can be reduced.

  As yet another specific form of the present invention, a plurality of power supply circuits for individually supplying operation power to the plurality of memory banks in a one-to-one correspondence are provided. The control unit supplies operation power from a corresponding power supply circuit to a memory bank whose operation is designated by a command, and supplies operation power from the power supply circuit to the memory bank when performing the dummy operation. Even when the number of parallel memory banks whose operation is specified by a command is different in the operation other than the read operation, the change in the operating voltage can be reduced.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to prevent an undesired change in the read logical value of the storage information held in the nonvolatile memory cell even if the number of parallel memory banks whose operation is specified by the command is different.

<Overall configuration of flash memory>
FIG. 1 generally shows an example of a flash memory 1 according to the present invention. The flash memory 1 includes a plurality of, for example, n + 1 memory banks MBNK0 to MBNKn that can operate independently on a single semiconductor substrate (semiconductor chip) such as single crystal silicon, and memories for the memory banks MBNK0 to MBNKn. It has a control unit (CNT) 2 that controls the operation and an interface control unit (IF) 3 with the outside. The control unit 2 includes an address buffer (ABUF) 4, an address counter (ACNT) 5, an internal power supply circuit (VGN) 6, a command decoder (CDEC) 7, a microcomputer (MPU) 8, a data input / output control logic circuit (DIO) ) 9. In the following description, it is assumed that n = 3 for convenience and that four memory banks are provided. Although not specifically shown, the microcomputer 8 includes a central processing unit (CPU), a program memory that holds an operation program of the central processing unit, and a work RAM that is a work area of the central processing unit.

  The input / output terminal I / O [7: 0] of the flash memory 1 is also used for address input, data input / output, and command input. The X address signal (sector address signal) input from the input / output terminal I / O [7: 0] is supplied to the address buffer 4 via the interface control unit 3, and the input Y address signal passes through the interface control unit 3. Via the Y address counter 5. If the Y address signal is not supplied, the Y address counter 5 maintains the reset state of the initial value. A command input from the input / output terminal I / O [7: 0] is supplied to the command decoder 7 via the interface control unit 3. Write data to the memory bank input from the input / output terminal I / O [7: 0] is given to the data input / output control circuit 9 via the interface control unit 3, and is written in the memory bank to be written in 8-bit units. Supplied in. Read data from the memory bank is supplied from the data input / output control circuit 9 to the input / output terminals I / O [7: 0] via the interface control unit 3. Note that a signal input / output from the input / output terminal I / O [7: 0] is also referred to as a signal I / O [7: 0] for convenience.

  The interface control unit 3 inputs the chip enable signal / CE, the output enable signal / OE, the write enable signal / WE, the serial clock signal SC, the reset signal / RES, and the command enable signal / CDE as access control signals. The symbol / immediately before the signal name means that the signal is low enable. The interface control unit 3 controls the signal interface function with the outside according to the state of these signals.

  Each of the memory banks MBNK0 to MBNKn has a large number of nonvolatile memory cells in which stored information can be rewritten. An X address signal for selecting a nonvolatile memory cell from the memory banks MBNK0 to MBNKn is output from an address buffer 4, and a Y address signal for selecting a nonvolatile memory cell from the memory banks MBNK0 to MBNKn is an address counter 5. Is output from.

  The memory banks MBNK0 to MBNKn are not particularly limited, but include a memory cell array (MARY) 11, an X decoder 12, a sense latch circuit (SLAT) 16, a data buffer (DBUF) 15, a Y selector (YSEL) 14, and Y A decoder (YDEC) 13 and the like are included. The memory cell array 11 has a large number of electrically erasable and writable nonvolatile memory cells. The memory cell array 11, the X decoder 12, and the sense latch circuit 16 constitute a nonvolatile memory unit.

  For example, as illustrated in FIG. 2, the nonvolatile memory cell MC includes a source ST and a drain DT formed in a semiconductor substrate or a memory well SUB, and a floating gate FG formed in the channel region via an oxide film, The control gate CG is configured to overlap the floating gate FG via an interlayer insulating film.

  In the case of the AND type array illustrated in FIG. 3, the memory cell array 11 is connected to the main bit line MBL by way of a representatively illustrated subbit SBL via a selection MOS transistor M1 and is non-volatile to the subbit line SBL. The drain of the memory cell MC is coupled. The sources of the nonvolatile memory cells MC that share the sub-bit line SBL are commonly connected to the source line SL via the selection MOS transistor M2. The selection MOS transistor M1 is switch-controlled by the bit line control line SDi in the row direction unit, and the selection MOS transistor M2 is switch-controlled by the source line control line SSi in the row direction unit. The control gate of the nonvolatile memory cell MC is connected to the word line WL in the row direction unit. As illustrated in FIG. 1, each memory cell array 11 is a set of a plurality of sectors SCT0 to SCTi. Each sector is not particularly limited, but is a set of memory cells for j bytes sharing the word line WL.

  The sense latch circuit 16 has a plurality of sense latches (not shown) connected to the main bit lines in a one-to-one correspondence. The sense latch mainly comprises a static latch and includes a precharge circuit and a discharge circuit for a main bit line, and a sense node as one data input / output node is connected to a corresponding main bit line. The reference node, which is the other data input / output node in each sense latch, is connected to one data input / output terminal of the data buffer 15. The data buffer 15 outputs and outputs data in parallel with all the main bit lines MBL. The other data input / output terminal of the data buffer 15 is connected to the Y selector 14.

  The X decoder 12 decodes the X address signal and selects the word line WL, the bit line control line SDi, and the source line control line SSi illustrated in FIG. 3 according to the designated memory operation. The Y selector 14 has j-byte transfer gate switches (Y switches), and each Y switch is connected to the other j-byte data input / output terminals of the data buffer 15 in a one-to-one correspondence. The Y decoder 13 decodes the Y address signal output from the address counter 5 and selects a transfer gate switch (Y switch) of the Y selector 14 in units of bytes. Data is input / output between the data buffer 15 and the input / output circuit 9 in byte units via the selected Y switch. Therefore, if the address counter 5 is sequentially incremented from the initial value, the j-byte storage area of the data buffer is sequentially selected from the lowest to the highest in byte units via the Y decoder 13 and the Y selector 14, Data input / output operation is enabled between the selected byte area and the input / output circuit 9.

  Information storage of the nonvolatile memory cell utilizes the fact that the threshold voltage (Vth) of the memory cell changes according to the amount of charge stored in the floating gate as a charge holding region. At this time, the threshold voltage of the memory cell is limited to a desired range according to the value of the stored data, and the threshold voltage distribution is called a memory threshold voltage distribution. For example, when 2-bit information is stored in one nonvolatile memory cell, four types of memory threshold voltage distributions corresponding to data “01”, “00”, “10”, and “11” as storage information are obtained. It is decided. In order to obtain these memory threshold voltage distributions, an erase operation for obtaining the storage information “11” is performed, and a write verify voltage applied to the word line during the subsequent write operation is set to three different voltages. These three kinds of voltages may be switched sequentially to perform the write operation in three steps. In the writing process, for example, 0V may be applied to the bit line selected for writing, 6V may be applied to the unselected bit line, and 17V may be applied to the word line. Whether 0V or 6V is applied to the bit line is determined by the logical value of the write control data latched by the corresponding sense latch. Whether “1” or “0” is set in the sense latch during the writing process is controlled according to the write data in the data buffer. In the erase operation, for example, the bit line is set to 2V, the selected word line applied voltage is set to -16V, and the unselected word line is set to 0V, and the erase operation is performed in units of word lines.

  FIG. 4 illustrates storage information of a nonvolatile memory cell and a threshold voltage distribution corresponding thereto. VW0, VW1, VW2, and VW3 are lower skirt verify voltages corresponding to the stored information “11”, “10”, “00”, and “01” at the time of write verify. VEW0, VEW1, and VEW2 are upper skirt verify voltages corresponding to the stored information “11”, “10”, and “00” at the time of write verify. The threshold voltage distribution corresponding to the stored information “11”, “10”, “00”, “01” is defined by these upper and lower verify voltages. VRWL, VRWM, and VRWH are read word line voltages (read determination levels) for enabling determination of stored information “11”, “10”, “00”, and “01” during a read operation.

  In the read process, although not particularly limited, the read word line voltage is switched in the order of VRWM, VRWH, and VRWL. The logical value (logical value 0 when Vth> VRWM and logical value 1 when Vth <VRWM) obtained in the sense latch by setting the read word line voltage to VRWM determines the upper bits of the 2-bit storage information. Next, when the logical value obtained by setting the read word line voltage to VRWH is 0 (Vth> VRWH), the lower bit of the stored information is determined to be the logical value 1. Finally, when the logical value obtained by setting the read word line voltage to VRWL is 0 (Vth> VRWL), the lower bits of the stored information are logical values 0, and when the logical value is 1 (Vth <VRWL) The lower bit of the stored information is determined to be a logical value 1. As described above, the read word line level is switched three times, and the 2-bit stored information can be reproduced based on the data sequentially read three times by the sense latch circuit. Conversely, in the write operation, write control data is generated according to the 2-bit unit value of the write data held in the data buffer and applied to the sense latch, thereby forming a threshold voltage distribution corresponding to the 2-bit write data. Write processing is enabled at the timing. The logic for reproducing the 2-bit stored information and the logic for generating the write control data based on the 2-bit write data are provided in an interface portion with the sense latch circuit 16 in the data buffer 15 although not particularly shown. Yes.

  As described above, in the read operation, the stored information is determined based on the information read to the sense latch circuit 16 from the j-byte non-volatile memory cell whose selection terminal is connected to the selected one word line. Stored in the data buffer 15. The storage information stored in the data buffer 15 is transferred to the data input / output control circuit 9 in units of bytes selected by the Y decoder 13 and the Y selector 14, and is transferred to the outside from the input / output terminals I / O [7: 0]. Is output. In the write operation, sector data to be written (sector data before writing) is stored in the data buffer 15 via the sense latch 16, and all or part of the sector data before writing stored in the data buffer is input / output terminals. It is updated by write data input in units of 8 bits from I / O [7: 0]. Which byte of the sector data before writing is updated is determined by the operation of the Y selector 14. Thereafter, writing is performed in units of sectors using data in the updated sector. When all the data for one sector is rewritten, it suffices to fill the data buffer 15 with the write data from the beginning to the end. When a part of the sector is rewritten, it is only necessary to update only a part of the data buffer 15 corresponding to the part to be rewritten using the address preset function of the address counter 5 with the write data.

  The internal power supply circuit 6 generates various operation power supplies for writing, erasing, verifying, reading, and the like and supplies them to the memory banks MBNK0 to MBNKn.

  The command decoder 7 and MCU 8 generally control memory operations such as writing to the multibank in accordance with an access command supplied from the interface control unit 3. The access command is not particularly limited, but includes one or a plurality of command codes and address information and data information necessary for executing the command according to a predetermined format.

  FIG. 5 illustrates sector address mapping of the memory banks BNK0 to BNK3. The sector address is a sector unit address, and adjacent sector addresses are arranged in different memory banks. For example, the sector address Adr = 0x00 is BNK0, the next sector address Adr = 0x01 is the next BNK1, the next sector address Adr = 0x02 is the next BNK2, the next sector address Adr = 0x03 is the next BNK3, the next sector Address Adr = 0x04 returns to the beginning and is mapped in the order of BNK0.

<Flash memory command>
Commands for instructing the operation of the memory bank in the flash memory 1 are roughly classified into a single bank command and a multi-bank command. Data input / output operation between the external and the data buffer is instructed by a buffer command.

  The operation instruction by the buffer command uses a strobe signal. Buffer read is instructed by the low level of / OE, and buffer write is instructed by the low level of / WE. The buffer command is accompanied by a sector address, and the buffer write command is accompanied by write data.

  The single bank read command includes a bank read command code and one sector address. When the flash memory 1 receives the single bank read command, the flash memory 1 performs an internal operation of reading the storage information of the designated sector from the memory cell and storing it in the data buffer 15. A buffer read command is used for reading from the data buffer 15 to the outside. The single bank write command includes a bank write command code, one sector address, and a write start command. When the flash memory 1 receives the single bank write command, it reads the data of the designated sector into the sense latch according to the write sequence, and generates the write control data according to the value of the 2-bit unit of the write data held in the data buffer. Then, the information of the sense latch is updated, and the write selection and non-selection write operations and the write verify operation are performed according to the hold information of the sense latch. For writing the write data to the data buffer 15, a buffer write command is used. The single bank erase command includes a bank erase command code, one sector address, and an erase start command. When the flash memory 1 receives the single bank erase command, the flash memory 1 performs an erase operation and erase verify operation for erasing the data in the designated sector according to the erase sequence.

  The multi-bank command includes instruction information on the number of access sectors with respect to the single bank command. The number of access sectors that can be specified is 2 or more and n or less, and is 2 to 4 in this example. The memory bank to be accessed in the multi-bank command starts from the memory bank specified by the sector address information, and the plurality of continuous memory banks specified by the number of access sectors are the access target memory banks. The multi-bank read command includes a bank read command code and a plurality of sector addresses. When the flash memory 1 receives the multi-bank read command, the flash memory 1 performs an internal operation of reading storage information of a plurality of designated sector addresses from the memory cell and storing it in the data buffer 15. A buffer read command is used for reading from the data buffer 15 to the outside. The multi-bank write command includes a bank write command code, a plurality of sector addresses, and a write start command. When the flash memory 1 receives the multi-bank write command, it reads the data of the designated sectors into the sense latch according to the write sequence, and generates the write control data according to the value of the 2-bit unit of the write data held in the data buffer Then, the information of the sense latch is updated, and the write selection and non-selection write operations and the write verify operation are performed according to the hold information of the sense latch. For writing the write data to the data buffer 15, a buffer write command is used. The single bank erase command includes a bank erase command code, a plurality of sector addresses, and an erase start command. When the flash memory 1 receives the single bank erase command, the flash memory 1 performs an erase operation and erase verify operation for erasing the data in the designated sector according to the erase sequence.

《Dummy reading》
The command decoder 7 decodes the command, and instructs the MPU 8 to perform processing corresponding to the result of decoding such as the memory bank to be accessed and the type of bank access specified by the command. The MPU 8 performs control according to the instruction. In the case of the bank read command, the MPU 8 performs the read operation using the read determination level VEWM (S1r), the read operation using the read determination level VEWH (S2r), as shown in FIG. A read operation (S3r) using the read determination level VEWL is performed. In each read operation, bit line precharge, word line selection, sense amplifier activation, and transfer of read detection data from the sense amplifier to the data buffer 15 are performed. On the other hand, the MPU 8 performs a read operation (dummy read operation) for reading stored information from the non-volatile memory cells also for the non-access target memory bank. That is, for the non-access target memory bank, the S1r, S2r. The bit line precharge, word line selection, and sense amplifier activation operations are performed in the same manner as the read operations in S3r, but the read detection data is not transferred from the sense amplifier to the data buffer 15. This is to prevent the data from being undesirably destroyed when valid data to be used later is stored in the data buffer 15 of the read unselected memory bank. For example, when the operation of the memory bank MBNK1 is designated by a single bank read command, the read detection data is not transferred from the sense amplifier to the data buffer 15 for the remaining memory banks MBNK0, MBNK2, and MBNK3. A read operation is executed for each of the memory banks MBNK0 to MBNK3. When the operations of the memory banks MBNK1 to MBNK3 are designated by the multi-bank read command, the memory bank MBNK0 is not transferred to the remaining memory bank MBNK0 except that the read detection data is not transferred from the sense amplifier to the data buffer 15. ... Read operation is performed for MBNK3. Word selection in the non-access target memory bank may be performed using the same sector address as the access target memory bank.

  In the case of the bank erase command, the MPU 8 performs the erase bias voltage application operation (S1e) to the erase target sector and the erase verify operation for the nonvolatile memory cell of the erase target sector, as shown in FIG. (S2e) An upper skirt check operation (S3e) is performed on the nonvolatile memory cell in the sector to be erased. In the erase verify operation (S2e), all memory cells in the sector to be erased are selected by the verify voltage VWV0, and control data for suppressing the erase bias is supplied to the sense latch corresponding to the nonvolatile memory cell turned off. The operation is repeated until all the memory cells are turned off. In the upper skirt check operation (S3e), all the memory cells in the sector to be erased are selected at the 11 upper skirt verify voltage VWE0 to detect whether at least one nonvolatile memory cell is in an off state, and at least one An erase error is detected when it is detected that one of the nonvolatile memory cells is in an off state. On the other hand, the MPU 8 also performs a read operation (dummy read operation) for reading stored information from the non-volatile memory cells in the erase verify operation (S2e) and the 11 upper skirt check (S3e) for the non-access target memory bank. That is, bit line precharge, word line selection and sense amplifier activation are performed on the non-access target memory bank in the same manner as in S2e and S3e, but the determination operation and determination result are output to the MPU 8. No action is taken. Word selection in the non-access target memory bank may be performed using the same sector address as the access target memory bank.

  In the case of the bank write command, the MPU 8 applies the 01 write bias voltage application operation to the write target sector (S1w) and the 01 write to the nonvolatile memory cell in the write target sector, as shown in FIG. Verify operation (S2w), application operation of 00 write bias voltage to write target sector (S3w), 00 write verify operation to nonvolatile memory cell of write target sector (S4w), application operation of 10 write bias voltage to write target sector ( S5w), and 10 write verify operation (S6w) is performed on the nonvolatile memory cell in the write target sector. Thereafter, the MPU 8 performs the 00 upper skirt check operation (S7w) for the nonvolatile memory cell in the write target sector and the 10 upper skirt check operation (S8w) for the nonvolatile memory cell in the write target sector. In the write verify operation (S2w), all memory cells in the write target sector are selected by the verify voltage VWV1, and control data for suppressing the write bias is supplied to the sense latch corresponding to the nonvolatile memory cell turned off. The operation is repeated until all the memory cells are turned off. In the write verify operation (S4w), the same determination operation is performed at the verify voltage VWV2. In the write verify operation (S6w), the same determination operation is performed at the verify voltage VWV3. In the upper skirt check operation (S7w), all memory cells in the write target sector are selected by the word line at the 00 upper skirt verify voltage VWE2, and it is detected whether at least one nonvolatile memory cell is in the OFF state. A write error is detected when it is detected that one of the nonvolatile memory cells is in the off state. In the upper skirt check operation (S8w), the same determination operation is performed using the 10 upper skirt verify voltage VWE1. On the other hand, the MPU 8 also performs a read operation (dummy read operation) for reading stored information from the nonvolatile memory cells in the write verify operation (S2w, S4w, S6w) and the upper skirt check (S7w, S8w) for the non-access target memory bank. Do. In other words, the bit line precharge, word line selection, and sense amplifier activation operations are performed on the non-access target memory banks in the same manner as the operations of S2w, S4w, S6w, S7w, and S8w. The operation of outputting the determination result to the MPU 8 is not performed. Word selection in the non-access target memory bank may be performed using the same sector address as the access target memory bank.

  As described above, the dummy read operation is performed in the remaining memory banks regardless of the number of memory banks instructed to be accessed by the command. Regardless of the state of the access operation instruction by the command, the read operation in response to the bank read command, the write verify operation and the upper tail check operation in response to the bank write command, and the erase verify operation and upper foot check in response to the bank erase command In operation, the overall power consumption state in all memory banks is substantially constant. As a result, even if the number of parallel memory banks whose operation is specified by the command is different, an undesired change in the read logical value of the stored information held in the nonvolatile memory cell is unlikely to occur. FIG. 9 illustrates how the threshold voltage distribution apparently changes in several types of multi-bank operations when dummy reading is not performed. A characteristic indicated by A indicates an apparent threshold voltage distribution when parallel writing is performed in a multi-bank and reading is performed in a single bank. A characteristic indicated by B indicates an apparent threshold voltage distribution when parallel writing is performed in a multibank and parallel reading is performed in a multibank. A characteristic indicated by C indicates an apparent threshold voltage distribution when writing is performed in a single bank and parallel reading is performed in a single bank. A characteristic indicated by D indicates an apparent threshold voltage distribution when writing is performed in a single bank and parallel reading is performed in a multibank. In the 50% distribution, the apparent threshold voltage changes by about 0.2V. On the other hand, the apparent threshold voltage change is approximately 0.1 V in the 50% distribution between the B characteristic and the D characteristic for performing multi-bank parallel reading. From this, it is clear that the undesired change in the threshold voltage is apparently reduced by performing the dummy read operation.

  FIG. 10 shows another example of the flash memory. The flash memory 1A shown in FIG. 1 performs a dummy read operation in the same manner as the flash memory 1, but the configuration relating to the operation power supply control for the memory banks MBNK0 to MBNK3 is different. That is, the control unit 2 controls the supply state of operation power by the power supply circuit 6 according to the number of memory banks whose operation is designated by the command CMD. In the power supply circuit, a voltage necessary for operation is selected by a selection signal 20 from the control unit 2 and supplied to the memory banks MBNK0 to MBNK3. The parallel operation bank number information 21 informs the power supply circuit of the number of banks operating in parallel. The controller 2 increases the power supply voltage of the operation power supply as the number of memory banks designated for operation increases, or increases the current supply capability of the operation power supply as the number of memory banks designated for operation increases. When the power supply circuit includes a charge pump circuit as a booster circuit, thereby generating various internal voltages, in the case of a circuit configuration that needs to compensate exclusively for the voltage effect when the number of parallel operation banks is large, the charge pump includes: It is a good idea to employ a circuit configuration in which many pump elements are connected in series. On the other hand, when generating various internal voltages, in the case of a circuit configuration that needs to compensate exclusively for the current supply capability when the number of parallel operation banks is large, the charge pump has a circuit configuration in which a number of pump elements are connected in parallel. It is a good idea to adopt it. With the configuration of FIG. 10, the change in the operating voltage can be reduced even when the number of parallel memory banks whose operation is specified by a command in operations other than the read operation including dummy read is different.

  FIG. 11 shows another example of the flash memory. The flash memory 1A shown in FIG. 1 performs a dummy read operation in the same manner as the flash memory 1, but the configuration relating to the operation power supply control for the memory banks MBNK0 to MBNK3 is different. That is, power supply circuits VGNa to VGNd are provided for each of the memory banks MBNK0 to MBNK3. The control unit 2 supplies operation power from the corresponding power supply circuit among the power supply circuits VGNa to VGNd to the memory bank whose operation is specified by the command, and also supplies the power supply circuit VGNa to the memory bank when performing the dummy read operation. Operation power is supplied from the corresponding power supply circuit of VGNd. The selection signals 21a to 21d and the parallel operation bank number information 21a to 21d are given for each of the power supply circuits VGNa to VGNd. The parallel operation bank number information 21a to 21d is used to notify the number of other memory banks operated in parallel when the operation of the corresponding memory bank is selected. The power supply circuits VGNa to VGNd increase the power supply voltage of the operation power supply as the number of memory banks specified for operation increases, or increase the current supply capability of the operation power supply as the number of memory banks specified for operation increases. . According to the configuration of FIG. 11, the change in the operating voltage can be reduced even when the number of parallel memory banks whose operation is specified by a command is different in operations other than the read operation.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the nonvolatile memory is not limited to the flash memory, and may be an MNOS, a ferroelectric memory cell, or the like. Further, the information stored in the memory cell is not limited to 2 bits per memory cell, and may be multi-value of 1 bit or 3 bits or more. In the case of a memory cell capable of multi-value storage, multi-value storage may be performed by performing multi-value storage depending on a difference in threshold voltage, or by accumulating charges locally in a storage gate. Further, the configuration of the memory cell array of the flash memory is not limited to the AND type, and can be appropriately changed to a NOR type, a NAND type, or the like. Needless to say, the threshold voltage definition for erasing and writing may be the reverse of this specification. Also, the command type, write data input method, number of parallel input bits, and the like may be different from the above. Data, an address, and a command may be input from dedicated terminals. The nonvolatile memory is not limited to a single memory chip. It may be an on-chip memory mounted on a data processing chip such as a microcomputer.

1 is an overall block diagram of a flash memory according to the present invention. 2 is a schematic cross-sectional view illustrating a cross-sectional structure of a nonvolatile memory cell. FIG. It is a circuit diagram which illustrates an AND type array as composition of a memory cell array. It is explanatory drawing which illustrates the memory | storage information of a non-volatile memory cell, and threshold voltage component distribution corresponding to it. It is explanatory drawing which shows an example of the mapping of the sector address of a memory bank. It is a flowchart which illustrates the processing flow which responds to a bank read command. It is a flowchart which illustrates the processing flow which responds to a bank erase command. It is a flowchart which illustrates the processing flow which responds to a bank write command. FIG. 10 is a characteristic diagram showing how the threshold voltage distribution apparently changes in several types of multi-bank operations when dummy reading is not performed. FIG. 9 is a schematic configuration diagram of another flash memory configured to perform operation power control of a memory bank in accordance with the number of memory banks operating in parallel in addition to dummy reads. It is a schematic block diagram of another flash memory in which a power supply circuit is provided for each memory bank that operates in parallel in addition to a dummy read.

Explanation of symbols

1 Flash memory MBNK0 to MBNKn Memory bank 2 Control unit (CNT) 2
3 Interface controller (IF)
4 Address buffer (ABUF)
5 Address counter (ACNT)
6 Internal power supply circuit (VGN)
7 Command decoder (CDEC)
8 Microcomputer (MPU) 8
9 Data input / output control logic (DIO)
11 Memory cell array (MARY)
12 X decoder 12
13 Y decoder (YDEC)
14 Y selector (YSEL)
15 Data buffer (DBUF)
16 sense latch circuit (SLAT)

Claims (11)

A plurality of memory banks each capable of independently operating a memory, and a control unit that controls memory operations of the plurality of memory banks;
The memory bank has a large number of electrically rewritable nonvolatile memory cells;
The control unit can operate the plurality of memory banks in parallel in response to a command given from the outside,
The control unit is a non-volatile memory that, when there is at least one memory bank that reads stored information in response to the command, causes the remaining memory banks to perform dummy reading of the stored information in parallel with the reading.   The non-volatile memory according to claim 1, wherein the control unit invalidates a read result of the dummy read by blocking a transmission path of the read result of the dummy read. The memory bank includes a nonvolatile memory unit having the nonvolatile memory cell, and a data buffer buffer unit connected to the nonvolatile memory unit,
The data buffer unit temporarily holds data read from the nonvolatile memory unit and can output the data to the outside, and temporarily holds write data supplied from the outside and can supply the data to the memory unit. The non-volatile memory according to claim 1.   The non-volatile memory according to claim 3, wherein the control unit does not transfer data read by the non-volatile memory unit by the dummy reading to the data buffer unit. The nonvolatile memory section includes a plurality of bit lines connected to data terminals of the nonvolatile memory cells, a sense latch connected to the respective bit lines, and a plurality of words connected to selection terminals of the nonvolatile memory cells. Line and
The nonvolatile memory according to claim 4, wherein the control unit causes the sense latch to latch data read from the nonvolatile memory cell to the bit line by the dummy reading.   2. The nonvolatile memory according to claim 1, wherein the control unit causes the dummy read to be executed in response to an operation in response to a read command for reading storage information of the nonvolatile memory cell from the nonvolatile memory unit to the data buffer unit.   When the control unit responds to a write command for setting a threshold voltage of a nonvolatile memory cell in a corresponding nonvolatile memory unit according to the write data held by the data buffer unit, the control unit performs the dummy read along with a write verify operation. The non-volatile memory according to claim 1, which is executed.   2. The nonvolatile memory according to claim 1, wherein the control unit causes the dummy read to be executed in association with an erase verify operation when responding to an erase command for initializing a threshold voltage of the nonvolatile memory cell. A power supply circuit for supplying operating power to the plurality of memory banks;
The control unit controls the supply state of operation power by the power supply circuit according to the number of memory banks whose operation is designated by a command,
The control unit increases the power supply voltage of the operation power supply as the number of memory banks designated for operation increases, or increases the current supply capability of the operation power supply as the number of memory banks designated for operation increases. The non-volatile memory according to 1. A plurality of power supply circuits that individually supply operation power to the plurality of memory banks in a one-to-one correspondence;
The control unit supplies operation power from a corresponding power supply circuit to a memory bank whose operation is designated by a command, and supplies operation power from the power supply circuit to the memory bank when performing the dummy operation. Non-volatile memory. A plurality of memory banks each capable of independently operating a memory, and a control unit that controls memory operations of the plurality of memory banks;
The memory bank has a large number of electrically rewritable nonvolatile memory cells;
The control unit can operate the plurality of memory banks in parallel in response to a command given from the outside,
When there is at least one memory bank that reads stored information in response to the command, the control unit causes the remaining memory banks to execute reading while interrupting the middle of the read path in parallel with the reading. Non-volatile memory.

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