CN109524047B - Byte programming retry method of flash memory - Google Patents
Byte programming retry method of flash memory Download PDFInfo
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- CN109524047B CN109524047B CN201811197887.2A CN201811197887A CN109524047B CN 109524047 B CN109524047 B CN 109524047B CN 201811197887 A CN201811197887 A CN 201811197887A CN 109524047 B CN109524047 B CN 109524047B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
- G11C16/3481—Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
Abstract
The invention provides a byte programming method of a flash memory and a byte programming retry method thereof, wherein the byte programming method is to program a plurality of byte storage areas of the memory in sequence by taking a plurality of bytes as a unit in the same time sequence period, and then verify the reliability of the memory. The programming retry method divides the standard time of byte programming into a plurality of sections with the same time interval, and executes the following steps in the same time sequence period: and in the current time period, programming operation is carried out on a plurality of byte storage areas of the memory by taking a plurality of bytes as a unit, whether the programming operation passes or not is verified, if so, the programming operation in the subsequent time period is not verified, otherwise, whether the programming operation passes or not is repeatedly verified in the next time period until all the time period verification is completed. The invention has the technical effects of shortening the programming time of the reliability test of the memory and improving the test efficiency.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a byte programming retry method of a flash memory.
Background
The memory is a memory device of the computer system for storing programs and data. The memory is divided into volatile memory and nonvolatile memory. Volatile memory loses the data stored therein immediately upon system shutdown; it requires a continuous power supply to maintain the data. Non-volatile memory retains data when the system is shut down or no power is supplied. For non-volatile memories, the reliability of data storage (implementation Performance) is one of the parameters that evaluate memory Performance. Therefore, the performance of the memory needs to be evaluated by a reliability test before the memory is shipped. For the nonvolatile Memory being a Flash Memory (Flash Memory), the method of verifying the reliability of the Flash Memory generally employs an erasing method. The working principle of the erasing method is as follows: a bit of data is erased and read again to verify the reliability of the erased data. When the erasing data of the bit is consistent with the reading data, the reliability of the flash memory is verified to be effective. This approach is suitable for micron-scale flash memories. Flash memories fabricated with 0.38um and 0.197um processes, for example, can be verified for reliability using an erase method. The disadvantage of the above method is that it is only applicable to bit-operated flash memories. Therefore, a programming method using byte operation is proposed for nanoscale flash memory to verify the reliability of flash memory. For example: for a 90nm flash memory, a standard Byte Program Retry (Byte Program Retry) method can be used, which works on the principle: after a single byte operation, i.e., a single byte corresponding to a single byte memory region programming retry, the reliability of the flash memory is verified. For example, for the current test byte, firstly erasing the data of the byte storage area, secondly reading the erased data of the byte storage area, then writing single data into the byte storage area, and lastly reading the written data of the byte storage area, and then verifying the reliability of the flash memory. Namely single byte programming and single byte verification. This byte programming method requires about 50us for the rise time (Ramp up) and the fall time (Ramp down) of the Program Pump (Program Pump) since the byte programming time is 6 us. I.e. a single byte has a programming time of 50us +6 us-56 us, and when 512 bytes need to be tested, it has a programming time of 56us x 512-28672 us. Therefore, the programming time is long, which not only affects the reliability test time of the flash memory, but also affects the operating speed of the flash memory. The flash memory is a digital integrated circuit chip, programming of the flash memory is to execute an operation of a digital high level signal 1 or a digital low level signal 0 aiming at a storage area, and due to the fact that a single byte programming operation is carried out in a standard byte programming method, the programming depth of the flash memory is only suitable for the absolute 0 condition, but not suitable for a flash memory with a non-absolute 0 of a mirror image structure, namely when the flash memory with the non-absolute 0 mirror image structure is divided into high and low level signals by taking 0.5V as a reference, the low level signals are low level signals when the voltage is lower than 0.5V, the low level signals are actually non-0, and the standard byte programming method considers that the voltages above 0V are all 1, so that the programming operation of the flash memory fails. The standard byte programming method is directed to a flash memory with a large programming current, that is, a flash memory supporting a fast programming technology, rather than a flash memory supporting a chip writing technology, such as a SONOS flash memory.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a retry method for byte programming of a flash memory to shorten the programming time of reliability test.
In order to solve the above technical problem, the present invention provides a retry method for byte programming of a flash memory, which divides a standard time for byte programming into a plurality of segments with the same time interval, and executes the following steps within the same time period: in the current time period, programming operation is carried out on a plurality of byte storage areas of the memory by taking a plurality of bytes as a unit, whether the programming operation passes or not is verified, if the programming operation passes, the verification program is ended, the programming operation in the subsequent time period is not verified, and the verification success of the reliability of the memory is judged, otherwise, the reliability verification failure of the memory is judged; in the next time period, programming operation is carried out on a plurality of byte storage areas of the memory by taking a plurality of bytes as units, and whether the programming operation passes or not is repeatedly verified until verification in all the time periods is completed; and when the verification of the multi-section programming operation fails, judging that the reliability test of the memory completely fails.
Furthermore, the byte programming retry method of the flash memory provided by the invention divides the standard time of byte programming into three sections with the same time interval, and executes the following steps in the same time sequence cycle: in a first time period, carrying out first programming operation on a plurality of byte storage areas of the memory by taking a plurality of bytes as units, verifying whether the first programming operation passes, if so, ending a verification program, and judging that the reliability of the memory is successfully verified, otherwise, judging that the reliability of the memory fails to be verified; in a second time period, performing second programming operation on a plurality of byte storage areas of the memory by taking a plurality of bytes as units, verifying whether the second programming operation passes, if so, ending the verification program, and judging that the reliability verification of the memory is successful, otherwise, judging that the reliability verification of the memory fails; and in a third time period, carrying out third programming operation on a plurality of byte storage areas of the memory by taking a plurality of bytes as a unit, verifying whether the third programming operation passes, if so, judging that the verification of the reliability of the memory is successful, otherwise, judging that the verification of the reliability of the memory fails.
Further, the retry method for byte programming of flash memory provided by the present invention, wherein the step of programming the plurality of byte storage areas of the memory in units of a plurality of bytes within the same timing cycle comprises: within the same time sequence period, sequentially executing data erasing operation, data reading erasing operation, data writing operation and data reading writing operation on a plurality of byte storage areas of the memory; the step of verifying the reliability of the memory comprises: when the erasing data and the read erasing data which are sequentially executed by the plurality of byte storage areas of the memory are consistent, and the written data and the read written data are consistent, verifying that the reliability of the plurality of byte storage areas of the memory passes, otherwise, not passing.
Further, the byte programming retry method of the flash memory provided by the invention sequentially programs the row or half-row storage area of the memory by taking a plurality of bytes as a unit in the same time sequence period, and then verifies the reliability of the memory.
Furthermore, the byte programming retry method of the flash memory provided by the invention programs the sector or half-sector storage area of the memory in sequence by taking a plurality of bytes as a unit in the same time sequence period, and then verifies the reliability of the memory.
Furthermore, the byte programming retry method of the flash memory provided by the invention sequentially programs the block or half block storage area of the memory by taking a plurality of bytes as a unit in the same time sequence period, and then verifies the reliability of the memory.
Furthermore, the byte programming retry method of the flash memory provided by the invention sequentially programs the page or half-page storage area of the memory by taking a plurality of bytes as a unit in the same time sequence period, and then verifies the reliability of the memory.
Further, the invention provides a byte programming retry method of the flash memory, wherein the flash memory is a nanoscale flash memory.
Compared with the prior art, the byte programming retry method of the flash memory provided by the invention divides the time sequence cycle of byte programming into a plurality of sections with the same time interval, after the programming operation of the memory is verified in the current time period, the verification program is ended, the subsequent programming operation is not verified, if the programming operation is not verified, the verification is repeated in the next time period until the verification in all the time periods is completed. The byte programming retry method of the flash memory provided by the invention adopts the byte programming method, so the method also has the technical effects of shortening the programming time of the reliability test of the memory and improving the test efficiency of the reliability of the memory.
Drawings
FIG. 1 is a flow chart of a method of byte programming of a flash memory;
FIG. 2 is a flow chart of a method for sequentially programming a plurality of byte storage areas of a flash memory;
fig. 3 is a flowchart of a program retry method of a flash memory.
Detailed Description
The invention is described in detail below with reference to the attached drawing figures:
example one
Referring to fig. 1, the present embodiment provides a byte programming method for a flash memory, which sequentially programs a plurality of byte storage areas of the flash memory by taking a plurality of bytes as a unit in the same timing cycle, and then verifies the reliability of the flash memory. The sequential programming means that a plurality of bytes are sequentially programmed in a plurality of byte storage areas of the memory, and taking six bytes as an example, the six bytes are sequentially programmed in six byte storage areas corresponding to the memory.
Referring to fig. 2, the step of programming the byte storage areas of the memory in units of bytes in the same timing cycle includes:
in the same time sequence period, the operation of erasing data, the operation of reading the erasing data, the operation of writing the data and the operation of reading the writing data are sequentially executed on a plurality of byte storage areas of the memory.
The step of verifying the reliability of the memory comprises the following steps: when the erasing data and the read erasing data which are sequentially executed by the plurality of byte storage areas of the memory are consistent, and the written data and the read written data are consistent, verifying that the reliability of the plurality of byte storage areas of the memory passes, otherwise, not passing.
The standard time for byte programming in the first embodiment is 6us, the sum of the rising edge process and the falling edge process of the timing cycle of the programming pump for byte programming is 50us, and the high level and the low level duration of the timing cycle are ignored.
The embodiment is an improvement of a byte programming method of a flash memory, and in the same time sequence period, a plurality of byte storage areas of the memory are sequentially programmed by taking a plurality of bytes as a unit, and then the reliability of the memory is verified. Because the programming operation is carried out on the plurality of byte storage areas of the memory in the same time sequence period, namely after the plurality of byte data are programmed into the plurality of byte storage areas of the memory, the reliability of the plurality of byte storage areas is integrally verified. That is, the invention verifies a plurality of byte storage areas at one time outside the same time sequence period, and the high-low level transition of the time sequence period only needs one ascending and descending process. Instead of immediately verifying the reliability of the storage area corresponding to a single byte after programming the single byte, each verification requires a separate time sequence period and each verification requires a rising and falling process of high-low level conversion, taking N bytes as an example, a standard byte programming method is adopted, the programming of the reliability test needs to be respectively carried out for multiple times in N time sequence periods, and the programming of the reliability test only needs to be carried out once in one time sequence period by adopting the byte programming method of the invention, so that the invention saves N-1 time sequence periods compared with the standard byte programming method, thereby shortening the programming time of the reliability test of the memory and improving the efficiency of the reliability test of the memory. Wherein N is a natural number greater than 1. For example, when the same test is performed on 512 bytes, the programming time is (50us +6us) × 512 ═ 28672us when the single byte programming method in the prior art is adopted, whereas when the byte programming method of the flash memory of the present invention is adopted, the programming time is 50us +6us × 512 ═ 3122us, and as can be seen by comparison, under the condition of the same byte length, after the technical scheme of the present invention is adopted, the (512-1) × 50us ═ 25550us can be saved, so that the programming time of the memory reliability test is shortened, and the test efficiency is improved.
In a preferred embodiment, the byte programming method for a flash memory according to the present invention sequentially programs a row or half-row memory area of the flash memory in units of a plurality of bytes within a same timing cycle, and then verifies the reliability of the flash memory.
As a preferred embodiment, the byte programming method of the flash memory provided by the present invention sequentially programs the sectors or half sectors of the memory in units of multiple bytes in the same timing cycle, and then verifies the reliability of the memory.
In a preferred embodiment, the byte programming method for a flash memory according to the present invention sequentially programs a block or a half block of a memory in units of a plurality of bytes in a same timing cycle, and then verifies the reliability of the memory.
In a preferred embodiment, the byte programming method for a flash memory according to the present invention sequentially programs a page or a half-page memory area of the flash memory in units of a plurality of bytes in a same timing cycle, and then verifies the reliability of the flash memory.
In the above embodiment, the line memory area, the half-line memory area, the fan memory area, the half-fan memory area, the block memory area, the half-block memory area, the page memory area, or the half-page memory area is programmed in sequence by using a plurality of bytes as a unit, and then the reliability of the memory is verified. The byte number of the row storage area, the byte number of the fan storage area, the byte number of the block storage area and the byte number of the page storage area of the memory with fixed storage capacity are fixed values of a plurality of bytes which are more than 1, and the fixed values form a standard dividing mode in the memory, so the method has the convenience of programming operation, can index to a specific certain row, a certain sector, a certain block area or a certain page, can improve the programming efficiency, and can meet the pointing requirements of different clients.
In this embodiment, a plurality of bytes with a certain capacity can be determined according to the time sequence ratio of the programming pump for sequential programming. For example, the sector storage area of the memory is sequentially programmed in a plurality of bytes according to the time schedule selection of the programming pump, and then the reliability of the memory is verified.
This embodiment is a byte programming method for nanoscale flash memory, for example: it is suitable for 90nm flash memory.
Example two
Second embodiment is a byte programming retry method for a flash memory based on the byte programming method of the first embodiment, which divides the standard time of byte programming into multiple segments with the same time interval, and executes the following steps within the same timing cycle:
and in the current time period, programming the multiple byte storage areas of the memory by taking the multiple bytes as a unit, verifying whether the programming operation passes, if so, ending the verification program, namely, not verifying the programming operation of the subsequent time period, otherwise, in the next time period, programming the multiple byte storage areas of the memory by taking the multiple bytes as a unit, and repeatedly verifying whether the programming operation passes until all the time periods are verified.
Please refer to fig. 3, for example: dividing the standard time of byte programming into three sections with the same time interval, and executing the following steps in the same time sequence period:
in a first time period, carrying out first programming operation on a plurality of byte storage areas of the memory by taking a plurality of bytes as units, verifying whether the first programming operation passes, if so, ending the verification program, not verifying the programming operation in a subsequent time period, and judging that the verification of the reliability of the memory succeeds, otherwise, judging that the verification of the reliability of the memory fails;
in a second time period, carrying out second programming operation on a plurality of byte storage areas of the memory by taking a plurality of bytes as units, verifying whether the second programming operation passes, if so, ending the verification program, not verifying the programming operation in the subsequent time period, and judging that the reliability verification of the memory succeeds, otherwise, judging that the reliability verification of the memory fails;
and in a third time period, carrying out third programming operation on a plurality of byte storage areas of the memory by taking a plurality of bytes as a unit, verifying whether the third programming operation passes, if so, judging that the verification of the reliability of the memory is successful, otherwise, judging that the verification of the reliability of the memory fails.
For example: taking the program data 55AA as an example, the standard time for byte programming is 6us, the standard time is divided into three segments, each segment has a time interval of 2us, and the process time of the rising edge and the falling edge of the high and low levels of the timing cycle of the program pump for byte programming is 50 us. The programming data is not limited to 55AA, but may be any other data. The programming steps are as follows:
executing the following steps in the same time sequence period:
in the first 2us time period, carrying out first programming 55AA operation on a plurality of byte storage areas of the memory, verifying whether the first programming operation passes, namely verifying erased data and written data, if so, finishing the verification program, not verifying the programming operation of the subsequent time period, namely, not verifying the programming operation in the second and third 2us time periods, and judging that the reliability verification of the memory is successful, otherwise, failing to verify the reliability of the memory;
in the second 2us time period, performing second programming 55AA operation on a plurality of byte storage areas of the memory, verifying whether the second programming operation passes, if so, ending the verification program, not verifying the programming operation in the subsequent time period, and judging that the reliability verification of the memory is successful, otherwise, judging that the reliability verification of the memory fails;
and in the third 2us time period, carrying out third programming 55AA operation on the plurality of byte storage areas of the memory, verifying whether the third programming operation passes, if so, judging that the reliability verification of the memory is successful, otherwise, judging that the reliability verification of the memory fails.
And when the verification of the three programming operations fails, judging that the reliability test of the memory completely fails, resetting the test system at the moment, and judging that the memory has a problem or the test system has a problem.
The second embodiment adopts the byte programming method of the flash memory of the first embodiment, so that the technical effects of shortening the programming time of the reliability test of the memory and improving the test efficiency are also achieved.
In the first and second embodiments of the present invention, the number of bytes to be programmed can be arbitrarily selected according to the ratio of the timing of the programming pump to the time consumed by the number of bytes, so that the flexibility of the memory programming operation is improved.
The present invention is not limited to the above-described embodiments, and various changes and modifications within the scope of the present invention are within the scope of the present invention.
Claims (7)
1. A retry method for byte programming of flash memory is characterized in that a standard time for byte programming is divided into a plurality of segments with the same time interval, and the following steps are executed in the same timing cycle: performing a program operation on a plurality of byte storage areas of the memory in units of a plurality of bytes in a current time period, the program operation including: sequentially executing data erasing operation, data reading erasing operation, data writing operation and data reading writing operation on a plurality of byte storage areas of the memory, then verifying the reliability of the memory, verifying whether the programming operation passes, if so, ending the verification program, not verifying the programming operation of the subsequent time period, and judging the verification success of the reliability of the memory, otherwise, judging the reliability verification failure of the memory and executing the next time period; the verifying the authenticity of the memory comprises: when the erasing data executed by the plurality of byte storage areas of the memory is consistent with the read erasing data and the writing data is consistent with the read writing data, verifying that the reliability of the plurality of byte storage areas of the memory passes, otherwise, not passing; and in the next time period, performing programming operation on a plurality of byte storage areas of the memory by taking a plurality of bytes as a unit, and repeatedly verifying whether the programming operation passes or not until all time period verification is completed.
2. The byte program retry method of flash memory according to claim 1, wherein the standard time of byte program is divided into three segments with the same time interval, and the following steps are performed within the same timing cycle;
in a first time period, carrying out first programming operation on a plurality of byte storage areas of the memory by taking a plurality of bytes as a unit, verifying whether the first programming operation passes, if so, finishing a verification program, judging that the reliability of the memory is successfully verified, otherwise, judging that the reliability of the memory fails to be verified, and executing a second time period;
in a second time period, carrying out second programming operation on a plurality of byte storage areas of the memory by taking a plurality of bytes as units, verifying whether the second programming operation passes, if so, finishing the verification program, judging that the reliability verification of the memory succeeds, otherwise, judging that the reliability verification of the memory fails, and executing a third time period;
and in a third time period, carrying out third programming operation on a plurality of byte storage areas of the memory by taking a plurality of bytes as a unit, verifying whether the third programming operation passes, if so, judging that the verification of the reliability of the memory is successful, otherwise, judging that the verification of the reliability of the memory fails.
3. The byte program retry method of a flash memory according to claim 1, wherein the row or half-row memory area of the memory is sequentially programmed in units of a plurality of bytes within the same timing cycle, and then the reliability of the memory is verified.
4. The byte program retry method of a flash memory according to claim 1, wherein sectors or half sectors of the memory are sequentially programmed in units of a plurality of bytes within the same timing cycle, and then the reliability of the memory is verified.
5. The byte program retry method of a flash memory according to claim 1, wherein the block or half block memory area of the memory is sequentially programmed in units of a plurality of bytes within the same timing cycle, and then the reliability of the memory is verified.
6. The byte program retry method of a flash memory according to claim 1, wherein the page or half-page memory area of the memory is sequentially programmed in units of a plurality of bytes within the same timing cycle, and then the reliability of the memory is verified.
7. The byte program retry method of a flash memory as claimed in claim 1, wherein the flash memory is a nanoscale flash memory.
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| KR100954949B1 (en) * | 2008-05-14 | 2010-04-27 | 주식회사 하이닉스반도체 | Multi level cell programming method of non volatile memory device |
| CN101800077B (en) * | 2009-02-11 | 2012-04-18 | 北京兆易创新科技有限公司 | Method and device for carrying out data programming on flash |
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