JP4170261B2 - Nonvolatile semiconductor memory device and data writing or erasing method thereof - Google Patents

Description

  The present invention relates to a nonvolatile semiconductor memory device and a data writing or erasing method thereof, and more particularly, to a nonvolatile semiconductor memory device including a memory cell capable of electrically writing or erasing data and a data writing or erasing method thereof.

  Among electrically rewritable non-volatile semiconductor memories, flash memory whose data is erased all at once or in units of blocks is mounted on a personal computer (PC) or the like and used to store a BIOS (Basic Input / Output System). It is widely used as a memory card for personal computers, digital cameras, and home game machines.

  In flash memory, when writing / erasing data to / from a memory cell, it is necessary to apply a high voltage to the gate and source of the memory cell, and the voltage stress at this time causes a problem and causes deterioration of the memory cell. As a result, the write / erase time is increased and the number of rewrites is reduced. That is, not applying excessive voltage stress to the memory cell at the time of writing / erasing leads to an increase in the number of times of rewriting of the flash memory.

  The memory cell state in the flash memory includes a read state, a write state, and an erase state. FIG. 8 shows a voltage arrangement of voltages applied to the memory cells of the flash memory in these states. 8A shows a voltage arrangement at the time of reading data in the memory cell, FIG. 8B shows a voltage arrangement at the time of writing data in the memory cell, and FIG. 8C shows a voltage arrangement at the time of erasing data in the memory cell.

  Each memory cell can store, for example, 1-bit data of “0” or “1”. In this specification, writing this data to the memory cell is also referred to as “memory cell writing”. In addition, erasing this data from the memory cell is also called “erasing the memory cell”, and reading this data from the memory cell is also called “reading the memory cell”.

  As shown in FIGS. 8A to 8C, the flash memory is composed of a memory cell array including a plurality of memory cells arranged in a matrix in the row direction (X direction) and the column direction (Y direction). Each memory cell includes a MOS transistor. Each MOS transistor has a gate connected to a word line 81 provided in each row of the memory cell array, a drain connected to a bit line 82 provided in each column of the memory cell array, and a source provided in each row of the memory cell array. A source line 83 is connected. By applying a predetermined voltage to the word line 81, the bit line 82, and the source line 83, the data of the selected memory cell is read, written, and erased.

  As shown in FIG. 8A, when reading data from a memory cell, a gate voltage Vread and a drain voltage Vrd are applied to the memory cell to be read. In this example, the power supply potential Vdd is applied to the word line 81 as the gate voltage Vread, 1 V is applied to the bit line 82 as the drain voltage Vrd, and 0 V is applied to the source line 83.

  As shown in FIG. 8B, when data is written in the memory cell, the gate voltage Vwg, the drain voltage Vwd, and the source voltage Vw (write voltage) are applied to the memory cell to be written. In this example, 1.6 V is applied to the word line 81 as the gate voltage Vwg, 0.6 V is applied to the bit line 82 as the drain voltage Vwd, and 7.6 V is applied to the source line 83 as the source voltage Vw. Has been.

  As shown in FIG. 8C, when erasing a memory cell, a gate voltage Ve (erase voltage) is applied to the memory cell to be erased. In this example, 12 V is applied to the word line 81 and 0 V is applied to the bit line 82 and the source line 83 as the gate voltage Ve.

  In such a flash memory, the above-described write voltage Vw and erase voltage Ve are applied to a selected memory cell as a write pulse or erase pulse having a predetermined pulse width to shift the threshold value and Although memory and erasure are performed, due to manufacturing variations in actual products, even when a write pulse or erase pulse having the same pulse width is applied, write defects (including insufficient writing and overwriting) and erasure defects occur. There was a problem that occurred.

  Therefore, Patent Document 1 discloses a flash memory that corrects the write voltage Vw and the erase voltage Ve according to the characteristics of the memory cell. A conventional flash memory will be described with reference to FIGS.

  FIG. 9 is a configuration diagram of a conventional flash memory described in Patent Document 1. In FIG. As shown in FIG. 9, the flash memory includes a memory array 11, a data latch 12, a write circuit 13, an address register circuit 14, an X-DEC (decoder) circuit 15, a Y-DEC circuit 16, an erase circuit 17, an SA. -An AMP (sense amplifier) circuit 18, an I / O buffer 23, a power supply circuit 25, a power supply SW (switching) circuit 26, and a control circuit 27 are provided.

  The power supply circuit 25 generates a write voltage Vw and an erase voltage Ve, and the write voltage Vw and the erase voltage Ve are applied to the memory cells of the memory array 11 via the write circuit 13 and the erase circuit 17. The power supply circuit 25 includes a voltage correction circuit 40 that corrects the write voltage Vw and the erase voltage Ve.

  FIG. 10 is a circuit diagram showing a configuration of a voltage correction circuit 40 provided in a conventional flash memory. As shown in FIG. 10, the voltage correction circuit 40 includes a voltage dividing circuit 41 that divides the output voltage of the booster circuit (or step-down circuit) 31 by a series resistor R, a MOS transistor Qa connected in parallel to the series resistor R, It consists of Qb, Qc, Qd, and Qe. Control signals Sa to Se are input to the gate terminals of these MOS transistors Qa to Qe, and the write voltage Vw and the erase voltage Ve are controlled.

  FIG. 11 is a flowchart showing a method for determining the write voltage Vw in the conventional flash memory. The erase voltage Ve is also determined in the same manner as the write voltage Vw.

  First, the write voltage Vw is set to an initial voltage according to the design (step S111). Next, the write data is stored in the data latch 12 in the flash memory (step S112). Next, a write pulse is generated by the write circuit 13 and applied to the selected memory cell (step S113). Next, reading is performed by applying the read voltage Vrd (step S114). Next, it is determined whether the threshold value Vth ′ is equal to or higher than a predetermined level V1 (step S115). Next, when it is determined that the threshold value Vth ′ is not equal to or higher than the predetermined level V1, the write voltage Vw is corrected by the voltage correction circuit 40 (step S116). Then, writing (step S113), reading (step S114), and determination (step S115) are performed again.

  In this way, the occurrence of defects is reduced by increasing the write voltage Vw and the erase voltage Ve sequentially from the initial voltage for the device that cannot be written or erased with the initial voltage, thereby performing writing or erasing.

  In general, in a retry method in which a predetermined voltage is applied to a memory cell with a constant pulse width and erase is repeated until erase is completed, the number of retries increases as the write or erase voltage increases as a result of repeated write and erase. It is known. That is, if the write or erase pulse width is the same, the higher the write or erase voltage, the greater the voltage stress, so that the stressed tunnel film deteriorates.

Patent Document 2 is known as a conventional method for erasing a nonvolatile semiconductor memory. Further, Patent Literatures 3 and 4 are known as conventional nonvolatile semiconductor memory writing methods.
Japanese Patent Laid-Open No. 2000-123484 JP-A-5-234388 JP-A-5-314780 Japanese Patent Laid-Open No. 6-199598

  In the conventional flash memory of Patent Document 1, since writing / erasing is performed from the same voltage every time, there is a problem that extra voltage stress is applied before reaching the optimum writing / erasing voltage. In addition, even though the write / erase characteristics of flash memory vary from chip to chip, writing / erasing data under the same conditions for all chips can cause extra voltage stress on chips with poor write / erase characteristics. It also becomes.

  The present invention has been made to solve such problems, and an object of the present invention is to provide a nonvolatile semiconductor memory device capable of reducing voltage stress during writing / erasing.

A method of writing or erasing data in a nonvolatile semiconductor memory device according to the present invention is a method of writing or erasing data in a nonvolatile semiconductor memory device including memory cells capable of electrically writing or erasing data. A voltage pulse determining step for determining the voltage and pulse width of the write or erase voltage pulse applied to the memory cell according to the characteristics, and data relating to the voltage and pulse width of the write or erase voltage pulse determined by the voltage pulse determining step A voltage pulse storing step for storing, a voltage pulse generating step for generating the writing or erasing voltage pulse based on data on the voltage and pulse width of the writing or erasing voltage pulse stored by the voltage pulse storing step, Voltage pulse generation step And a data rewriting step of applying a write or erase voltage pulse generated thereby to the memory cell and writing or erasing data of the memory cell, wherein the voltage pulse determining step is performed by the data rewriting step. A reading step of reading data of the memory cell that has been read, a determination step of determining a threshold level of the memory cell from which data has been read by the reading step, and a threshold level of the memory cell being predetermined by the determination step and wherein the voltage pulse generating step when it is determined not to reach the level of the data rewrite and step, said reading step, said determining step and, causes repeated voltage pulses count stearyl for counting the number of repetitions And flop, by the determination step, when said threshold level of the memory cell is determined to have reached the predetermined level, the voltage pulse voltage was applied to the memory cell in the data rewriting step just performed And the number of retries by expanding the pulse width by the count number of the voltage pulse count step corresponding to the voltage pulse applied to the memory cell in the data rewrite step executed immediately before. The voltage determination step for determining the voltage and pulse width of the write or erase voltage pulse so that the pulse width corresponds to one time, and even if the count number of the voltage pulse count step reaches a predetermined number, The threshold level of the memory cell is set to a predetermined level by the determining step. Correcting the voltage of the write or erase voltage pulse generated by the pulse generation step when it is determined that it has not reached, the voltage pulse generation step corresponding to the corrected voltage of the write or erase voltage pulse; The data rewriting step, the reading step, and the determining step are repeated, and the number of repetitions corresponding to the corrected write or erase voltage pulse voltage is counted in the voltage pulse counting step. And a voltage pulse correction step for resetting the counted number corresponding to the voltage of the write or erase voltage pulse before correction .
The non-volatile semiconductor memory device of the present invention is a non-volatile semiconductor memory device that includes a memory cell that can electrically write or erase data, and is applied to the memory cell according to the characteristics of the memory cell. Alternatively, a voltage pulse determination unit that determines the voltage and pulse width of the erase voltage pulse, a voltage pulse storage unit that stores data related to the voltage and pulse width of the write or erase voltage pulse determined by the voltage pulse determination unit, and the voltage A voltage pulse generator that generates the write or erase voltage pulse based on data relating to the voltage and pulse width of the write or erase voltage pulse stored by the pulse storage unit, and the write or erase generated by the voltage pulse generator A voltage pulse is applied to the memory cell, and the memory cell data A data rewrite unit for writing or erasing, wherein the voltage pulse determining unit is a read unit for reading data of a memory cell written or erased by the data rewrite unit, and a memory from which data is read by the read unit A determination unit for determining a threshold level of the cell, and generation of a voltage pulse by the voltage pulse generation unit when the determination unit determines that the threshold level of the memory cell has not reached a predetermined level ; Repeating and repeating data writing or erasing to the memory cell by the data rewriting unit, reading from the memory cell by the reading unit, and determination of the threshold level of the memory cell by the determination unit A voltage pulse counting unit for counting the number of times, and a determination unit. Te, when the threshold level of the memory cell is determined to have reached a predetermined level, by the data rewrite unit just performed at the same voltage as the voltage of引加voltage pulse to the memory cell Yes, and corresponding to the number of retries by extending the pulse width by the number of counts in the voltage pulse count unit corresponding to the voltage pulse applied to the memory cell by the data rewrite unit executed immediately before A determining unit that determines a voltage and a pulse width of the write or erase voltage pulse so as to have a single pulse width ;
Generated by the voltage pulse generation unit when the determination unit determines that the threshold level of the memory cell has not reached a predetermined level even when the count number by the voltage pulse count unit reaches a predetermined number The write or erase voltage pulse is corrected, the data rewrite unit corresponding to the corrected write or erase voltage pulse is written to or erased from the memory cell, and the read unit from the memory cell is corrected. Reading and determination of the threshold level of the memory cell by the determination unit are repeated, and the voltage pulse count unit counts the number of repetitions corresponding to the corrected write or erase voltage pulse voltage. As shown in FIG. Characterized in that it comprises a voltage pulse correction unit that resets the count number counted by the.
According to the present invention, there is provided a nonvolatile semiconductor memory device including a memory cell in which data can be electrically written or erased, and a write or erase voltage to be applied to the memory cell is determined according to characteristics of the memory cell. A voltage determining unit, a voltage storage unit storing data related to the write or erase voltage determined by the voltage determining unit, and the writing or erasing based on data related to the write or erase voltage stored by the voltage storage unit A voltage generation unit that generates a voltage; and a data rewriting unit that applies a write or erase voltage generated by the voltage generation unit to the memory cell and writes or erases data in the memory cell.
Thereby, the voltage stress at the time of writing / erasing of the memory cell can be reduced.

  In the above-described nonvolatile semiconductor memory device, the voltage determination unit includes a reading unit that reads data of a memory cell written or erased by the data rewriting unit, and a threshold of the memory cell from which the data is read by the reading unit. A voltage applied to the memory cell by the data rewriting unit when the threshold level of the memory cell has reached a predetermined level by a determination unit that determines a value level; And a determination unit that determines that the voltage is the write or erase voltage. Thereby, the voltage stress at the time of writing / erasing the memory cell can be further reduced.

  In the above-described nonvolatile semiconductor memory device, when the determination unit determines that the threshold level of the memory cell has not reached a predetermined level, the write or erase voltage generated by the voltage generation unit is A voltage correction unit for correction may be further provided, and the data rewriting unit may apply the voltage corrected by the voltage correction unit to the memory cell. Thereby, the voltage stress at the time of writing / erasing of the memory cell can be further reduced.

  In the above nonvolatile semiconductor memory device, the voltage generator boosts or steps down a power supply voltage based on an input clock and outputs the write voltage or erase voltage, and the boost or step down circuit A comparator that compares the output voltage with a reference voltage, and an oscillator that controls a clock input to the step-up or step-down circuit based on the output of the comparator. Thereby, the voltage stress at the time of writing / erasing of the memory cell can be effectively reduced.

  In the above-described nonvolatile semiconductor memory device, the voltage correction unit includes: a voltage dividing circuit including a plurality of resistors that divide the voltage generated by the voltage generation unit; and a switch that switches resistance values of the plurality of resistors. The data relating to the write or erase voltage stored in the voltage storage unit may be data for turning on and off the switch. Thereby, the voltage stress at the time of writing / erasing the memory cell can be efficiently reduced.

  In the above-described nonvolatile semiconductor memory device, the data related to the write or erase voltage stored by the voltage storage unit has the number of retries that repeats the application of the write or erase voltage to the memory cell, and the data rewrite unit The write or erase voltage may be applied for a period corresponding to the number of retries. Thereby, the voltage stress at the time of writing / erasing the memory cell can be further reduced.

  In the above-described nonvolatile semiconductor memory device, the voltage storage unit may be a partial region of a memory cell array including the memory cells. Thereby, the voltage stress at the time of writing / erasing the memory cell can be efficiently reduced.

  A method of writing or erasing data in a nonvolatile semiconductor memory device according to the present invention is a method of writing or erasing data in a nonvolatile semiconductor memory device including a memory cell capable of electrically writing or erasing data. Based on the characteristics, the step of determining the write or erase voltage to be applied to the memory cell, the step of storing the data related to the determined write or erase voltage, and the stored data related to the write or erase voltage And a step of generating the write or erase voltage and a step of applying the generated write or erase voltage to the memory cell to write or erase data in the memory cell. Thereby, the voltage stress at the time of writing / erasing of the memory cell can be reduced.

  In the data writing or erasing method of the nonvolatile semiconductor memory device described above, the step of determining the writing or erasing voltage includes reading the data of the memory cell that has been written or erased by the step of writing or erasing the data of the memory cell. And when determining that the threshold level of the memory cell has reached a predetermined level by determining the threshold level of the read memory cell, and determining the threshold level of the memory cell, Determining the voltage applied to the memory cell by the writing or erasing step as the writing or erasing voltage. Thereby, the voltage stress at the time of writing / erasing the memory cell can be further reduced.

  In the above-described data writing or erasing method of the nonvolatile semiconductor memory device, the step of generating the voltage when the determination step determines that the threshold level of the memory cell has not reached a predetermined level. The step of correcting the write or erase voltage generated by the step of applying the voltage corrected by the step of correcting the voltage to the memory cell. There may be. Thereby, the voltage stress at the time of writing / erasing of the memory cell can be further reduced.

  According to the present invention, it is possible to provide a nonvolatile semiconductor memory device that can reduce voltage stress during writing / erasing.

Reference technology First, with reference to FIG. 1, the configuration of the flash memory. As shown in FIG. 1, the flash memory includes a memory array 11 as a storage element. The memory array 11 is composed of a plurality of memory cells as in FIG.

  The flash memory also holds a data latch 12 that holds externally input write data, a write circuit 13 that writes to the memory array 11 based on the data held in the data latch 12, and an address signal. Address register circuit 14, X-DEC (decoder) circuit 15 for selecting one word line corresponding to the X address taken into the address register circuit 14 from the word lines in the memory array 11, and a block at the time of erasing An erase circuit 17 for selecting (mat) and the like, an SA-AMP (sense amplifier) circuit 18 for amplifying and outputting data read from the memory array 11, and a source line of the memory array 11 at the time of writing or the like One bit corresponding to the Y address taken into the S-DEC circuit 19 and the address register circuit 14. And a Y-SELE (selection) circuit 20 for selecting the door line. The write circuit 13 (data writing unit) and the erasing circuit 17 (data erasing unit) apply the write voltage Vw or the erase voltage Ve output from the power supply circuit 25 to the memory cell to write or erase the memory cell. It operates as a data rewriting unit to be performed.

  Further, the flash memory includes a control circuit 27 that converts an external control signal into a control signal to each circuit in the flash memory, an I / O buffer 23 that inputs and outputs address signals and data signals, and a charge pump. Such a booster and step-down circuit, and a power supply circuit 25 that generates a voltage required inside the chip such as a write voltage Vw, an erase voltage Ve, and a read voltage Vrd based on a power supply potential Vdd supplied from the outside, and the operation of the memory A power supply SW (switching) circuit 26 that selects a desired voltage from these voltages according to the state and supplies the selected voltage to the memory array 11 is provided.

  The control circuit 27 operates as a voltage determining unit that determines the write voltage Vw or the erase voltage Ve to be applied to the memory cell according to the procedure described later with reference to FIGS. For example, the voltage determination unit includes a reading unit (not shown) that reads data from a memory cell, a determination unit (not shown) that determines a threshold level of the memory cell from which the data has been read, A determination unit (not shown) that determines that the voltage when the predetermined level is reached is the write voltage Vw or the erase voltage Ve; The power supply circuit 25 is provided with a voltage generation circuit 30 (voltage generation unit) and a voltage correction circuit 40 (voltage correction unit) described later. The voltage correction circuit is generated by the voltage generation circuit 30 and controlled by the control circuit 27. The write voltage Vw or the erase voltage Ve corrected by 40 is applied to the memory array 11.

Et al is, EXTRA region 21 is provided in the memory array 11. The EXTRA area 21 is an area for storing information such as tests and security provided in the memory cell area in addition to the microcomputer program storage area (hereinafter referred to as user area), and is arranged in a block different from the user area. The EXTRA area 21 stores data indicating an initial value of the write / erase voltage as a voltage storage unit.

  The data indicating the initial value of the write / erase voltage is, for example, a correction code of a voltage correction circuit 40 to be described later, but any data format can be used as long as a desired write voltage Vw or erase voltage Ve can be generated by the voltage correction circuit 40. But you can. Note that the data indicating the initial value of the write / erase voltage is not limited to the EXTRA region 21 in the memory array 11 and may be stored in other regions, other storage elements, or the like.

Next, with reference to FIG. 2, description will be given of a configuration of electrostatic pressure generation circuit and the voltage compensation circuit. The voltage generation circuit 30 and the voltage correction circuit 40 are circuits provided in the power supply circuit 25 described above. The voltage generation circuit 30 is a circuit that generates the write voltage Vw or the erase voltage Ve based on the reference voltage Vref, and the voltage correction circuit 40 is the write voltage Vw or the erase voltage output from the voltage generation circuit 30 based on the control signal. This is a circuit for correcting the voltage Ve.

  As shown in FIG. 2, the voltage generation circuit 30 generates a boost circuit (or step-down circuit) 31 such as a charge pump that generates a voltage in accordance with an input clock, a reference voltage Vref, and an output voltage of the boost circuit 31. A comparator 33 for comparison and an oscillator 32 for generating a clock based on the output of the comparator 33 are provided. By providing the comparator 33 and the oscillator 32, the clock input to the booster circuit 31 becomes variable with respect to the reference voltage Vref, the output voltage of the booster circuit 31 can be controlled, and a stable voltage can be generated with high accuracy. Can do. The comparator 33 refers to the output of the booster circuit 31 via the resistor R, but may refer to the output of the booster circuit 31 directly or via a plurality of resistors R.

  As shown in FIG. 2, the voltage correction circuit 40 divides the voltage output from the booster circuit 31 by a series-shaped resistor (or diode) R, and the series resistor constituting the voltage divider circuit 41. MOS transistors Qa, Qb, Qc, Qd, and Qe connected in parallel with some of R are provided, and correction codes Sa to Se, which are control signals, are respectively provided at the gate terminals of these MOS transistors Qa to Qe. Entered. The correction codes Sa to Se are signals output from, for example, a switching control register in the control circuit 27. When the MOS transistors Qa to Qe are turned on or off according to the correction codes Sa to Se, the voltage dividing ratio by the voltage dividing circuit 41 is set, and the voltage corresponding to the voltage dividing ratio is set to the write voltage Vw (or erase). Is output as voltage Ve). That is, the write voltage Vw and the erase voltage Ve can be made variable by the correction codes Sa to Se.

  For example, when any of the MOS transistors Qa to Qe is changed from the on state to the off state, the write voltage Vw (or the erase voltage Ve) becomes a higher voltage. When any of the MOS transistors Qa to Qe is turned on from the off state, the write voltage Vw (or the erase voltage Ve) becomes a lower voltage. In this example, the five resistors R are controlled by the MOS transistors Qa to Qe. However, the present invention is not limited to this, and any number of resistors may be used.

Next, with reference to FIGS. 3 and 4, it will be described a method of erasing data in main Moriseru. FIG. 3 is a flowchart showing a procedure for erasing a memory cell, and FIG. 4 is a timing chart showing signals at the time of erasing the memory cell. This erasing of the memory cell is performed by the circuits of FIGS.

  As shown in FIG. 3, first, the erase voltage Ve is initially set (step S301). The control circuit 27 reads the erase voltage initial value code of the EXTRA area 21, sets this code in the switching control register of the flash controller, and generates the correction code of the voltage correction circuit 40 corresponding to the register value. The voltage correction circuit 40 sets the erase voltage Ve output from the power supply circuit 25 to a desired initial value according to the correction code. In the first erase, since the erase voltage initial value code is not written in the EXTRA region 21, the erase voltage Ve may be an arbitrary voltage. For example, a low voltage may be set as the initial value. .

  Next, an erase pulse is applied to erase the memory cell (step S302). The erase circuit 17 selects a block to be erased from the memory array 11 according to an instruction from the control circuit 27 and the like, generates an erase pulse, and applies the erase pulse to the selected memory cell.

  Specifically, as shown in FIG. 4, an erase mode signal of the power supply potential Vdd is input to the power supply circuit 25 and the like, and the power supply circuit 25 outputs an erase voltage Ve. When the erase circuit 17 outputs an erase pulse of the power supply potential Vdd, the erase voltage Ve is applied to the gate of the memory cell with the same width as the erase pulse. At this time, the source and drain of the memory cell are 0V. Thus, the data in the desired memory cell is erased.

  Next, the erased memory cell is read (step S303). A memory cell to be read is selected by the X-DEC circuit 15 or the Y-SELE circuit 20, and a read voltage Vrd (for example, 1.0 V) of a predetermined level is applied to the word line of the memory array 11 to read the SA-AMP circuit 18. Is amplified to a predetermined level and output.

  Next, it is determined whether or not the read result has reached a desired erase level (step S304). The control circuit 27 determines whether the threshold value of the read erased bit is equal to or lower than a predetermined level.

  If it is determined in step S304 that the read result has not reached the desired erase level, voltage correction is performed (step S305). The control circuit 27 changes the switching control register, and the corresponding correction code is also changed. The voltage correction circuit 40 corrects the erase voltage Ve according to the correction code. Then, the erase pulse is applied again using the corrected erase voltage Ve (step S302). Further, reading (step S303) and reading result determination are performed (step S304).

  If it is determined in step S304 that the read result has reached the desired erase level, the voltage correction code at that time is written in the EXTRA area 21 as the erase voltage initial value code (step S306). In this way, the memory cell is erased without causing an erase failure.

Next, with reference to FIGS. 5 and 6, it will be described writing method of data main Moriseru. FIG. 5 is a flowchart showing a procedure for programming a memory cell, and FIG. 6 is a timing chart showing signals at the time of programming the memory cell. This memory cell is written by the circuits shown in FIGS. 5 and 6 is the same as or similar to the erasing method shown in FIGS. 3 and 4, and description thereof will be omitted as appropriate.

  As shown in FIG. 5, first, the write voltage Vw is set (step S501). The control circuit 27 reads the write voltage initial value code written in the EXTRA area 21 and generates a correction code, and the voltage correction circuit 40 sets the write voltage Vw to a desired initial value according to the correction code. .

  Next, a write pulse is applied to write the memory cell (step S502). The control circuit 27 stores write data in the data latch 12 in the flash memory, selects a memory cell to be written by the X-DEC circuit 15 or the Y-SELE circuit 20, and the write circuit 13 is stored in the data latch 12. A write pulse is generated according to the written data, and the write pulse is applied to the selected memory cell.

  Specifically, as shown in FIG. 6, the write mode signal of the power supply potential Vdd is input to the power supply circuit 25 and the power supply circuit 25 outputs the write voltage Vw. At this time, Vwg is applied to the gate of the memory cell and Vwd is applied to the drain of the memory cell by the X-DEC circuit 15 and the Y-SELE circuit 20. When the write circuit 13 outputs a write pulse of the power supply potential Vdd, the write voltage Vw is applied to the source of the memory cell with the same width as the write pulse. Thus, data is written into a desired memory cell.

  Next, the written memory cell is read (step S503), and it is determined whether the read result has reached a desired write level (step S504). The control circuit 27 determines whether the threshold value of the read and written bit is equal to or higher than a predetermined level.

  If it is determined in step S504 that the read result does not reach the desired write level, voltage correction is performed (step S505). Then, the write pulse is applied again using the corrected write voltage Vw (step S502). Further, reading (step S503) and determination of the reading result are performed (step S504).

  If it is determined in step S504 that the read result has reached the desired write level, the voltage correction code at that time is written in the EXTRA area 21 as the write voltage initial value code (step S506). In this way, the memory cell is erased without causing an erase failure.

  In this manner, the erase voltage Ve / write voltage Vw is corrected in order from the initial value until the memory cell reaches a predetermined erase / write level, and the voltage when the memory cell reaches the predetermined erase / write level. The correction code of the correction circuit is written in the EXTRA area 21. When the next erasing / writing is initially set, the correction code written in the EXTRA area 21 is read out and the erasing / writing is performed with the optimum erasing voltage Ve / writing voltage Vw. It can be carried out.

  That is, in the prior art, the initial value of the erase voltage Ve / write voltage Vw at the time of erasing / writing is always set to a constant voltage, but in this embodiment, the correction code when the previous erasing / writing was performed In order to set the correction code as the initial value from the next time, the erase is performed without applying extra voltage stress applied to the memory cell until the necessary applied voltage is reached in the second and subsequent erase / writes. / Write can be performed. Therefore, deterioration of the memory cell can be reduced and the number of rewrites can be increased. Further, since unnecessary erasing / writing is not performed, the erasing / writing time can be shortened.

Form state of implementation of the invention below with reference to the flowchart of FIG. 7 will be described a method of erasing a memory cell according to the shape condition of the present invention. The configuration of the flash memory and voltage correction circuit is the same as that shown in FIGS. Further, steps S701 to S706 in FIG. 7 are the same as or similar to steps S301 to S306 in FIG.

  As shown in FIG. 7, first, the erase voltage Ve is initially set (step S701), and the erase pulse width is set (step S707). The control circuit 27 reads the number of retries in the EXTRA area 21 and sets the erase pulse width defined by the number of retries in the erase circuit 17.

  Next, an erase pulse is applied to erase the memory cell (step S702). The erase circuit 17 generates an erase pulse having a set pulse width and applies the erase pulse to the selected memory cell.

  Next, the erased memory cell is read (step S703), and it is determined whether the read result has reached a desired erase level (step S704).

  If it is determined in step S704 that the read result has not reached the desired erase level, the number of retries is determined (step S708). For example, the control circuit 27 determines whether the number of retries is 10 or more.

  If it is determined in step S708 that the number of retries is not 10 or more, the number of retries is incremented, the erase pulse is applied again (step S702), read (step S703), and the read result is determined (step). S704).

  If it is determined in step S708 that the number of retries is 10 or more, voltage correction is performed (step S705). Then, the erase pulse is applied again using the corrected erase voltage Ve (step S702). Further, reading (step S703) and reading result determination are performed (step S704).

  If it is determined in step S704 that the read result has reached the desired erase level, the voltage correction code at that time is written in the EXTRA area 21 as the erase voltage initial value code (step S706). Further, the number of retries at that time is written in the EXTRA area 21 (step S709). In this way, the memory cell is erased without causing an erase failure. Note that the memory cell can be written by the same method.

  As described above, in this embodiment, a retry method is used in which a predetermined voltage is applied to the memory cell with a constant pulse width for writing / erasing, and writing / erasing is repeatedly performed until the writing / erasing is completed. For example, conventionally, when the number of retries is set to 10, the setup for applying the erase voltage Ve and the write voltage Vw to the gate and the source of the memory cell every time is required for the number of retries. Then, by writing the optimum voltage value and the number of retries in the EXTRA area 21, the erase / write pulse corresponding to the number of retries is made one pulse to perform erasing / writing.

  For example, if the erase pulse is 2 ms and the read decision is passed with 5 retries, the next erase operation can be performed by erasing the memory cell once with the 10 ms erase pulse, and the erase pulse for 4 times can be obtained. Since the setup time can be shortened, the erase time (write time) is shortened.

It is a block diagram showing a configuration example of a flash memory circuit. Is a circuit diagram showing an example of configuration of a power supply circuit provided in the flash memory. Is a flowchart illustrating an example of the erasing method in flash memory. Is a timing chart at the time of the erase pulse is applied in flash memory. Is a flowchart illustrating an example of a writing method in the flash memory. It is a timing chart at the time of writing pulse applied in flash memory. 3 is a flowchart showing an example of an erasing voltage determination procedure in the flash memory according to the present invention. It is a figure which shows the voltage arrangement | positioning at the time of reading of the flash memory cell, writing, and erasing. It is a block diagram which shows the structural example of the conventional flash memory circuit part. It is a circuit diagram which shows the structural example of the voltage correction circuit provided in the conventional flash memory. It is a flowchart which shows an example of the determination procedure of the write voltage in the conventional flash memory.

Explanation of symbols

11 memory array 12 data latch 13 write circuit 14 address register circuit 15 X-DEC circuit 16 Y-DEC circuit 17 erase circuit 18 SA-AMP circuit 19 S-DEC circuit 20 Y-SELE circuit 21 EXTRA area 23 I / O buffer 25 Power supply circuit 26 Power supply SW circuit 27 Control circuit

Claims (2)

A method of writing or erasing data in a nonvolatile semiconductor memory device having a memory cell capable of electrically writing or erasing data,
A voltage pulse determining step for determining a voltage and a pulse width of a write or erase voltage pulse applied to the memory cell according to the characteristics of the memory cell;
A voltage pulse storing step for storing data relating to the voltage and pulse width of the write or erase voltage pulse determined by the voltage pulse determining step;
A voltage pulse generating step for generating the write or erase voltage pulse based on data relating to the voltage and pulse width of the write or erase voltage pulse stored by the voltage pulse storing step;
Applying a write or erase voltage pulse generated by the voltage pulse generating step to the memory cell, and writing or erasing data of the memory cell, and a data rewriting step,
The voltage pulse determining step includes
A read step of reading data of the memory cell written or erased by the data rewriting step;
A determination step of determining a threshold level of the memory cell from which data has been read by the reading step;
When the determination step determines that the threshold level of the memory cell has not reached a predetermined level, the voltage pulse generation step , the data rewrite step, the read step, and the determination step are performed. A voltage pulse counting step for repeating and counting the number of repetitions;
When the determination step determines that the threshold level of the memory cell has reached a predetermined level, the same voltage as the voltage of the voltage pulse applied to the memory cell in the data rewriting step executed immediately before And corresponding to the number of retries by extending the pulse width by the count number of the voltage pulse count step corresponding to the voltage pulse applied to the memory cell in the data rewrite step executed immediately before. A voltage determining step for determining a voltage and a pulse width of the write or erase voltage pulse so as to have a single pulse width ;
Generated by the pulse generation step when the threshold level of the memory cell has not reached the predetermined level even if the count number of the voltage pulse count step reaches a predetermined number. Correcting the voltage of the write or erase voltage pulse to be performed, the voltage pulse generating step corresponding to the corrected voltage of the write or erase voltage pulse, the data rewriting step, the reading step, the determination step, And counting in accordance with the voltage of the write or erase voltage pulse before correction so that the number of repetitions corresponding to the voltage of the corrected write or erase voltage pulse is counted in the voltage pulse counting step. voltage pulse to reset the count number is Data writing or erasing method for a nonvolatile semiconductor memory device characterized by comprising a correction step. A non-volatile semiconductor memory device comprising memory cells capable of electrically writing or erasing data,
A voltage pulse determining unit that determines a voltage and a pulse width of a write or erase voltage pulse applied to the memory cell according to the characteristics of the memory cell;
A voltage pulse storage unit for storing data relating to the voltage and pulse width of the write or erase voltage pulse determined by the voltage pulse determination unit;
A voltage pulse generator for generating the write or erase voltage pulse based on the voltage and pulse width data of the write or erase voltage pulse stored by the voltage pulse storage unit;
A data rewrite unit that applies a write or erase voltage pulse generated by the voltage pulse generator to the memory cell and writes or erases data in the memory cell, and
The voltage pulse determination unit is
A read unit for reading data of a memory cell written or erased by the data rewrite unit;
A determination unit for determining a threshold level of a memory cell from which data is read by the reading unit;
When the determination unit determines that the threshold level of the memory cell has not reached a predetermined level, voltage pulse generation by the voltage pulse generation unit and data writing to the memory cell by the data rewriting unit or A voltage pulse counting unit that repeats erasing, reading from the memory cell by the reading unit, and determining the threshold level of the memory cell by the determining unit and counting the number of repetitions;
When the determination unit determines that the threshold level of the memory cell has reached a predetermined level, the voltage of the voltage pulse applied to the memory cell by the data rewriting unit executed immediately before By extending the pulse width by the count number in the voltage pulse count unit corresponding to the voltage pulse applied to the memory cell by the data rewrite unit executed immediately before, the same voltage, and the number of retries A determination unit for determining a voltage and a pulse width of the write or erase voltage pulse so as to have a single pulse width corresponding to
Generated by the voltage pulse generation unit when the determination unit determines that the threshold level of the memory cell has not reached a predetermined level even when the count number by the voltage pulse count unit reaches a predetermined number The write or erase voltage pulse is corrected, the data rewrite unit corresponding to the corrected write or erase voltage pulse is written to or erased from the memory cell, and the read unit from the memory cell is corrected. Reading and determination of the threshold level of the memory cell by the determination unit are repeated, and the voltage pulse count unit counts the number of repetitions corresponding to the corrected write or erase voltage pulse voltage. As shown in FIG. To the non-volatile semiconductor memory device, characterized in that it comprises a voltage pulse correction unit for resetting the counted number of counts, the.

Images