KR0172377B1 - Non-volatile memory - Google Patents

Abstract

1. The technical field to which the invention described in the claims belongs:

Multistate Nonvolatile Semiconductor Memory

2. The technical problem the invention is trying to solve:

Expanding the storage capacity of a memory cell provides a multi-state nonvolatile semiconductor memory that can simplify the circuit around the memory cell array with water.

3. Summary of the Solution of the Invention:

The improved memory includes parallel bit lines; Having a plurality of strings formed in a semiconductor substrate and arranged in a matrix, each memory cell in the string having a multi-state memory cell array configured to have control gates, floating gates, and source and drain regions for storage of multi-state data; Control the memory cells connected to the gates and upper word lines of the first and second select transistors, select strings belonging to the same group and at least one word line in each operation mode, and control the memory cells connected to the selected word lines. And control means for commonly applying a corresponding voltage according to each operation mode to the gate.

4. Important uses of the invention:

It is used as a multi-state semiconductor memory.

Description

Multi-State Nonvolatile Memory and Its Driving Method

1 is a circuit diagram related to memory cells of a flash memory (Flash-EEFROM), which stores one bit of information per memory cell.

FIG. 2 is a circuit diagram of a specific embodiment derived in accordance with the present invention, wherein a memory cell related circuit diagram of a flash memory stores multi-bit information per memory cell.

FIG. 3 is a diagram illustrating a voltage relationship between a threshold voltage distribution and a bit line of a memory according to FIG. 2 without any particular intention, except that the embodiments of the present invention are described in detail.

4, 5, 6, and 7 illustrate voltages appearing on the bit lines of a memory cell in comparison with reference voltages when 11, 10, 1, 0 states are programmed in the memory according to FIG. As shown, the figure for explaining the state change of the memory cell step by step.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile memory, and more particularly, to an apparatus and a driving method thereof for providing a multi-state nonvolatile semiconductor memory storing a plurality of bit information in one memory cell.

In general, the nonvolatile semiconductor memory is divided into mask ROM, EPROM, EEPROM, and EEPROM in this field. Flash Ipyrom, which has the ability to change and flash erased data, has recently been in the spotlight as permanent memory in personal computers.

In such a conventional nonvolatile semiconductor memory, the memory cell can take only one of two information storage states, i.e., on or off. One combination of on or off defines one bit of information. Thus, N independent memory cells are required to store N (where N is a natural number of two or more) bits of data in such a conventional memory element. If an increase in the number of data bits to be stored in a memory device having a single bit memory cell is required, the number of memory cells must be increased by that much.

On the other hand, the information stored in a typical single bit memory cell is determined according to the state in which the memory cell is programmed (to input desired information into the memory cell). The information storage state of the memory cell is determined according to a difference of a threshold voltage (the minimum voltage that must be applied between the gate terminal and the source terminal of the transistor in order for the cell transistor to be turned on). In the case of mask ROM, the differential of the threshold voltage of the cell transistor is achieved by programming during the fabrication process using ion implantation techniques. In contrast, in the case of EPROM, EEPROM, Flash-EEPROM, etc., a floating gate in a memory cell (usually two gates of one memory cell transistor) forms an upper and lower layers on the drain source channel region. The threshold voltage of each memory cell is changed by differentiating the amount of charge stored in the upper layer, called the control gate, and stored in the charge accumulation portion surrounded by the insulating material between the control gate and the channel region. The stored information states are thus distinguished.

In order to read the information stored in each memory cell in the memory device, it is necessary to check the storage state of the programmed memory cells. To this end, a decoder circuit selects and reads a desired memory cell and applies signals to a circuit related to the memory cell. As a result, a signal of a different current or voltage in the storage state information of the memory cell is obtained on the bit line. By measuring the current or voltage signal thus obtained, it is possible to distinguish the state information stored in the memory cell.

The structure of a memory cell array of these memory devices is divided into NOR-type and NAND-type according to the form in which memory cells are connected to a bit line. In the NOR-type, each memory cell is connected between a bit line and a ground line. In the NAND-type, a plurality of memory cells are connected in series between a bit line and a ground line. Here, the memory cells connected in series to the bit line and the selection transistors (transistors connected between the serially connected memory cells and the bit line and between the serially connected memory cells and the ground line) are combined. In the field, it is called a string. The transistors in the selected string are turned on to read the state information stored in the NAND-type memory device.

In addition, the control gate terminal of the memory cells that are not selected in the string is provided with a voltage higher than the voltage applied to the control gate terminal of the selected memory cell. Accordingly, the unselected memory cells have a lower equivalent resistance value than the selected memory cell, and the current flowing from the corresponding bit line to the string depends on the state of information stored in the selected memory cell in the string. The voltage or current appearing on the bit line in accordance with the information state stored in the selected memory cell is sensed by a sense circuit (commonly referred to as a sense amplifier).

As one of the representative techniques for such memory elements in the related art, in particular, a memory cell related circuit of a flash memory configured to be NAND type and storing a single bit of information per one memory cell, an understanding of the configuration of the present invention will be described later. In order to further aid the present invention, it is shown as FIG. Referring to FIG. 1, one entire string including select transistors 2 and 8 and memory cell transistors 3,4-7 connected in series between a string select line (SSL) and a ground select line (GSL) is a bit. It is connected to line 9. Here, FIG. 1 illustrates one string and a circuit related thereto for convenience of illustration, but in practice, a memory device has a form in which a plurality of strings are connected to a plurality of bit lines to increase storage capacity. Therefore, in one chip, the memory cell transistors in the string together with the memory cell transistors in all other strings constitute a memory cell array, in which the transistors are cross-arranged in a matrix of rows and columns. In FIG. 1, the row decoder and program controller 1 is configured to drive a selected row and a signal for driving a selected transistor on the string select line SSL, the ground select line GSL, and the word lines WL1, WL2-WL16. Each row decoded signal for selection is provided. Thus, transistors 2, 8, 3, 4-7 in the string are controlled on or off in response to the signals provided to gate terminals and control gate terminals. The drain-source passage of the deflation type transistor N1 is connected in series to the bit line 9. The gate of the D-type transistor N1 is a control signal that is maintained at H state of about 5 volts during the program Is connected to. The transistor N1 is a high voltage device used to accelerate the read operation by separating the capacitance of the bit line 9 from the capacitance of the node 10 of the page buffer 12 during the data read operation. The MOS transistor N2, which receives the control signal BLSHF through a gate terminal, has a drain-source path connected to the bit line 9 to protect the page buffer 12 from high voltage. The page buffer 12, also called a data register and sense amplifier, consists of the elements connected to the node 10. The control signal DCB is applied to the gate of the transistor N3 in the page buffer 12 to discharge the charge on the bit line after the end of the erase and program operations and to reset the data in the data register immediately before the read operation. It is connected. In addition, the gate of the transistor N4 is connected to the control line SBL in the H state during the program. Node 15 of the bit line is connected to a latch that constitutes a data raster called a page buffer in a narrow sense. Each of the latches 13 and 14 is composed of two inverters connected alternately. The latch is not only a page buffer for temporarily storing data to temporarily write data to memory cells at a time through each corresponding bit line in a program operation, but also as a verification detector for determining whether a program is performed well in a program verifying operation. In addition, the read operation functions as a sensing amplifier for sensing and amplifying data on the bit lines read from the memory cells. The bit line selection related transistor used in a program operation or a read operation includes a transistor N9 that receives a selection signal Y1 as a gate in addition to the transistors N1 and N2. In addition to the transistors N3 and N4 for setting transistors that determine the initial value of the latch, transistors N7 and N8 are included. The transistor P3 is a device whose gate is connected to the node 11 and supplies a constant current on the node 10 of the bit line. The constant current unit 33 for providing a constant current to the node 11 includes a transistor N5 for receiving a reference voltage Vref as a gate, a transistor P1 for receiving a control signal as a gate, a transistor P2 having a gate connected to the node 11, and a gate of the control signal. Is composed of a transistor N6 to receive. As described above, since the memory having the configuration of FIG. 1 can store only a single bit of information per memory cell, the number of memory cells should be increased correspondingly when more information is stored in the memory. Therefore, the size of the chip is increased in proportion to the storage information capacity.

Thus, a series of attempts have been made in the art to increase the storage information capacity of a memory device without increasing the size of the chip. One such attempt is a technique for storing more than two bits of information per memory cell. Typically, one memory cell stores one bit of information, but for example, when two bits of information are stored in one memory cell, the state of the memory cell will be one of 0, 1, 10, and 11. In this case, the memory device can store twice the amount of information with the same number of memory cells as compared with the memory device that stores only one bit of information in one memory cell. The multi-state memory device in the case of storing 2 bins as described above is implemented by programming the threshold voltages of the memory cells to be programmed as one of four different values. Therefore, if the multi-state memory stores two bits per memory cell, the amount of information corresponding to the single-bit memory can be stored even with a memory cell corresponding to half of the single-bit memory, thereby reducing the chip size. In addition, increasing the number of bits stored per memory cell will increase the amount of storage as compared to single-bit memory.

This implementation of multistate memory is advantageous in the NOR-type memory structure described above. This is because the NOR-type is determined only by the state of the selected memory cell in the amount of current flowing through the memory cell during a read operation. Therefore, in the memory having such a structure, a word line connected to a selected memory cell is turned on to read information of a memory cell, and a current or bit flowing in the bit line by selecting a bit line to which the selected memory cell is connected. The voltage induced in the line can be processed using one or more branch circuits. Therefore, such NOR-type memory has the advantage of being easy to apply to multi-state memory and fast in operation. However, importantly, the size of the entire memory cell array is larger than that of the NAND-type memory due to the constraint that each memory cell must be connected between the bit line and the ground line.

On the other hand, in the NAND-type memory device, the implementation of the multi-state memory is more difficult than the NOR-type described above. Because a plurality of memory cells are connected in series between the bit line and the ground line, the amount of current flowing in the selected string is affected by not only the information stored in the selected memory cell but also the state of the unselected memory cells in the same string. Because I receive. Thus, the current sensing (Current Sensing) technique used in the NOR-type cannot be used in such a NAND-type structure. As described above, in the NAND-type memory, the density of memory cells is better than that of the NOR-type memory. However, the above-mentioned difficulties exist, and the application thereof is excluded from the multi-state technology that stores a plurality of bits of information in one memory cell. come.

Thus, it would be very desirable to be able to use the multistate memory technology that has been applied to the NOR-type in NAND-type memory structures. In this case, since the number of memory cells is reduced and the density of memory cells is improved, a very compact memory chip can be provided.

Accordingly, an object of the present invention is to provide a multi-state nonvolatile semiconductor memory capable of solving the above-mentioned conventional problems.

Another object of the present invention is to provide a multi-state nonvolatile semiconductor die and a method of driving the same, which can apply a multi-state data storage technology to a NAND-type memory structure.

It is still another object of the present invention to provide a multi-state nonvolatile semiconductor memory which can expand the storage capacity of a memory cell and also simplify the circuit around the memory cell array.

It is still another object of the present invention to reduce the number of memory cells and improve the degree of integration by differentiating ion implantation in the manufacture of each memory cell or multiple differentiating the amount of charge programmed in the floating gate of each memory cell. A nonvolatile semiconductor memory and its driving method are provided.

In accordance with the above objects, the present invention provides a device comprising: parallel bit lines formed on a semiconductor substrate; A plurality of strings formed in the semiconductor substrate and arranged in a matrix form, each string having a plurality of serially connected memory cells connected to a corresponding bit line, and each memory cell having a control gate and a floating gate for storing multi-state data. And a multi-state nonvolatile semiconductor memory device having a multi-state memory cell array configured to have source and drain regions formed spaced apart through a channel in a semiconductor substrate. Each of the strings is positioned between a source of a first selection transistor having a drain connected to a corresponding bit line among the bit lines and a drain of a second selection transistor having a source connected to a common source line. In addition, control means for selecting strings belonging to the same group and at least one word line in each operation mode, and applying a corresponding voltage according to each operation mode to a control gate of memory cells connected to the selected word line in common. Is connected to the gate and the word lines of the first and second selection transistors.

To program data into one of a plurality of states in a memory cell of the multi-state memory cell array, read the programmed data, erase the programmed data according to a predetermined purpose, and perform verification according to each operation. The multi-state nonvolatile semiconductor memory device of the present invention is sequentially connected every two bit lines to alternately access selected memory cells of strings belonging to one same group and strings belonging to another same group in each operation mode. And simultaneously selecting bit lines belonging to the same group, selecting bit lines belonging to the same group as the other, and unselected bit lines belonging to the same group as the predetermined voltage in response to an applied selection signal. Connect the level of the selected bitline to each motion mode. Bit line level control means for correspondingly controlling; Multi-state reference voltage generating means for selecting one of the preset reference voltages differently according to each operation mode and logic level of the applied data and providing the same through an output terminal; The bit line level control means and the multi-state reference voltage generating means; The program data is temporarily stored and connected to the bit line level control means and the multi-state reference voltage generating means, respectively, to temporarily write data into the memory cells through corresponding bit lines in a program operation among the operation modes. And a sensing and storing means for latching the sensed read data by comparing the voltage on the bit lines derived from the memory cells selected in the read operation with the multi-level reference voltage to determine whether the program has been sufficiently performed in the verify operation.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings. It should be noted that the same reference numerals in the figures represent the same elements or signals wherever possible.

In the following description, numerous specific details such as memory cells and the structure of the bit lines, voltage values, circuit configurations and components are shown to provide a more general understanding of the present invention. It will be apparent to those skilled in the art that the present invention may be practiced without these specific details.

The term memory cell or memory transistor as used herein refers to a multistate floating gate MOS FET having a source, a drain, a floating gate and a control gate. The term program means the writing of data into selected memory transistors. The term charging is defined as charging a predetermined voltage to a channel of each memory transistor constituting a NAND-structured memory cell and a junction capacitor of a source and a drain thereof.

The same group is used to refer to strings connected to odd or even bit lines in a memory cell array when there are a plurality of bit lines in parallel.

The EEPROM of the present invention is fabricated using a CMOS fabrication technique on the same chip, and N-channel and P-channel transistors having a threshold voltage of a set volt are used.

Figure 2 illustrates a memory cell related circuit of a multi-state nonvolatile memory, in particular NAND-type EEPROM. However, the multi-state nonvolatile semiconductor memory of the present invention is not limited to the NAND-type EEPROM shown in FIG. 2 but can also be applied to NOR-type EEPROM, EPROM, EEPROM, MASK ROM, and the like. Referring to FIG. 2, each memory cell 3A-7A, 3B-7B, which stores two bits of information per cell in a floating gate, is shown as NAND-type. The memory cells 3A-7A and 3B-7B each include first and second select transistors 2A, respectively connected to SSL and GSL similarly to the circuit of FIG. 1 to form a cell string having a basic structure. 2B) and (8A, 8B) are connected in series. The bit lines BL1 and BL2 are connected to the memory cells of each string through the transistors 2A and 2B, respectively. Here, FIG. 2 shows two strings and related circuits for convenience of illustration, but in practice, a memory device has a form in which a plurality of strings are connected to a plurality of bit lines to increase storage capacity. Therefore, in one chip, the memory cell transistors in the string together with the memory cell transistors in all other strings constitute a memory cell array, in which the cell transistors are arranged in a matrix of rows and columns. . In order to select strings belonging to the same group and at least one word line in each operation mode, and to apply a corresponding voltage according to each operation mode to the control gate of the memory cells connected to the selected word line in common, The row decoder and program controller 1 connected to the gate of the two-selection transistor and the word lines is a signal and a signal for driving the selected transistor on the false string select line SSL, the ground select line GSL and the word lines WL1, WL2-WL16. Row decoding signals for selecting rows are provided as voltage signals, respectively. Thus, the transistors 2A-8A, 2B-8B in the string are controlled on or off in response to the signals provided to the gate terminals and the control gate terminals. Therefore, the selection of one particular memory cell is performed by activating the word line to which the cell is connected, the string select transistors corresponding to the cell, and the bit line select transistors to which the string is connected. When storing two bits per memory cell, the threshold voltages of the memory cells 3A-7A and 3B-7B are -2.6V or less as shown in the distribution diagram of FIG. 1), -2.0 V to 1.6 V (2). A value of -1.0 V to 0.6 V (3) and 0 V to 0.4 V (4) is set so that one of four different states is stored in one memory cell during programming. The manufacturing of the memory cells 3A)-(7A) and (3B)-(7B) is preferably carried out on a silicon semiconductor substrate having a major surface, the detailed structure of which is filed on January 13, 1993. It can be prepared as a structure as disclosed in the Republic of Korea Patent Application No. 93-390 previously filed by.

As shown in FIG. 2, data is programmed into a multi-state memory cell array having a plurality of strings connected to the row decoder and program controller 1, read the programmed data, and erased the programmed data for a predetermined purpose. In addition, in order to perform verification according to each operation, the semiconductor memory of FIG. 2 includes a bit line selection and charging unit 100 connected to the bit lines BL1 and BL2, a bit line level control unit 200 connected to the bit line selection and charging unit 100, It is connected to the multi-state reference voltage generator 350 and the fraud bit line level control unit 200 and the multi-state reference voltage generator 350 to temporarily store data to write data to memory cells at once through the corresponding bit lines in a program operation. Whether the program performed well in the program verification operation. And determining a page butter 300 for detecting and amplifying data on bit lines read from memory cells in a read operation.

Here, the page buffer 300 includes latches 17-18, 21-22 for storing data and associated transistors N8, N9, N10, N11, which are composed of two inverters alternately connected to the sensing circuit 14 as a sense amplifier. N12, N13, N14, N15, N16, and P11, and the bit line selection and charging unit 100 includes PMOS and NMOS transistors for selecting one of two bit lines (P3, N3, N4). And P4) and charging PMOS transistors P1 and P2 for receiving a power supply voltage at a source terminal. Drain terminals of the PMOS transistors P1 and P2 are connected to source terminals of the high voltage application preventing transistors N1 and N2 having drain-source passages connected to the bit lines BL1 (9) and BL2 (10), respectively. . The transistors N1 and N2 receive the control signal BLSHF to the gate terminal. The bit line level controller 200 includes a current source 23 connected between a node 11 connected to a source terminal of the selection transistor N3 and a ground, and the PMOS transistors having a source-drain path connected in series between the node 11 and a power supply voltage. (P5, P6, and P7), and a reset ensemble transistor N5 having a source-drain path connected between the node 11 and ground. The multi-state reference voltage generator 350 is configured to provide first, second, and third reference voltages (reference voltages Vref1,2,3) on node 12 of the second input terminal (−) of the sensing circuit 14. It has MOS transistors N6, N7, P8, P9 and P10. In the circuit of FIG. 2 configured as described above, one page buffer 300 exists per two bit lines according to the characteristics of the present invention, and one of the two bit lines is selected as the bit line selection signal BSO applied to the gate terminal; Is achieved by the corresponding selection transistors P3, N3, N4, P4.

Hereinafter, related operations of the multi-state nonvolatile semiconductor memory according to FIG. 2 having the above-described configuration will be described in detail with reference to FIGS. 3, 4, 5, 6, and 7.

[Read operation]

A read operation, also called a read or read mode, reads and stores data stored in a multi-state memory cell into the page buffer 300 through a selected bit line through a selected bit line, stores the data through an internal latch, and outputs the result to an external device. Point to. In order to perform such an operation, a voltage Vread (for example, a power supply voltage Vcc) required for a read operation is applied to a source terminal of the selection transistors 8A and 8B having a gate connected to the GSL of FIG. 2, and SSL and SGL The Vpass voltage (for example, 7 V) is applied to the word line of the unselected memory cell, and the voltage (for example 0 V) lower than the voltage Vpass is applied only to the word line of the selected memory cell. In this case, the voltage values of the important signals applied during the read operation may be provided together with the values of the Read column shown in Table-1 below. Table 1 below shows corresponding voltage values in the order of erase, program, read, program verify, and erase verify.

When voltage signals as shown in Table-1 are applied to corresponding portions in the second diagram, different voltages are induced in the selected bit line in the threshold voltage state of the selected cell. Here, in the bit line selection, any one of two bit lines is first selected by the bit line selection and operation of the bit line selection transistors P3, N3, N4, and P4 in the charging unit 100. Therefore, in the memory as a whole, it can be seen that the read operation of the present embodiment takes a method of sensing the voltage on all the bit lines twice in half. Therefore, since one bit buffer can cover two bit lines, the size of the chip is reduced accordingly. When the corresponding voltage is applied to each part according to Table-1 above and 0V is applied to the selected word line to which the control gates of the selected memory cells are commonly connected in different strings, the threshold voltage of the selected cells is -2.6V or less after the program execution. As shown in the lower part of FIG. 3, the voltage induced on the corresponding bit line is 2.6 V or more (7), and the threshold voltages of the selected cells are -2.0 V to 1.6 V (2) and -1.0 V to 0.6 V (3). ), The voltages induced in the bit lines are 1.6 V to 2.0 V (8) and 0.6 V to 1.0 V (9), respectively. In addition, when the threshold voltage of the selected cell is 0V to 0.4V (4), the voltage induced in the bit line becomes 0V (10) regardless of the threshold voltage of the selected memory cell. In FIG. 2, the PMOS field effect transistors FETs P1 and P2 in the bit line selection and charging unit 100 change the voltage of the unselected bit line to the same voltage as the power supply voltage Vcc, thereby selecting the selected memory cell. This prevents current from flowing to unselected bit lines through an unselected string connected to the same word line. In addition, the gate terminal of the transistor P7 in the bit line level controller 200 is supplied during a read operation. The signal is applied in a high voltage state so that the three transistors P5, P6 and P7 do not affect during the read operation. The NMOSFET N5 having a drain connected to the drain of the PMOSFET P7 receives an initial state of the selected bit line by receiving the reset signal Reset supplied to the gate terminal as a high voltage state for a predetermined time as soon as a read operation is started. It plays the role of making ground voltage (0V) state. After the selected bit line is initialized, the voltage on the bit line induced according to the threshold voltage value of the selected memory cell is transmitted to the node 11 through a pair of bit line selection transistors P3, N3 or P44 N4. Is provided. Therefore, the voltage on the node 11 is input to the first input terminal (+) of the sensing circuit 14. In order to distinguish four different states stored in the selected memory cell, the sensing circuit 14 uses three different levels of reference voltages Vrefl (13), Vref2 (14), and Vref3 () as shown in FIG. 15) is also received from the output node 12 of the multi-state reference voltage generator 350. Here, the specific configuration of the sensing circuit 14 may be implemented as a sense amplifier as disclosed in the patent application Nos. 95-12691 filed with the Korean Patent Office on May 20, 1995 by the applicant of the present application.

The voltage on the selected bit line provided to the node 11 is compared with the three reference voltages, which are sensed in two cycles in this embodiment.

In the first cycle, the clock signal in the multi-state reference voltage generator 350 ref1, Low and high voltages are respectively applied to the ref2 terminal to provide the second reference voltage Vref2 to the node 12. Accordingly, the bit line voltage applied to the first input terminal (+) and the second reference voltage Vref2 applied to the second input terminal (−) are compared by the sensing circuit 14, so that the selected memory cells are selected from four types of memory. It is distinguished whether it is programmed to belong to the upper two states or to the lower two states among the cell states. That is, the second reference voltage Vref2 is applied as 1.3 volts in FIG. 3 to become a reference voltage for dividing the upper two states or the lower two states. It can be seen that the priority of the second reference voltage Vref2 in this embodiment shortens the cycle of the sensing operation to two times. If the second reference voltage Vref2 is not provided preferentially, the cycle of the sensing operation is increased to three times.

The voltage level of the high or low sensed in the state in which the sensing circuit 14 is operable (that is, the high voltage is applied to the terminal SAE and the enable transistor N8 is activated) is determined through the output terminal SAO of the sensing circuit 14. Up to node 15. The detection result data on the output terminal SAO, P1, Apply a low voltage to all P2 terminals R1, When the high and low voltages are applied to the R2 terminal, they are stored in the first latch 17-18 through the transfer transistor N9. Also, in the second cycle, the clock signal in the multi-state reference voltage generator 350 ref1, Apply high and low voltage to ref2 terminal respectively. In this case, the data signal on the node 16 of the latch 17-18. (When the voltage shown on the selected bit line is higher and lower than the second reference voltage Vref2, respectively, the voltage becomes low and high level, respectively). The gate terminals of the transistors P9 and N6 are applied. Thus, the data signal In the case of the low level, the third reference voltage Vref3 is applied to the node 12, and in the case of the high level, the first reference voltage Vref1 is applied to the node 12. Accordingly, it is determined whether the voltage of the bit line shown on the node 11 corresponds to any one of the upper two states or the one of the lower two states. In other words, one state out of four states is distinguished in the second cycle. The voltage level of the high or low sensed in the state in which the sensing circuit 14 is operable (that is, the high voltage is applied to the terminal SAE and the enable transistor N8 is activated) is determined through the output terminal SAO of the sensing circuit 14. Up to node 15. The detection result data on the output terminal SAO is P1, Apply a low voltage to all P2 terminals R1, When low and high voltages are applied to the R2 terminal, they are stored in the second latch 21-22 through the transfer transistor N14.

On the other hand, in order to read the multilevel state stored in the memory cell, when the voltage Vread necessary for the read operation is applied to the source terminals of the select transistors 8A and 8B having the gate connected to the GSL signal line in the circuit of FIG. The time at which the voltage induced on the bit line reaches a steady state according to the threshold voltage state of is determined by the sub-threshold characteristic of the selected cell.

When the voltage of the bit line reaches from 0V to the desired voltage, the selected memory cell initially supplies a large amount of current to the bit line in the ON state, rapidly increasing the voltage of the bit line from 0V, but As the voltage nears a steady state, the difference between the voltage applied between the gate terminal and the source terminal of the selected memory cell is approximately equal to the threshold voltage of the selected memory cell. Slowly increase to the desired voltage. That is, in this state, the selected memory cell supplies a very small current (Sub-Threshold Current) to the bit line, so that the voltage of the bit line gradually increases for a long time. Therefore, an undesirable phenomenon occurs in which the read operation time is delayed accordingly. In the embodiment of the present invention, in order to prevent such a phenomenon, the current source 23 is employed between the node 11 and the ground in FIG. The current Ib1 flowing through the current source 23 prevents the selected memory cell from operating in the sub-threshold voltage state, thereby shortening the read operation time relatively. It will not be difficult for those skilled in the art to make the current source 23 connected to the node 11 by using the same transistor as the MOS transistor or the memory cell transistor.

[Program and program verify operation]

In the circuit of FIG. 2, the voltages of the signals applied to the main parts of the circuit during the program operation or the program verify operation are as shown in Table-1 above. The overall program cycle consists of a program operation of actually injecting electrons into the floating gate of the memory cell and a program verify operation of verifying whether the programmed memory cells have reached a desired state. The program operation and the program confirmation operation are repeated until the threshold voltages of all selected memory cells reach a desired level. During the program operation, the supply voltage (Vcc) and ground voltage are applied to the SSL and GSL terminals, Vpgm (for example, 14V to 20V) is applied to the word line to which the selected memory cell is connected, and the rest of the unselected memory cells are connected. The word lines are subjected to a Vpass (typically 8V to 12V) voltage. At this time, since 0V is applied to the substrate where the memory cells are located, a high voltage potential is maintained between the control gate terminal of the selected memory cell and the substrate of the selected memory cell, and thus FN (Fowler-Nordheim) is applied to the floating gate terminal of the selected memory cell. Electrons are collected by the tunneling phenomenon. As a result, the threshold voltage of the selected memory cell increases in a positive direction. Such a program operation is simultaneously performed on a plurality of memory cells connected to a selected word line instead of one memory cell. In the art, when all memory cells connected to one word line are programmed at the same time, a page program or a page write is called. Accordingly, the degree to which the selected memory cells are programmed is slightly different, and each of the selected memory cells is individually verified to verify that the desired state has been reached after one program operation, without affecting the memory cells having reached the desired state ( Program Inhibit) The program operation should be applied only to the memory cells which have less program. This program and program check operation is repeated until all selected cells have reached the desired state. In FIG. 2, the program operation is programmed with half of the cells connected to the selected word line first and then the other half. This is caused by the operation of the bit line selection transistors P3, N3, N4, and P4 in the bit line selection and charging unit 100. This is because a voltage is applied and the program is not prevented. For example, a signal BSO that selects one bit line in every two columns, Is applied as low and high, transistors P3 and N3 are turned on so that the odd-numbered bit lines (BL1 in FIG. 2) are all selected for the programming of the memory cells connected to the selected word line. At this time, the charging transistor P2 connected to the unselected bit line 10 is turned on in response to a low signal applied to the gate terminal to provide a power supply voltage on the bit line 10. Therefore, the memory cells connected to the selected word line in the string connected to the bit line 10 are prevented from being programmed.

On the other hand, program data information given externally during a program operation is input to two latches 17-18 and 21-22 in every two columns. The circuit of FIG. 2 makes both outputs Q1 and Q2 of the two latch circuits high when the selected memory cell reaches a desired state of the four states. Accordingly, the bit line to which the programmed memory cell is connected is occupied by the power supply voltage Vcc by the transistors P5 and P6, so that even if the program operation for the less programmed memory cells continues, the state of the memory cell once the program is completed is affected. Do not receive.

The process of selecting the reference voltage applied to the node 12 of the sensing circuit 14 of FIG. 2 in the program checking operation is the same as in the above-described read operation, and the output of the sensing circuit 14 is latched (17-18). 21-22), the path to pass in the first cycle, unlike in the read operation, P1, Apply high and low voltage to P2 terminal, R1, A low voltage is applied to both R2 terminals, causing the Q1 value stored in the first latch 17-18 through transistors N10 and N11 to transition from low to high when necessary. In the second cycle P1, Apply low and high voltage to P2 terminal, R1, A low voltage is applied to both R2 terminals, causing the Q2 value stored in the second latch 21-22 through transistors N15 and N16 to transition from low to high when necessary. The procedures for programming the memory cells selected as states 11, 10, 1, and 0 respectively from the erase (Erase, threshold voltage of memory cells of -2.6 V or less) described below are shown in Tables 2, 3, 4, and 5 below. In this case, the state change of the memory cells according to the stages is shown corresponding to FIGS. 4, 5, 6, and 7.

Table 2 above shows a state of a program verify operation when the program is programmed from the erase state 11 to the 11 state. In this case, since the selected memory cell does not need to be programmed, since both Q1 and Q2 are high, the bit line to which the memory cell is connected is cut off by the power supply voltage Vcc by transistors P5 and P6 during the program operation. The state of the cell does not change. The Stop items in Tables 2 to 5 correspond to the numbers of the arrows shown in FIGS. 4 to 7, respectively, and these numbers indicate the voltage induced in the bit line during the program check operation after one program operation. It compares with each reference voltage and shows what state is being reached. The Load Enable item in Tables 2 to 5 shows that the gate node 19 of the transistor N11 in FIG. 2 is in a high state (Y = Yes) or a low state (N = No). Selected Reference items in Tables 2 to 5 show which reference voltages among the reference voltages shown in the node 12 in FIG. 2 are selected and provided.

Initial Q1 and Q2 items in Table 2 to Table 5 show data values stored in the two latches of FIG. 2 before the start of the program operation. Final Q1 and Q2 items are stored in the latches after the program check operation is completed. Shows.

For convenience of explanation, a process of programming from an erase state to 0 will be described with reference to FIG. 7.

Step 1 of Table 5 corresponds to the arrow 1 in FIG. 7, and the state of the memory cell is changed only when the bit line of the selected memory cell has a voltage greater than Vref3 after the program operation is completed from the erased state. This is the case. In this case, the reference voltage applied to the sensing circuit 14 of FIG. 2 during the first cycle of the program check operation becomes Vref2 so that the output voltage of the sensing circuit 14 becomes low (0), and thus the NMOSFET N10 of FIG. The state is cut-off, and the value Q1 of the first latch remains unchanged. Thus, during the second cycle, the reference voltage of the sensing circuit 14 of FIG. 2 becomes Vref1 so that its output voltage is low (0), so that the NMOSFET N15 of FIG. 2 is cut off. The value of the second latch Q2 remains unchanged. Steps 2 and 3 in Table-5 correspond to arrows 2 and 3 in Fig. 7, respectively, and the operation is similar to Step 1 in Table-5. Step 4 of Table 5 corresponds to the arrow 4 in FIG. 7, which is a case where the state of the memory cell is changed to a degree that the bit line voltage of the selected memory cell is smaller than Vref2 after the program operation is completed. In this case, during the first cycle of the program check operation, the reference voltage of FIG. 2 becomes Vref2 and the output voltage of the sensing circuit becomes high (1) so that the NMOSFET N10 is ON, but Q2 is low, so the node of FIG. The voltage of 19) remains low by the NMOSFET N12, and the NMOSFET N11 is cut off. Therefore, the Load Enable item in Table-5 becomes N, and the value Q1 of the first latch remains unchanged. Steps 4 and 5 of Table 5 correspond to arrows 4 and 5 of FIG. 7, and have similar operations to step 3. Step 6 of Table 5 corresponds to the arrow 6 in FIG. 7 when the state of the memory cell is changed to the extent that the bit line voltage by the selected memory cell is smaller than Vref1 after the program operation is completed. The program wants the cell to complete. In this case, during the first cycle of the program check operation, the reference voltage of FIG. 2 becomes Vref2, and the output voltage of the sensing circuit becomes high (1), so that N10 is ON, but Q2 is low, so the node of FIG. Since the voltage of 19) remains low by the NMOSFET N12, and the NMOSEFT N11 is cut off, the Load Enable item in Table-5 is N, and the value Q1 of the first latch circuit is unchanged. However, since the reference voltage applied to the sensing circuit of FIG. 2 during the second cycle is Vref1, the output voltage of the sensing circuit is high (1), and when the NMOSFET N15 is on and the P2 signal is high, the NMOSFET N16 is on. The voltage at node 20 changes from high to low, causing Q2 to change from low to high. Since the program is completed with the selected memory cell in the desired state or Q1 is low, one more program operation is performed as shown in Step 7 of Table-5. In this case, during the first cycle of the program check operation, the reference voltage of the sensing circuit of FIG. 2 becomes Vref2 so that the output voltage of the sensing circuit becomes high (1), the NMOSFT N10 is on, and Q2 is high. Voltage of 19 When the P1 signal enters the high state, the NMOSF ET N11 is also turned on, and the voltage of the node 16 changes from high to low so that Q1 changes from low to high. During the second cycle, Q2 is already high, so Q2 remains unchanged. In the zero state program, one more program operation as shown in Step 7 of Table 5 means that the minimum threshold voltage of the memory cell in the zero state 4 of FIG. 3 is slightly larger than 0V. In practice, in general, if the program operation is repeated, the amount of change in the threshold voltage changed by one program operation decreases as the number of program operations increases. For these two reasons, it is not really a problem to carry out one more program operation as shown in Step 7 of Table-5 during zero state programming.

[Erase operation and Erase-Verify operation]

In the circuit of FIG. 2, the voltages of the signals applied to the main parts of the circuit during the erase operation and the erase check operation are as shown in Table-1 above. The basic unit of the erase operation is a string. In the erase operation, the SSL and GSL terminals are in a floating state, and 0 V is applied to word lines to which memory cells in the selected string are connected. The erase operation is simultaneously applied to memory cells connected to a plurality of selected word lines. At this time, an erase voltage Vers (typically 21V to 24V) is applied to the substrate where the memory cells are located, so that a high voltage is induced between the control gate terminal and the substrate of the selected memory cells and stored in the floating gate of the selected memory cells. Are escaped to the substrate by FN tunneling. Accordingly, the threshold voltage of the selected memory cell increases in the negative direction.

Similarly to the program operation, the erase operation is repeatedly performed to perform the (erase operation) + (erase confirmation operation) so that all selected memory cells reach a desired state (number 1 or 7 in FIG. 3). The signals applied to the respective parts of FIG. 2 during operation are shown in Table 1. In the erasure check operation, 7V is applied to the SSL and GSL signal lines of the selected string and 0V is applied to all the word lines inside the selected string. Basically, the erase check operation is similar to the read operation, except that the bit line voltage is determined by all memory cells in the string, so that the voltage induced in the bit line does not erase the threshold voltage among the memory cells in the selected string. Not determined by memory cells.

In the erase check operation, PMOSFETs P1 and P2 shown in FIG. 2 are charged to the same word line as the selected string by charging the voltage of the unselected bit line with the same voltage as the power supply voltage Vcc as in the read operation. This prevents all flow through unselected strings to unselected bit lines. Supplied to the gate terminal of the transistor P7 during the erase check operation. Since the signal is in a high low voltage state, transistors P5, P6, and P7 do not affect the erase check operation, and the NMOSFET N5 connected to the drain of the PMOSFET P7 is supplied to the gate terminal as soon as the erase check operation starts. Becomes a high voltage state for a certain time, making the initial state of the selected bit line the ground voltage (0V). After the selected bit line is initialized, the bit line voltage induced according to the threshold voltage values of the selected memory cells is transferred to the input node 11 of the sensing circuit 14 through the bit line selection transistors P2, N3, or P4, N4. Supplied. In order to simultaneously distinguish the states of the memory cells, all three reference voltages Vref1 (15), Vref2 (14), and Vref3 (13) shown in FIG. 3 should be 2.6 volts.

The voltage induced on the bit line is sensed in two cycles. In the first cycle, the clock signal in the multi-state reference voltage generator 350 ref1, The low and high voltages are applied to the ref2 terminal to provide the node 12 with the clock signal Vref2 (2.6 volts in the case of erasure confirmation) in the second reference. The result detected by the sensing circuit 14 in the operable state is shown in the output SAO of the sensing circuit. P1, Low voltage is applied to all P2 terminals R1, In the state where high and low voltages are applied to the R2 terminal, the voltage is stored in the first latch circuits 17 and 18 through the transistor N9. In the second cycle ref1, Low and high voltages are applied to the ref2 terminal. On the other hand, the signal Q1 stored in the first latch circuit 17-18 by the first cycle is connected to the gate terminals of the transistors P9 and N6. When Q1 is a high voltage, Vref3 and Qref is a low voltage. Voltage is supplied to the reference input node 12 of the sense circuit. The detection result of the sensing circuit 914 in the operational state is shown in the output SAO and the result is P1, Low voltage is applied to all P2 terminals R1, It is stored in the second latch circuit 21-22 through the transistor N14 with the low and high voltage applied to the R2 terminal. However, unlike in the read operation, Vref1 = Vref2 = Vref3 = 2.6V, so the outputs of the two latch circuits 17-18 and 21-22 when the bit line voltage is larger than 2.6V regardless of the selected reference terminal. Q2 is all high, indicating that all memory cells in the selected string have been sufficiently erased.

In the above, the data is programmed into the memory cell array of the NAND structured multi-state nonvolatile semiconductor memory, the programmed data is read, and the programmed data is erased according to a predetermined purpose, respectively. Implementing another verification on the operation of is described as an example and limited to the example.

However, the present invention is not limited to the memory of the NAND structure described above, but can be applied to a general-purpose multi-state nonvolatile memory device that stores a plurality of bit information by differentiating the amount of charge stored in the floating gate of the memory cell. Even in the case of the MASK ROM, it is possible to manufacture a memory cell having a plurality of states by the ion implantation technique.

According to the present invention as described above, a multi-state data storage technique can be applied to a NAND-type memory structure, and thus the number of memory cells can be significantly reduced compared to a single bit storage. In addition, the peripheral circuits of the memory cell array, such as the page buffer, have a structure corresponding to the two bit lines, thereby making the chip size more compact, thereby achieving the above-described object. Accordingly, the present invention has an advantage in that the number of memory cells can be reduced and the degree of integration can be improved by differentiating the amount of charge programmed in the floating gate of each memory cell in a nonvolatile semiconductor memory.

Claims (11)

Parallel bit lines formed over the semiconductor substrate; A plurality of strings formed in the semiconductor substrate and arranged in a matrix form, each string having a plurality of serially connected memory cells, connected to a corresponding bit line, and having a drain connected to a corresponding bit line among the bit lines; The source and source of the one select transistor are positioned between the drains of the second select transistor connected to the common source line, each memory cell spaced apart from the control gate, the floating gate and the semiconductor substrate through a channel for storage of multi-state data. A multi-state nonvolatile semiconductor memory having a multi-state memory cell array configured to have formed source and drain regions, the multi-state nonvolatile semiconductor memory comprising: gates of the first and second select transistors and the word lines, the same in each operation mode; Strings belonging to the group and at least one wordline Selected, and the non-volatile semiconductor memory characterized by having a control means for applying a corresponding voltage according to the respective operation Modal in common to the control gates of the memory cells connected to the selected word line. Parallel bit lines formed over the semiconductor substrate; A plurality of strings formed in the semiconductor substrate and arranged in a matrix form, each string having a plurality of serially connected memory cells connected to a corresponding bit line and having a drain connected to a corresponding bit line among the bit lines; The source and source of the one select transistor are positioned between the drains of the second select transistor connected to the common source line, each memory cell spaced apart from the control gate, the floating gate and the semiconductor substrate through a channel for storage of multi-state data. A multistate memory cell array configured to have formed source and drain regions; Control gates of the memory cells connected to the gates and the word lines of the first and second selection transistors, the strings belonging to the same group in each operation mode, and at least one word line and connected to the selected word lines. A data read method in a multi-state nonvolatile semiconductor memory having control means for applying a corresponding voltage according to each operation mode in common to a data source, comprising: maintaining a read voltage between a selected word line and the common source line and maintaining one same group; The voltages according to the threshold voltages of the memory cells of the same group connected to the selected word line by simultaneously selecting bit lines belonging to each other and charging non-selected bit lines belonging to another same group to a predetermined voltage are applied to the selected bit lines. A derivation process for deriving at the same time into each The derived voltages are differently compared as intermediate reference voltages among preset reference voltages, respectively, and the data indicating whether the selected memory cells are programmed to belong to an upper state or a lower state among a plurality of memory cell states is respectively programmed. A first storing step of simultaneously storing the temporary storing means; Comparing the derived voltage with a reference voltage according to the logic level of the stored data to simultaneously store in the second temporary storage means read data which actually indicates which of the plurality of memory cell states is selected. And a second storage process. 3. The method of claim 2, wherein the voltage is derived so that a derivation process for causing a voltage according to threshold voltage values of memory cells of the same group connected to the selected word line to be simultaneously drawn on the selected bit lines is performed faster. And providing a current source between the node and ground. 4. The data read method of claim 3, wherein the derivation process is performed after initializing the level of the selected bit lines to ground potential by an operation of a reset transistor in response to a reset signal. Parallel bit lines formed over the semiconductor substrate; A plurality of strings formed in the semiconductor substrate and arranged in a matrix form, each string having a plurality of serially connected memory cells, connected to a corresponding bit line, and having a drain connected to a corresponding bit line among the bit lines; The source of the first select transistor and the source of the second select transistor connected to a common source line are positioned between each memory cell, and each memory cell is spaced apart through a channel on a substrate at a control gate, a floating gate and a peninsula for storage of multi-state data. A multistate memory cell array configured to have formed source and drain regions; Control gates of the memory cells connected to the gates and the word lines of the first and second select transistors, the strings belonging to the same group in each operation mode and at least one word line, and connected to the selected word lines. A data program method in a multi-state nonvolatile semiconductor memory having control means for applying a corresponding voltage according to each operation mode in common: A program data provided in a program mode is stored through first and second temporary storage means, respectively. Receiving; The program voltage is maintained between the selected word line and the common source line, the power supply voltage and the ground voltage are applied to the gates of the first and second selection transistors, and the pass voltage is applied to the unselected word lines. The threshold voltage value of one of a plurality of states in which memory cells of the same group connected to the selected word line are simultaneously selected by simultaneously selecting bit lines and charging unselected bit lines belonging to the same group to another with a predetermined voltage. Data program method characterized in that consisting of a program and a program prohibition process to have a. Parallel bit lines formed over the semiconductor substrate; A plurality of strings formed in the semiconductor substrate and arranged in a matrix form, each string having a plurality of series-connected memory cells connected to a corresponding bit line and having a drain connected to a corresponding bit line among the bit lines; The source and source of the one select transistor are positioned between the drains of the second select transistor connected to the common source line, each memory cell spaced apart from the control gate, the floating gate and the semiconductor substrate through a channel for storage of multi-state data. A multistate memory cell array configured to have formed source and drain regions; Control gates of the memory cells connected to the gates and the word lines of the first and second selection transistors, the strings belonging to the same group in each operation mode, and at least one word line and connected to the selected word lines. A data program checking method in a nonvolatile semiconductor memory having control means for applying a corresponding voltage corresponding to each operation mode to a common method, the method comprising: maintaining a verification voltage between a selected word line and the common source line after performing a program operation; The voltage according to the threshold voltage value of the memory cells of the same group connected to the selected word line is selected by simultaneously selecting the bit lines belonging to the same group and charging the unselected bit lines belonging to the other same group to a predetermined voltage. To be drawn simultaneously on the bit lines Ex step; A first verifying step of comparing the derived voltage as an intermediate reference voltage among preset reference voltages and changing a logic state of data stored in the first temporary storage means according to the comparison result; A second verification process of comparing the derived voltage with a reference voltage according to the logic level of the stored data and changing a logic state of the data stored in the second temporary storage means according to the comparison result; And if the logic of the stored data is not set in the verification process, performing a program operation and then performing a re-execution process again. Parallel bit lines formed over the semiconductor substrate; A plurality of strings formed in the semiconductor substrate and arranged in a matrix form, each string having a plurality of serially connected memory cells, connected to a corresponding bit line, and having a drain connected to a corresponding bit line among the bit lines; The source and source of the one select transistor are positioned between the drains of the second select transistor connected to the common source line, each memory cell spaced apart from the control gate, the floating gate and the semiconductor substrate through a channel for storage of multi-state data. A multistate memory cell array configured to have formed source and drain regions; Control gates of the memory cells connected to the gates and the word lines of the first and second select transistors, the strings belonging to the same group in each operation mode and at least one word line, and connected to the selected word lines. A data erasing method in a multi-state nonvolatile semiconductor memory having control means for applying a corresponding voltage according to each operation mode in common, the method comprising: applying a ground voltage to all word lines connected to the memory cells, And erasing the memory cells temporarily by floating a common source line and gate terminals of the first and second selection transistors and providing an erase voltage to the substrate. Parallel bit lines formed on the semiconductor substrate; A plurality of strings formed in the semiconductor substrate and arranged in a matrix form, each string having a plurality of serially connected memory cells, connected to a corresponding bit line, and having a drain connected to a corresponding bit line among the bit lines; The source and source of the one select transistor are positioned between the drains of the second select transistor connected to the common source line, each memory cell spaced apart from the control gate, the floating gate and the semiconductor substrate through a channel for storage of multi-state data. A multistate memory cell array configured to have formed source and drain regions; Control gates of the memory cells connected to the gates and the word lines of the first and second selection transistors, the strings belonging to the same group in each operation mode, and at least one word line and connected to the selected word lines. In a multi-state nonvolatile semiconductor memory and a method for confirming data erasing, having a control means for applying a corresponding voltage according to each operation mode in common: A verification voltage is applied between all word lines and the common source line after performing an erase operation. Maintaining and charging unselected bit lines belonging to the same group to a predetermined voltage so that voltages corresponding to string threshold voltages of memory cells of the same group connected to the selected word line are simultaneously drawn on the selected bit lines. Derivation process; A first verifying step of comparing the derived voltage as an intermediate reference voltage and storing it in a first temporary storage means; A second verification step of comparing the derived voltage with the intermediate reference voltage and storing it in a second temporary storage means regardless of the logic level of the stored data; And if the logic of the stored data is not set in the verification process, performing the erase operation and performing the re-execution process again. Parallel bit lines formed over the semiconductor substrate; A plurality of strings formed in the semiconductor substrate and arranged in a matrix form, each string having a plurality of serially connected memory cells, connected to a corresponding bit line, and having a drain connected to a corresponding bit line among the bit lines; The source and source of the one select transistor are positioned between the drains of the second select transistor connected to the common source line, each memory cell spaced apart from the control gate, the floating gate and the semiconductor substrate through a channel for storage of multi-state data. A multi-state nonvolatile semiconductor memory having a multi-state memory cell array configured to have formed source and drain regions; Control gates of the memory cells connected to the gates and the fraud word lines of the first and second selection transistors and selecting at least one word line and strings belonging to the same group in each operation mode. Control means for applying a corresponding voltage to each operation mode in common; To program data into one of a plurality of states in a memory cell of the multi-state memory cell array, read the programmed data, erase the programmed data according to a predetermined purpose, and perform verification according to each operation. In order to alternately access selected memory cells of strings belonging to one same group and strings belonging to another same group in each operation mode, one bit line is sequentially connected every two bit lines and one Bit line selection and charging means for simultaneously selecting bit lines belonging to the same group and charging unselected bit lines belonging to the same group with a predetermined voltage; Bit line level control means connected to the bit line selection and charging means for controlling the level of the selected bit line corresponding to each operation mode; Multi-state reference voltage generation means for selecting one of the preset reference voltages differently according to each operation mode and logic level of the applied data and providing the same through an output terminal; The program data is temporarily stored and connected to the bit line level control means and the multi-state reference voltage generating means, respectively, to temporarily write data into the memory cells through corresponding bit lines in a program operation among the operation modes. Determining whether the program has been sufficiently performed in the verify operation, and comparing the voltage on the bit lines derived from the memory cells selected in the read operation with the reference voltage of the multiple levels to have sense and storage means for latching the sensed read data. Nonvolatile semiconductor memory device characterized in that. 10. The nonvolatile semiconductor memory device according to claim 9, wherein the multi-state data storage of each memory cell stores one of four states. Parallel bit lines formed over the semiconductor substrate; A plurality of strings formed in the semiconductor substrate and arranged in a matrix form, each string having a plurality of serially connected memory cells connected to a corresponding bit line and having a drain connected to a corresponding bit line among the bit lines; The source and the source of the first select transistor are located between the drains of the second select transistors connected to a common source line, each memory cell having a channel through a control gate, a floating gate and a semiconductor substrate to store two bits of data. A NAND flash multi-state semiconductor memory having a multi-state memory cell array configured to have source and drain regions spaced apart from each other; Control gates of the memory cells connected to the gates and the word lines of the first and second selection transistors, the strings belonging to the same group in each operation mode, and at least one word line and connected to the selected word lines. A row decoder and a program controller for commonly applying a corresponding voltage according to each operation mode to the row decoder; Program data into one of two bits of data represented in a memory cell of the multi-state memory cell array, read the programmed data, erase the programmed data according to a predetermined purpose, and verify verification according to each operation. In order to implement, in order to alternately access selected memory cells of strings belonging to one same group and strings belonging to another same group in each operation mode, they are connected in turn every two bit lines, and respond to an applied selection signal. Bit line selection and charging means for simultaneously selecting bit lines belonging to one same group and charging unselected bit lines belonging to another same group to a predetermined voltage; Bit line level control means having a current source and a reset transistor, the bit line level control means connected to the bit line selection and charging means to control the level of the selected bit line corresponding to each operation mode; Multi-state reference voltage generating means for selecting one of three preset reference voltages according to each operation mode and logic level of the applied data and providing the same through an output terminal; It includes a sense amplifier and two latches, each connected to the bit line level control means and the multi-state reference voltage generating means, respectively, the data at the time through the corresponding bit lines in the program operation of the operation mode; Temporarily store the program data to write to the memory cells, determine whether the program has been sufficiently performed in the program verify operation, and compare the voltage on the bit lines derived from the memory cells selected in the read operation with the reference voltage of the multiple levels to detect the readout. And sensing and storing means for latching data.