JPH07192480A - Flash memory - Google Patents

Abstract

PURPOSE:To obtain a constant erasing characteristic by controlling a current flowing through a source of a memory cell transistor so as to become a prescribed current value, and eliminating dependency of the erasing characteristic on erasing voltage supplied from the outside and thickness of a film between a substrate and a floating gate. CONSTITUTION:When a current value of a current Is flowing through a source of a memory cell transistor(Tr) becomes larger than the reference current Iref, a current IA flowing through a pMOSTr 19 and a nMOSTr 23 becomes larger than a current value of the Iref. Consequently, a current value of a current IB flowing through a nMOSTr 22 becomes larger than a current value of the Iref, voltage of a node 24 is dropped, gate voltage of a nMOSTr 15 is dropped. Therefore, as the Is is decreased, voltage of the node 24 is recovered to a normal value by the Iref, the Is is made equal to Iref. On the other hand, when the Is becomes smaller than Iref, the IA also becomes smaller than the Iref. Consequently, the Is also becomes smaller than the Iref, voltage of the node 24 is boosted and gate voltage of the Tr 15 is boosted. Therefore, as Is is increase, voltage of the node 24 is recovered to a normal value by the Iref, and the Is is made equal the Iref.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a batch erasing type electrically erasable and writable read only memory, a so-called flash memory.

The flash memory has a wide range such as an external storage device in a computer and a voice storage device because it is easy to integrate, electrically rewritable, and non-volatile. Application is possible,
It is attracting attention as a promising device in the future.

[0003]

2. Description of the Related Art FIG. 3 is a schematic sectional view showing the structure of a memory cell transistor mounted on a flash memory.

In the figure, 1 is a P-type silicon substrate, 2 is a source made of an N-type diffusion layer, 3 is a drain made of an N-type diffusion layer, 4 is a floating gate, and 5 is a control gate.

An insulating layer between the P-type silicon substrate 1 and the floating gate 4 and the floating gate 4 are provided.
The insulating layer between the control gate 5 and the control gate 5 is not shown.

Here, for writing, the source voltage Vs = 0
[V], drain voltage Vd≈6 [V], control gate voltage Vcg≈12 [V], and as shown by arrow A,
This is performed by injecting electrons generated in the vicinity of the drain 3 into the floating gate 4.

On the other hand, in erasing, the source voltage Vs≈
12V, drain 3 = open, control gate voltage Vcg = 0 [V], and electrons are extracted from the floating gate 4 to the source 2 as indicated by arrow B.

For reading, the source voltage Vs = 0
It is performed by setting [V], drain voltage Vd≈1 V, control gate voltage Vcg≈5 [V], and determining “1” or “0” of data depending on whether the drain current flows.

FIG. 4 is a circuit diagram showing a source power supply circuit provided in a conventional flash memory.
Is an erase instruction signal, and 6 and 7 are enhancement type pMOs.
S-transistors, 8 and 9 are enhancement type nMO
It is an S transistor.

Further, 10 is a power supply line for supplying a power supply voltage VCC (5 [V]) supplied from the outside to the internal circuit, and 11
Is the erase voltage VPP supplied from the outside (about 12 [V])
Is an erasing voltage line for supplying to the internal circuit.

The pMOS transistor 7 and the nMO
The inverter 12 is composed of the S transistor 9,
Its output 12A is connected to the source of the memory cell transistor.

At the time of erasing, the erasing instruction signal / SE
= 0 [V], the pMOS transistor 7 is turned on (conducting), and the nMOS transistor 9 is turned off (non-conducting), and the erase voltage VPP is supplied to the source of the memory cell transistor.

On the other hand, at the time of reading and writing, the erase instruction signal / SE = VCC, the pMOS transistor 7 is turned off, the nMOS transistor 9 is turned on, and the source voltage of the memory cell transistor is 0.
It is set to [V].

In this case, the pMOS transistor 6 is turned on and the gate voltage of the nMOS transistor 9 = VPP.
As a result, the nMOS transistor 9 is maintained in a completely ON state.

In this case, the nMOS transistor 8
= OFF, which prevents current from flowing to the erase instruction signal input side via the pMOS transistor 6 and the nMOS transistor 8.

[0016]

Here, in the conventional flash memory, the erase voltage VPP supplied from the outside causes the erase voltage line 11 and the pMOS transistor 7 of the source power supply circuit shown in FIG. Memory through
Supplied to the source of the cell transistor.

Therefore, the source voltage of the memory cell transistor depends on the erase voltage VPP supplied from the outside, and when the erase voltage VPP supplied from the outside changes during erase, the source voltage of the memory cell transistor of the memory cell transistor changes. The source voltage also fluctuates, the electric field strength between the source of the memory cell transistor and the floating gate fluctuates, and there is a problem that stable erase characteristics may not be obtained.

Further, in the non-volatile memory, if the film thickness between the substrate and the floating gate varies due to the process, the electric field strength between the source and the floating gate also varies during erasing. , The expected constant erasing characteristics cannot be obtained.

However, in the conventional flash memory, no measures have been taken against the variation in the electric field between the source and the floating gate due to the variation in the film thickness between the substrate and the floating gate.

In view of the above point, the present invention eliminates the dependency of the erase characteristic on the erase voltage supplied from the outside and the dependency of the erase characteristic on the film thickness between the substrate and the floating gate, and is supplied from the outside. It is an object of the present invention to provide a flash memory capable of obtaining expected constant erase characteristics even with respect to variations in erase voltage and variations in film thickness between a substrate and a floating gate.

[0021]

The flash memory according to the present invention determines whether or not the current flowing into the source of the memory cell transistor has a predetermined current value at the time of erasing, and Memory cell
A source current control circuit that controls the current flowing into the source of the transistor is provided.

[0022]

In the flash memory, the current flowing into the source of the memory cell transistor during erase is
This current depends on the vertical electric field on the substrate surface, which is caused by the band-to-band tunneling phenomenon on the substrate surface in the source region.

In the present invention, since the current flowing into the source of the memory cell transistor is controlled to have a predetermined current value at the time of erasing, when the erasing voltage supplied from the outside fluctuates. In addition, even when the film thickness between the substrate and the floating gate varies due to the process, the memory cell
The electric field between the source of the transistor and the floating gate can be maintained at a predetermined strength.

Therefore, according to the present invention, the dependence of the erase characteristic on the erase voltage supplied from the outside and the dependence of the erase characteristic on the film thickness between the substrate and the floating gate can be eliminated.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment and a second embodiment of the present invention will be described below with reference to FIGS.

First Embodiment FIG. 1 FIG. 1 is a diagram showing a main part of the first embodiment of the present invention, showing a source current control circuit provided in the first embodiment of the present invention.

In FIG. 1, 14 is a source current monitor circuit, and 15 is a source current monitor circuit.
Is an enhancement type nMOS transistor forming a variable resistance element, and the source of this nMOS transistor 15 is connected to the source of the memory cell transistor at the time of erasing.

In the source current monitor circuit 14,
Reference numeral 16 is an erase voltage line for supplying the erase voltage VPP supplied from the outside to the internal circuit, and 17 to 20 are enhancement type pMOS transistors.

Here, pMOS transistors 17 and 18
One current mirror circuit is composed of
The S transistors 19 and 20 form another current mirror circuit.

Reference numeral 21 is a depletion type nMOS transistor which forms a constant current source circuit.
The transistor 21 allows the pMOS transistor 17
A reference current Iref having a predetermined current value is made to flow therethrough.

Further, 22 and 23 are enhancement type nMOSs having the same size forming the current mirror circuit.
It is a transistor.

Here, pMOS transistors 19 and n
The current value of the current I _A flowing through the MOS transistor 23 is
pMOS transistor 20 and nMOS transistor 1
5 depends on the current value of the current Is that flows into the source of the memory cell transistor via 5.

Further, the pMOS transistor 18 and nM
The current value of the current I _B flowing through the OS transistor 22 is p
It depends on the current value of the reference current Iref flowing through the MOS transistor 17 and the current value of the current I _A flowing through the nMOS transistor 23.

Further, when the current value of the current Is flowing into the source of the memory cell transistor depends on the voltage value of the gate of the nMOS transistor 15, that is, the voltage value of the node 24, the voltage value of the node 24 becomes high. Becomes large, and becomes small when the voltage value of the node 24 becomes low.

Therefore, at the time of erasing, for example, a memory cell
When the current value of the current Is flowing into the source of the transistor becomes larger than the current value of the reference current Iref, the current value of the current I _A flowing through the pMOS transistor 19 and the nMOS transistor 23 also becomes larger than the current value of the reference current Iref.

As a result, the current value of the current I _B flowing through the nMOS transistor 22 also becomes larger than the current value of the reference current Iref, the voltage of the node 24 decreases, and the gate voltage of the nMOS transistor 15 decreases.

Therefore, the current Is flowing into the source of the memory cell transistor decreases, the voltage of the node 24 returns to the normal value by the reference current Iref, and the current value of the current Is flowing in the source of the memory cell transistor is It becomes the same as the current value of the reference current Iref.

On the other hand, the current value of the current Is flowing into the source of the memory cell transistor is the reference current Iref.
When the current value becomes smaller than the current value of
9 and the current value of the current I _A flowing through the nMOS transistor 23 is also smaller than that of the reference current Iref.

As a result, the current value of the current I _B flowing through the nMOS transistor 22 also becomes smaller than the current value of the reference current Iref, the voltage of the node 24 increases, and the gate voltage of the nMOS transistor 15 increases.

Therefore, as the current Is flowing in the source of the memory cell transistor increases, the voltage of the node 24 returns to the normal value due to the reference current Iref, and the current value of the current Is flowing in the source of the memory cell transistor is , Becomes the same as the current value of the reference current Iref.

Thus, in the first embodiment,
The current value of the current Is flowing into the source of the memory cell transistor at the time of erasing is the source current monitoring circuit 14 and nM.
The source current control circuit including the OS transistor 15 controls the current value to be the same as the current value of the reference current Iref.

Therefore, even if the erase voltage VPP supplied from the outside fluctuates, or even if the film thickness between the substrate and the floating gate varies due to the process, the memory. The strength of the electric field between the source of the cell transistor and the floating gate can be maintained at the expected constant value.

As described above, according to the first embodiment, the dependency of the erase characteristic on the erase voltage VPP supplied from the outside and the dependency of the erase characteristic on the film thickness between the substrate and the floating gate are eliminated. Therefore, it is possible to obtain the expected constant erasing characteristic even with respect to the fluctuation of the erasing voltage VPP supplied from the outside and the variation in the film thickness between the substrate and the floating gate.

By the way, the erasing characteristic of the memory cell transistor is improved as the temperature rises (erasing speed becomes faster) and deteriorates as the temperature lowers (erasing speed slows) due to the temperature dependence of the tunnel phenomenon. I know that.

Here, in the first embodiment, the depletion type nMOS transistor 21 is used, and the reference current Iref is obtained by grounding the gate and the source of the nMOS transistor 21, but in this case. , The drain current of the nMOS transistor 21, that is, the current value of the reference current Iref decreases at high temperature and increases at low temperature.

That is, according to the first embodiment, the source current control circuit including the source current monitoring circuit 14 and the nMOS transistor 15 operates in the direction of relieving the temperature dependence of the erase characteristic of the memory cell transistor. So
Even if the temperature changes, the expected constant erasing characteristics can be obtained.

Second Embodiment FIG. 2 FIG. 2 is a diagram showing a main part of the second embodiment of the present invention, showing a source current control circuit provided in the second embodiment of the present invention. In FIG. 2, 25 is a source current monitoring circuit, and 26 is a negative voltage generating circuit.

In the source current monitor circuit 25,
27 is an erase voltage line for supplying an erase voltage VPP supplied from the outside to the internal circuit, and 28 to 31 are enhancement type pMOS transistors.

Here, pMOS transistors 28 and 29 are provided.
One current mirror circuit is composed of
Another current mirror circuit is configured by the S transistors 30 and 31.

The source of the pMOS transistor 31 is connected to the source of the memory cell transistor during erasing.

Reference numeral 32 is a depletion type nMOS transistor which forms a constant current source circuit.
The transistor 32 allows the pMOS transistor 28
The reference current Iref flows through the.

Further, 33 and 34 are enhancement type nMOSs having the same size as the current mirror circuit.
It is a transistor.

In the negative voltage generating circuit 26, 3
Reference numerals 5 and 36 are inverters forming a buffer circuit, 37 is a ring oscillation circuit, 38 is a NAND circuit, 39 is a capacitor, and 40 and 41 are inverters.

Further, 42 is an inverter for inverting the oscillation output S _A of the ring oscillation circuit 43, 43 is a charge pump circuit for generating a negative voltage, 44 to 46 are enhancement type pMOS transistors, and 47 to 49 are It is a capacitor.

The output terminal 4 of the charge pump circuit 43
3A is connected to the control gate of the memory cell transistor.

In the source current monitoring circuit 25, the current value of the current I _C flowing through the pMOS transistor 30 and the nMOS transistor 34 is the current Is flowing into the source of the memory cell transistor via the pMOS transistor 31. Depends on the value.

Further, the pMOS transistor 29 and nM
The current value of the current _ID flowing through the OS transistor 33 is p
It depends on the current value of the current I _C which flows the current value of the reference current Iref flowing through the MOS transistors 28 and the nMOS transistor 34.

When the output of the inverter 36 = H level, the NAND circuit 38 operates as an inverter. Therefore, the ring oscillation circuit 37 oscillates, and when the output of the inverter 36 = L level, the NAND circuit 38 operates. Circuit 3
Since the output of 8 is fixed at the H level, the oscillation operation is not performed.

Therefore, at the time of erasing, the current value of the current Is flowing into the source of the memory cell transistor is the reference current Ir.
When it becomes smaller than ef, the current value of the current I _C flowing through the pMOS transistor 30 and the nMOS transistor 34 also becomes smaller than the reference current Iref.

As a result, the current value of the current _ID flowing through the nMOS transistor 33 also becomes smaller than the reference current Iref, and the level of the node 50 becomes the H level.

As a result, the output of the inverter 36 becomes H level, the ring oscillation circuit 37 starts the oscillation operation, the oscillation output S _A is supplied to the capacitors 47 and 49, and the inverted oscillation output / S _A is supplied to the capacitor 48. To be done.

As a result, the charge pump circuit 43 generates a negative voltage, this negative voltage is supplied to the control gate of the memory cell transistor, and the electric field between the source and the control gate of the memory cell transistor is increased. The strength is increased, that is, the strength of the electric field between the floating gate of the memory cell transistor is increased, and the current Is flowing into the source of the memory cell transistor is increased.

When the current value of the current Is flowing into the source of the memory cell transistor becomes larger than the reference current Iref, the pMOS transistor 3
0 and the current value of the current I _C flowing through the nMOS transistor 34 are also larger than the current value of the reference current Iref.

As a result, the current value of the current _ID flowing through the nMOS transistor 33 also becomes larger than the current value of the reference current Iref, and the level of the node 50 becomes L level.

Therefore, in this case, the inverter 3
The output of 6 = L level, the ring oscillation circuit 37 stops the oscillation operation, and the supply of the negative voltage to the control gate of the memory cell transistor is stopped.

As described above, in the second embodiment,
The current value of the current Is flowing into the source of the memory cell transistor at the time of erasing is controlled by the source current control circuit including the source current monitoring circuit 25 and the negative voltage generation circuit 26 to be the same as the reference current Iref. It

Therefore, even if the erase voltage VPP supplied from the outside fluctuates, or if the film thickness between the substrate and the floating gate varies due to the process, the memory The strength of the electric field between the source of the cell transistor and the floating gate can be maintained at the expected constant value.

As described above, according to the second embodiment, the dependence of the erase characteristic on the erase voltage supplied from the outside and the dependence of the erase characteristic on the film thickness between the substrate and the floating gate can be eliminated. Therefore, it is possible to obtain the expected constant erasing characteristic even with respect to the fluctuation of the erasing voltage VPP supplied from the outside and the variation in the film thickness between the substrate and the floating gate.

Further, in the second embodiment, the depletion type nMOS transistor 32 is used, and the reference current Iref is obtained by grounding the gate and the source of the nMOS transistor 32.

That is, according to the second embodiment as well, the source current control circuit including the source current monitoring circuit 25 and the negative voltage generation circuit 26 operates in the direction of easing the temperature dependence of the erase characteristic. Similar to the case of the example, the expected constant erasing characteristic can be obtained even with the temperature change.

[0071]

According to the present invention, at the time of erasing, the current flowing into the source of the memory cell transistor is controlled so as to have a predetermined current value. Since the dependency on the erase voltage and the erase characteristic on the film thickness between the substrate and the floating gate can be eliminated, the fluctuation of the erase voltage supplied from the outside and the film thickness between the substrate and the floating gate can be reduced. Even with respect to variations, the expected constant erasing characteristics can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a main part (source current control circuit) of a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a main part (source current control circuit) of a second embodiment of the present invention.

[Fig. 3] Memory cell installed in flash memory
It is a schematic sectional drawing which shows the structure of a transistor.

FIG. 4 is a circuit diagram showing a source power supply circuit provided in a conventional flash memory.

[Explanation of symbols]

(Fig. 1) 14 Source Current Monitoring Circuit 15 Enhancement-type nMO that forms variable resistance element
S transistor (Fig. 2) 25 Source current monitor circuit 26 Negative voltage generation circuit 37 Ring oscillation circuit 43 Charge pump circuit

Claims (5)

[Claims] 1. A source and a drain formed opposite to each other on one main surface side of a semiconductor substrate, and a floating gate and a control gate formed above a semiconductor region between the source and the drain with an insulating layer interposed therebetween. Writing is performed by injecting electrons into the floating gate, and erasing is performed by extracting electrons injected into the floating gate to the source. In a flash memory, at the time of erasing, a source current control circuit that determines whether the current flowing into the source has a predetermined current value and controls the current flowing into the source so as to have the predetermined current value is provided. A flash memory characterized by being provided. 2. The source current control circuit includes a variable resistance element in a current path of a current flowing into the source,
Using a predetermined reference current, the current value of the current flowing into the source is monitored to see if it is the predetermined current value, and the resistance value of the variable resistance element is adjusted to the predetermined current value. 2. The flash according to claim 1, further comprising a source current monitoring circuit for controlling.
memory. 3. The enhancement-type first pM having a source connected to an erase voltage line for supplying a predetermined erase voltage and a gate connected to a drain.
An IS transistor, an enhancement-type second pMIS transistor having a source connected to the erase voltage line and a gate connected to the gate of the first pMIS transistor, and a drain connected to a drain of the first pMIS transistor. A depletion type first nMIS transistor having a gate and a drain grounded, and an enhancement type third pMIS having a source connected to the erase voltage line and a gate connected to the drain.
A transistor and a source connected to the erase voltage line,
An enhancement type fourth pMIS transistor having a gate connected to the gate of the third pMIS transistor, a drain connected to the drain of the fourth pMIS transistor, a gate connected to the drain, and a source grounded. Enhancement-type second nMIS
A transistor and a drain connected to the drain of the second pMIS transistor and a gate connected to the second nM
An enhancement-type third nMIS transistor having a source connected to the gate of the IS transistor and a grounded source is provided, and the variable resistance element has a drain connected to the drain of the third pMIS transistor and a gate connected to the drain of the third pMIS transistor. Connected to the drain of the second pMIS transistor,
3. The flash memory according to claim 2, wherein the flash memory is an enhancement type fourth nMOS transistor whose source is connected to the source of the memory cell transistor. 4. The source current control circuit is provided with a negative voltage generating circuit for supplying a negative voltage to the control gate, and a current value flowing into the source by using a predetermined reference current is the predetermined current. A source current monitoring circuit for monitoring the negative voltage generating circuit so that the current flowing into the source has the predetermined current value. The flash memory according to claim 1, wherein the flash memory is a flash memory. 5. The enhancement-type first pM in which the source current monitoring circuit has a source connected to an erase voltage line for supplying a predetermined erase voltage and a gate connected to a drain.
An IS transistor, an enhancement-type second pMIS transistor having a source connected to the erase voltage line and a gate connected to the gate of the first pMIS transistor, and a drain connected to a drain of the first pMIS transistor. And a depletion type first nMIS transistor having a gate and a drain grounded, a source connected to the erase voltage line, a gate connected to the drain, and a drain connected to the source of the memory cell transistor during erase. An enhancement-type third pMIS transistor to be connected, and an enhancement-type fourth pMIS transistor having a source connected to the erase voltage line and a gate connected to the gate of the third pMIS transistor.
PMIS transistor and drain of the fourth pM
An enhancement-type second nMIS transistor having a drain connected to the IS transistor, a gate connected to the drain, and a source grounded; and a drain connected to the drain of the second pMIS transistor and a gate connected to the second pMIS transistor. An n-type enhancement-type third n transistor connected to the gate of the nMIS transistor and having its source grounded.
A negative voltage generating circuit, the negative voltage generating circuit generates a negative voltage when the drain level of the second pMIS transistor is at a high level, and the negative voltage generating circuit generates a negative voltage level of the drain of the second pMIS transistor. 5. The flash memory according to claim 4, wherein the flash memory is configured not to generate a negative voltage when is low.