JPH0765589A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To avoid soft write by a method wherein a reference bias voltage for setting a bit line potential is regulated by a constant current source circuit in the range wherein a cell current can be ensured to be at a prescribed value, and the upper limit of the reference bias voltage is limited by a voltage limiting circuit without deteriorating a readout speed. CONSTITUTION:The drain of a nonvolatile memory cell MC1 is connected to a bit line BL and a transistor TN1. On the gate of the TN1, a reference bias voltage Vb for controlling a voltage of the bit line is impressed. Between a control line LN of the Vb and VDD, a constant current source circuit formed of a depletion type MOS transistor TD1 is provided. The drain and the gate of a transistor TN2 are connected in common to the control line LN. A part between the drain and the source of a cell transistor CC1 for control is connected between the source of the TN2 and the ground. The CC1 is identical in nonuniformity with the memory cell MC1. The control line LN is provided with a voltage limiting circuit VLC so that the gate and the drain of the transistor TN2 may not be at a prescribed potential or above.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device. In particular, it relates to a circuit configuration for generating a reference voltage on a bit line.

[0002]

2. Description of the Related Art Non-volatile memory cell transistors have a double-layer gate structure including a charge storage layer. That is,
A floating gate electrode is provided between the gate of the MOS transistor and the substrate, and the threshold value of the MOS transistor is changed by injecting or releasing electrons into this floating gate. In the charge accumulation state where electrons are injected into the floating gate, the threshold value of the MOS transistor is effectively raised, and this state is changed to the “0” state, and conversely, when the electrons are not accumulated, the threshold value is increased. Is lowered, and this state is referred to as "1" state.

FIG. 4 is a circuit diagram for generating the content of the memory cell stored as described above as an input signal to the sense amplifier SA. That is, the resistor R is connected to the bit line BL side of the drain of the nonvolatile memory cell transistor MC. The power supply voltage V is applied to the other end of the resistor R.
DD is given. A connection point between the resistor R and the cell transistor MC is referred to as a node A.

When a power supply voltage VDD is applied and a gate voltage for reading is applied to the gate terminal of the cell transistor MC, when the memory state of the cell transistor MC is "1", the threshold value is low, so the cell transistor MC A current flows through the node A and the potential of the node A becomes the ground potential. When the storage state is "0", the threshold value is high and no cell current flows, so that the node A is charged through the resistor R and the potential rises to the power supply voltage VDD. That is, the storage state of the cell transistor MC can be read as a change in the potential of the node A.

By the way, at the time of reading, the voltages at the gate terminal and the drain terminal of the selected memory cell transistor, respectively Vg and Vd, are applied. This Vg,
Vd is set sufficiently lower than the voltages (Vpg, Vpd) applied to the gate terminal and the drain terminal at the time of writing, but even then, hot electrons were slightly injected, and while reading out for a long time Moreover, the threshold value of the cell transistor in the "1" state may increase. Even if the threshold rise is slight, it is "1"
The cell current of the cell transistor in the state is reduced, and as a result, the reading speed may be deteriorated. This is called soft light.

FIG. 5 is a circuit diagram for avoiding the soft write. Resistor R and cell transistor MC having the configuration of FIG.
A transistor T1 is inserted in series between the two. The reference bias voltage Vb is applied to the gate of the transistor T1. The drain of the cell transistor MC in this figure is referred to as a node B.

FIG. 6 is a characteristic diagram showing load curves of the transistor T1 and the cell transistor MC in FIG. That is, when the memory state of the cell transistor MC is "1", the operating point 31 is reached and the potential of the node B becomes VL. When the storage state is "0", the node B is charged through the resistor R and the transistor T1 and the potential rises, but from the reference bias voltage Vb to a voltage lower than the threshold Vth of T1 by Vb-Vth. Transistor T1 when rising
Is turned off, the potential of the node B becomes VH, that is, Vb.
-Vth (operating point 32).

Since both the voltages VH and VL depend on the reference bias voltage Vb, it is understood that the drain voltage of the cell transistor at the time of reading can be controlled by the reference bias voltage Vb.

If the reference bias voltage Vb is low, the drain voltage of the cell transistor is lowered, which reduces the cell current. It is known that a decrease in cell current reduces the margin for noise and delays the read access time. Therefore, the reference bias voltage Vb is a potential such that the deterioration of the read speed is within the allowable range even if the read operation is continued within the guarantee period (usually about 10 years) after evaluating the reliability of the memory cell transistor. Moreover, it is desirable to set the voltage as high as possible. Therefore, the circuit that generates the reference bias voltage Vb needs a circuit configuration that generates a bit line voltage suitable for the above characteristics.

FIG. 7 is a circuit diagram showing a conventional reference bias voltage generating circuit. By supplying a constant current generated by the constant current source S1 to the load composed of the transistors T2 and T3, a voltage corresponding to two thresholds of the transistor is generated. There is also a method of generating a constant voltage using a Zener diode.

As described above, the reference bias voltage Vb is set to a voltage as high as possible within the range where soft writing is allowed and a large cell current can be taken.
Since an actual device includes various process variations, it is necessary to set a reference bias voltage that does not cause a problem even in the worst case.

In practice, since the gate length L of the memory cell transistor varies in processing technology, the target gate length L
Small L and large L cell transistors are formed. Since the soft write becomes more severe as the gate length L becomes smaller, it is necessary to set the reference bias potential assuming the worst condition when L becomes the smallest. If L becomes large in this setting, the cell current decreases and the read time deteriorates. That is, since the bit line voltage is set low according to the worst condition, there is a problem that the reading speed is sacrificed in order to improve reliability.

[0013]

As described above, in the related art, since the memory cell transistors include various process variations, it is necessary to set the reference bias voltage in accordance with the worst condition. Has no choice but to set the bit line voltage low. Therefore, the read speed is sacrificed in order to improve the reliability, which is a problem.

The present invention has been made in consideration of the above circumstances, and an object thereof is to effectively avoid soft writing without deteriorating the read time due to variations in processing of memory cell transistors. It is an object of the present invention to provide a nonvolatile semiconductor memory device that generates an optimum reference bias potential that satisfies the soft write constraint and the read speed constraint.

[0015]

A nonvolatile semiconductor memory device according to the present invention has a charge storage layer, a threshold value varies depending on the charge storage state, and data corresponding to the threshold value is stored. A non-volatile memory cell transistor, a bit line connected to the drain of the memory cell transistor, a word line connected to the gate of the memory cell transistor, a drain connected to a first power supply via a resistance element, and a source connected to the bit. First connected to the wire
And a constant current source circuit provided between a control line connected to the gate of the first MOS transistor and a first power supply, and a drain and a gate connected to the control line A second MOS transistor having similar characteristics, and a drain and a source are connected between the source and the second power source of the second MOS transistor, and the gate has the same voltage as the selected word line when reading the memory cell data. A control cell transistor having the same shape as the memory cell transistor to which a voltage is supplied, and a voltage limiting circuit for preventing the gate and drain of the second MOS transistor from exceeding a predetermined potential, A reference bias voltage is applied to the gate of the first MOS transistor via a line And controlling the voltage on the line.

[0016]

According to the present invention, the process variation of the memory cell transistor is reflected in the control cell transistor. The control cell transistor has a threshold value corresponding to the "1" state. When the processing of the memory cell transistor varies and the gate length L becomes small, the reference bias voltage is lowered within a range in which the constant current source circuit can secure a constant value of the cell current, so that soft writing is less likely to occur. Moreover, the reading speed does not deteriorate. On the other hand, when the gate length L becomes thicker, soft writing is relatively hard to occur, so the reference bias voltage is increased to the extent of no problem and a constant cell current is secured by the constant current source circuit to deteriorate the reading speed. Do not let Further, since the upper limit of the reference bias voltage is limited by the voltage limiting circuit so that the reference bias voltage does not drop below a certain potential, soft writing can be avoided even in the worst situation.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. 1 is a circuit diagram showing a main part of a nonvolatile semiconductor memory device according to an embodiment of the present invention. The bit line BL is connected to the drain of the nonvolatile memory cell MC1 and the gate is connected to the word line WL. N channel MO
The drain of the S transistor TN1 is connected to the power supply voltage VDD through the resistor R1 and the source is connected to the bit line BL. The bit line B is connected to the gate of the transistor TN1.
A reference bias voltage Vb for controlling the voltage of L is applied.

A constant current source circuit made up of a depletion type MOS transistor TD1 is provided between the control line LN for the reference bias voltage Vb and the power supply voltage VDD. That is, the drain of the transistor TD1 has the power supply voltage V
The source and gate are commonly connected to node 101 at DD. As a result, the transistor TD1 is a constant current source circuit whose current value can be adjusted by the transistor size.

The node 101 has an N channel MO.
The drain and gate of the S transistor TN2 are commonly connected. This transistor TN2 is a transistor T
It has the same characteristics as N1. A control cell transistor CC1 is provided between the source of the transistor TN2 and the ground potential.
The drain and source of are connected. The cell transistor CC1 has the same shape as the memory cell MC1, that is, is formed in the same process,
By using the transistor formed in the memory cell array, it is possible to give the same variation as the characteristic variation of the memory cell transistor due to processing. To the gate of the cell transistor CC1, the same potential Vg as that applied to the gate when the memory cell MC1 is read is applied. The threshold value is set to a threshold value corresponding to the "1" state.

Further, the control line L for the reference bias voltage Vb
N is a voltage limiting circuit VL for preventing the gate and drain of the transistor TN2 from exceeding a predetermined potential.
C is provided to limit the rise of the reference bias voltage Vb.

FIG. 2 is a load curve of TN2 and CC1 of the circuit of FIG. The operation of the circuit having the above configuration will be described using this. As described above, the current value is adjusted by the transistor size of the transistor TD1. That is, the gate width W of TD1 is adjusted so that this current becomes the same as the minimum required cell current at the time of reading, and the current value Icell is set. The solid line 21 is the voltage-current characteristic of the cell CC1, and the solid line
22 is a characteristic of the load transistor TN2. The point at which the current Icell passed by the current source depletion type transistor TD1 intersects with the solid line 21 is the potential V102 of the node 102, and FIG.
It appears as an output voltage at the middle node 101.

Next, consider the case where the processing of the cell transistor is varied and the gate length L is reduced. At this time, the cell current increases and has a characteristic as shown by a broken line 23, and the output bias voltage Vb decreases (V23) accordingly, and the soft write is alleviated. However, since the cell current secures Icell, the reading is performed. There is no deterioration in time.

On the contrary, when the gate length L becomes large,
The characteristic is as shown by the broken line 24, and the output bias voltage V
Although b increases, when L is large, soft write is relatively unlikely to occur, so that a certain increase in Vb can be tolerated and the cell current can be secured instead. Can be fast.

However, when L is larger than the characteristic shown by the broken line 24 and the cell current cannot be obtained, it is still possible to rapidly increase Vb when trying to secure the cell current.
Expected from. In order to prevent this, there is a voltage value limiting circuit VLC as a limiter function, which is controlled so that the potential of Vb does not rise above the soft writing limit voltage Vlimt.
The voltage limit circuit VLC is the soft write limit voltage Vlmt.
In the above case, it can be realized by using, for example, a Zener diode so that the reverse current starts to flow. Also TN
Since 2 uses a transistor having the same characteristics as the transistor TN1 for controlling the bit line voltage, even if the processing of this transistor varies, the variation can be absorbed and the optimum reference bias voltage Vb can be generated.

FIG. 3 is a circuit diagram showing the configuration of the second embodiment. This is obtained by replacing the depletion type transistor TD1 as the current source circuit in FIG. 1 with a current mirror circuit of a P-type transistor and an operational amplifier circuit, and the operating principle is the same as that of the embodiment of FIG. This is a configuration for providing further accuracy as a current source circuit.
That is, the P-channel MOS transistors TP1 and TP
The sources of 2 are commonly connected to VDD, their gates are commonly connected to the current control side node C, and are connected to the drain of the current control MOS transistor TN3. The gate of the transistor TN3 is controlled by the output of the operational amplifier OP. That is, the inverting input of the operational amplifier OP is the source of the transistor TN3, and the non-inverting input is the reference voltage Vre.
connected to f. The source of the transistor TN3 is grounded via the resistor R2.

The means for forming the constant current source is not limited to the method using the depletion type transistor or the method using the operational amplifier circuit, and the same effect can be obtained by using other means. The same applies to the voltage limiting circuit, which is not limited to the method using the Zener diode.

[0027]

As described above, according to the present invention,
When manufacturing a non-volatile semiconductor memory, even if there are variations, it is possible to self-align the reference bias potential for giving the optimum bit line potential that reduces the soft write without degrading the writing time as much as possible. It is possible to improve the manufacturing yield and reliability. Further, in the prior art, it is necessary to set the reference bias voltage so as to guarantee the worst condition, whereas in the present invention, the reference bias voltage can be set higher than the worst condition by the voltage limiting circuit, so that it is faster than the conventional one. Read operation is realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a main part of a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a characteristic diagram showing a load curve of the circuit in FIG.

FIG. 3 is a circuit diagram showing a configuration of a second embodiment.

FIG. 4 is a simplest circuit diagram for reading the stored contents of a nonvolatile memory as a voltage.

FIG. 5 is a circuit diagram of a clamp circuit of a bit line that can avoid soft writing.

6 is a characteristic diagram showing a load curve of the circuit in FIG.

FIG. 7 is a circuit diagram showing a conventional reference bias voltage generation circuit.

[Explanation of symbols] TN1, TN2 ... N-channel MOS transistor, MC
1 ... Non-volatile memory cell, TD1 ... Depletion type transistor, CC1 ... Control cell transistor, V
LC ... Voltage limiting circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/792

Claims (1)

[Claims] 1. A non-volatile memory cell transistor having a charge storage layer, the threshold value of which changes depending on the charge storage state, and which stores data according to the threshold value, and a drain of the memory cell transistor. A bit line connected to the memory cell transistor, a word line connected to the gate of the memory cell transistor, a drain connected to a first power supply via a resistance element, and a source connected to the bit line, a first MOS transistor, A constant current source circuit provided between a control line connected to the gate of the first MOS transistor and a first power supply; and a drain and a gate connected to the control line to connect the first M
A second MOS transistor having characteristics similar to those of the OS transistor; a drain connected between the source of the second MOS transistor and the second power supply; and a source connected to the gate of the selected word line at the time of reading memory cell data. A control cell transistor having the same shape as the memory cell transistor supplied with the same voltage as the voltage; and a voltage limiting circuit for preventing the gate and drain of the second MOS transistor from reaching a predetermined potential or more. A nonvolatile semiconductor memory device, wherein a reference bias voltage is applied to the gate of the first MOS transistor via the control line to control the voltage of the bit line.