JP2005149625A - Semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce read errors of stored-value caused by the variation of characteristics of a memory transistor in a semiconductor memory. <P>SOLUTION: A sense amplifier, which can set a reference current Iref to be supplied to a bit line in accordance with the varied characteristics of the memory transistor, is used in the semiconductor memory. The sense amplifier is provided with; a pMOS transistor 511 in which a source is connected to a power source line VDD, and a drain and a gate are connected to each other; a resistor 514 whose one end is connected to the drain of the pMOS transistor 511 and whose other end is connected to a ground line GND; pMOS transistors 512-1 to 512-3 in which the sources are connected to the power source line VDD and the gates are connected to the drain of the pMOS transistor 511; and trimming resistors 515-1 to 515-3 which individually control "On/Off" of the corresponding pMOS transistors 512-1 to 512-3. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory, and more particularly to an improvement in a sense amplifier that supplies a constant current to each bit line.

  The semiconductor memory includes a group of memory cells arranged in a matrix, a word line provided for each column of the memory cell group, and a bit line provided for each row of the memory cell group.

  As this type of semiconductor memory, for example, those disclosed in Patent Documents 1 and 2 below are known.

  As the semiconductor memory, for example, there is a type of memory that reads a stored value bit by bit, and a type of memory that reads a stored value of 1 byte (that is, 8 bits) simultaneously. In a type of memory that reads stored values bit by bit, one word line and one bit line are selected simultaneously. On the other hand, in a type of memory that simultaneously reads a 1-byte stored value, one word line and eight bit lines are selected simultaneously. A constant current Iref is supplied to the selected bit line.

  Each memory cell has, for example, one memory transistor. The binarized data is stored as the on / off state of the memory transistor. For example, in EEP-ROM (Electrically Erasable Programmable Read Only Memory) and flash memory, binary data is recorded by storage / non-storage of the floating gate. In a mask ROM (Read Only Memory), binary data is recorded by pulling up / down a gate electrode.

When the memory transistor in the selected memory cell is on, a part of the constant current Iref is discharged to the ground line through the memory transistor, and therefore the potential of the bit line connected to this memory cell is lowered. On the other hand, when the memory transistor of the selected memory cell is off, the memory transistor does not discharge current to the ground line, and therefore the potential of the bit line connected to this memory cell does not decrease. Thus, the high level / low level of the bit line potential is determined by turning on / off the memory transistor. Therefore, the stored value of the memory transistor can be read by determining the high level / low level of the bit line potential.
JP-A-6-60677 JP 2000-306392 A

  The high / low level of the bit line potential is determined by the difference between the constant current Iref supplied from the sense amplifier to the bit line and the current Icell flowing out from the selected memory transistor to the ground line. Therefore, in order to prevent erroneous reading, it is necessary to accurately control the current Iref-Icell.

  Here, the current Iref of the sense amplifier can be controlled with high accuracy by using a mirror circuit. On the other hand, since the current Icell flowing through the memory transistor is affected by the characteristic variation for each device, it is difficult to control with high accuracy. In one device, the characteristics of the memory transistor may differ depending on the position of the memory cell. As factors causing variations in the characteristics of the memory transistor, for example, variations in the thickness of the gate oxide film, the capacitance of the floating gate, and the diameter of the tunnel window can be considered.

  Variations in the characteristics of the memory transistors cause erroneous reading of stored values, and thus reduce the yield of semiconductor memories.

  An object of the present invention is to suppress the influence of characteristic variations of memory transistors and improve the yield of semiconductor memories.

  In a semiconductor memory according to the present invention, a current generation circuit that generates a reference current to be supplied to a bit line has a first main electrode connected to a first power supply line, and a second main electrode and a control electrode connected to each other. A first transistor, a resistor having one end connected to the second main electrode of the first transistor and the other end connected to the second power supply line, a first main electrode connected to the first power supply line, and a control electrode A plurality of second transistors connected to the control electrode of the first transistor, and provided for each second transistor, the first main electrode being connected to the second main electrode of the corresponding second transistor, and the second transistor A third transistor that outputs a reference current from the two main electrodes; and a current control circuit that individually controls on / off of the third transistor.

  In the semiconductor memory according to the present invention, the reference current supplied to the bit line is the sum of the currents flowing through the third transistor that is turned on. For this reason, the reference current can be adjusted by individually controlling on / off of the third transistor by the current control circuit. Therefore, according to the present invention, the reference current supplied to the bit line can be adjusted according to the characteristics of the semiconductor memory, thereby improving the yield of the semiconductor memory.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the size, shape, and arrangement relationship of each component are shown only schematically to the extent that the present invention can be understood, and the numerical conditions described below are merely examples. .

First Embodiment A first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is a block diagram schematically showing the overall configuration of the semiconductor memory according to the first embodiment. As shown in FIG. 1, the semiconductor memory 100 of the present embodiment includes a memory matrix 110, an address buffer 120, a Y decoder 130, an X decoder 140, a sense amplifier 150, a plurality of word lines WL, And a plurality of bit lines BL.

  As shown in FIG. 2, the memory matrix 110 includes a plurality of memory cells M11 to Mmn arranged in a matrix. In addition, a control line CL and an nMOS transistor 111 for selecting a control line are provided for each row of the memory matrix 110. Each of the memory cells M11 to Mmn includes a memory transistor 112 and a word line selection transistor 113. Here, an nMOS transistor having a floating gate structure is employed as the memory transistor 112, and a normal nMOS transistor is employed as the word line selection transistor 113. In the control line selection transistor 111, the source is connected to the control line CL, the read reference voltage Vref is input from the drain, and the gate is connected to the word line WL. The memory transistor 112 is connected to the source of the word line selection transistor 113 at the drain, connected to the control line CL at the gate, and connected to the ground line GND at the source. The word line select transistor 113 has a drain connected to the bit line BL and a gate connected to the word line WL. When any one of the word lines WL is selected (that is, set to a high level), the corresponding control line selection transistor 111 and word line selection transistor 113 are turned on. Thereby, the memory transistor 112 is turned on or off according to the stored value (charge accumulation / non-accumulation of the floating gate). Therefore, conduction / non-conduction between the bit line BL and the ground line GND is determined according to the stored value of the memory transistor 112.

  The address buffer 120 divides a read address input from the outside into an upper address and a lower address. The upper address is sent to the Y decoder 130 via the upper address line 121, and the lower address is sent to the X decoder 140 via the lower address line 122. In this embodiment, the upper address is 8 bits and the lower address is 4 bits. Therefore, the read address is 12 bits.

  The Y decoder 130 selects one word line WL corresponding to the upper address input from the upper address line 121. As described above, the selected word line WL is set to the high level, and the non-selected word lines WL are set to the low level. In this embodiment, the upper address is 8 bits, and therefore the number of word lines WL is 2 to the 8th power, that is, 256 (see FIG. 3). As shown in FIG. 3, in the present embodiment, the word line corresponding to the smallest upper address value '00000000' is arranged at the lowest stage, and the word line corresponding to the largest upper address value '11111111' is arranged at the uppermost stage. Arranged.

  The X decoder 140 selects eight (1 byte) bit lines BL corresponding to the lower address input from the lower address line 122. In this embodiment, the lower address is 4 bits, and therefore, the lower address value is the fourth power of 2, that is, 16 types. Therefore, when eight bit lines correspond to each lower address value (that is, when 1-byte binarized data is stored for each address), the total number of bit lines BL is 8 × 16, that is, 128. It is. As shown in FIG. 4, the X decoder 140 includes the same number of select transistors 141, 141,... As the bit lines BL. The drain of each selection transistor 141 is connected to the corresponding bit line BL. The source of each select transistor 141 is connected to the corresponding bit terminals T1 to T8 of the sense amplifier 150. Furthermore, the gate of each select transistor 141 is connected to one of address control lines ACL1-16. Here, the address control lines ACL1 to ACL16 are selected by a decoder (not shown) based on the value of the lower address line 122. As shown in FIG. 4, in this embodiment, eight bit lines corresponding to the smallest lower address value “0000” (that is, eight bit lines corresponding to the address control line ACL1) are arranged on the leftmost side. The eight bit lines corresponding to the largest lower address value '1111' (that is, the eight bit lines corresponding to the address control line ACL16) are arranged on the rightmost side.

  The sense amplifier 150 reads the stored value from the selected memory cell. The sense amplifier 150 includes eight readout circuits. Each readout circuit is connected to a corresponding bit terminal T1 to T8 (see FIG. 4). Hereinafter, the sense amplifier 150 will be described.

  FIG. 5 is a circuit diagram illustrating a configuration example of the sense amplifier 150. The sense amplifier 150 includes a current mirror circuit 510 and a read circuit 520.

  The current mirror circuit 510 includes pMOS transistors 511, 512-1 to 512-3, 513-1 to 513-3, a resistor 514, and trimming registers 515-1 to 515-3. The pMOS transistors 512-1 to 512-3 and 513-1 to 513-3 are provided for each bit terminal. On the other hand, one pMOS transistor 511, one resistor 514, and one trimming register 515-1 to 515-3 are provided in the sense amplifier 150, respectively.

  In the pMOS transistors 511, 512-1 to 512-3, the source is connected to the power supply line VDD, and the gate is connected to the drain of the pMOS transistor 511. The resistor 514 has one end connected to the drain of the pMOS transistor 511 and the other end connected to the ground line GND. In the present embodiment, the characteristics of the pMOS transistors 511, 512-1 to 512-3 are the same. The switching pMOS transistors 513-1 to 513-3 have their sources connected to the drains of the corresponding pMOS transistors 512-1 to 512-3, and are connected to the node N2 of the readout circuit 520 (see FIG. 6B). The drains are connected in common. In the present embodiment, the characteristics of the pMOS transistors 513-1 to 513-3 are the same. Therefore, the drain currents Iref1, Iref2, and Iref3 when the pMOS transistors 513-1 to 513-3 are on have the same value.

  An internal configuration of the trimming register 515-1 is shown in FIG. The trimming register 515-1 controls on / off of the switching pMOS transistor 513-1. The trimming register 515-1 includes an nMOS transistor 611 having a floating gate structure, a constant current source 612, and an inverter 613. In the nMOS transistor 611, the source is connected to the ground line GND, the drain is connected to the constant current source 612, and the reference potential Vref is constantly applied to the gate. The inverter 613 has an input terminal connected to the drain of the nMOS transistor 611 and an output terminal connected to the gate of the switching pMOS transistor 513-1. The configuration and operation of the trimming registers 515-2 and 515-3 are the same as the configuration and operation of the trimming register 515-1, and thus description thereof is omitted.

  In the trimming register 515-1 in FIG. 6A, when no charge is accumulated in the floating gate of the nMOS transistor 611, the nMOS transistor 611 is always off, so that the input potential of the inverter 613 becomes high level. . Therefore, the switching transistor 513-1 is turned on, so that the current Iref1 is supplied to the bit terminal T. On the other hand, when charge is accumulated in the floating gate of the nMOS transistor 611, the nMOS transistor 611 is always on, so that the input potential of the inverter 613 is at a low level. Therefore, the switching transistor 513-1 is off, and the current Iref1 is not supplied to the bit terminal T. Thus, in this embodiment, the reference current Iref supplied to the bit terminal is controlled by the number of trimming registers in which the floating gate of the nMOS transistor 611 is stored. Since Iref1 = Iref2 = Iref3 as described above, the current Iref supplied from the current mirror circuit 510 to the readout circuit 520 is any one of Iref1, 2Iref1, and 3Iref1.

  An internal structure of the reading circuit 520 is illustrated in FIG. The read circuit 520 includes pMOS transistors 621 and 622, nMOS transistors 623 to 626, and a buffer 627. The pMOS transistor 621 is connected to the power supply line VDD at the source, and receives the sense amplifier activation signal SAN from the gate. The pMOS transistor 622 has a source connected to the drain of the pMOS transistor 621, a drain connected to the node N1, and a gate connected to the bit terminal T (any of T1 to T8). In the nMOS transistor 623, the source is connected to the ground line GND, the drain is connected to the node N1, and the signal SAN is input from the gate. The nMOS transistor 624 has a source connected to the ground line GND, a drain connected to the node N1, and a gate connected to the bit terminal. The nMOS transistor 625 has a drain connected to the power supply line VDD, a source connected to the node N2, and a gate connected to the node N1. The nMOS transistor 626 has a drain connected to the bit terminal T, a source connected to the node N2, and a gate connected to the node N1. Buffer 627 is connected to node N2 at the input terminal, and outputs the read value from the output terminal to the outside.

  In the reading circuit 520 of FIG. 6B, when reading is not performed, the sense amplifier activation signal SAN is set to a high level. When the signal SAN is at a high level, the pMOS transistor 621 is turned off and the nMOS transistor 623 is turned on, so that the potential of the node N1 is at a low level. As a result, the nMOS transistors 625 and 626 are turned off, so that the output current Iref of the current mirror circuit 510 is not supplied to the bit terminal. On the other hand, when reading is performed, the signal SAN is set to a low level. When the signal SAN is at a low level, the pMOS transistor 621 is turned on and the nMOS transistor 623 is turned off. Therefore, when the bit line is at a low level, the pMOS transistor 622 is turned on and the nMOS transistor 624 is turned off, whereby the nMOS transistors 625 and 626 are turned on. Therefore, the current Iref is supplied to the bit line BL via the bit terminal and the X decoder 140. As will be described later, the memory transistor 112 (see FIG. 2) is turned on or off in accordance with charge accumulation / non-accumulation of the floating gate. When the memory transistor 112 is on, the current Iref is discharged to the ground line GND, so that the output of the buffer 627 becomes low level. On the other hand, when the memory transistor 112 is off, the potential of the bit line BL rises due to the current Iref, whereby the pMOS transistor 622 is turned off and the nMOS transistor 624 is turned on. For this reason, the nMOS transistors 625 and 626 are turned off, so that the potential of the node N2 is raised by the current Iref. As a result, the output of the buffer 627 becomes high level.

  Next, the overall operation of the semiconductor memory according to the present embodiment will be described.

  First, the read address is input to the address buffer 120 (see FIG. 1). Of this read address, the upper address (8 bits) is sent to the Y decoder 130, and the lower address 4 bits is sent to the X decoder 140. The Y decoder 130 sets one word line WL corresponding to the input upper address to a high level, and sets the other word lines WL to a low level. Further, the X decoder 140 turns on the eight selection transistors 141 corresponding to the input lower address and turns off the other selection transistors. As a result, eight memory cells, that is, one-byte memory cells in the memory matrix 110 are selected.

  The sense amplifier 150 outputs a predetermined constant current from each of the bit terminals T1 to T8. As described above, the value of the constant current is set by the trimming registers 515-1 to 515-3. These constant currents are supplied to the selected bit line BL via the selection transistor 141 that is turned on.

  As described above, the potential of the selected word line WL is set to a high level. Therefore, all the nMOS transistors 113, 113,... Connected to the selected word line WL are turned on. The nMOS transistor 111 connected to the selected word line WL is also turned on. As a result, among the memory transistors 112, 112,..., The one that stores the floating gate is turned on. On the other hand, among the memory transistors 112, 112,..., Those in which the floating gate is not charged are not turned on because the operation threshold is very high.

  When the memory transistor 112 is turned on, the selected bit line BL corresponding to the memory transistor 112 becomes conductive with the ground line GND. Therefore, the constant current supplied from the sense amplifier 150 to the bit line BL is discharged to the ground line GND, so that the potential of the bit line BL becomes a low value. On the other hand, when the memory transistor 112 is turned off, the selected bit line BL corresponding to the memory transistor 112 is not electrically connected to the ground line GND. Therefore, the constant current supplied from the sense amplifier 150 is accumulated in the bit line BL, thereby increasing the potential of the bit line BL. As described above, the buffer 627 provided in the reading circuit 520 (see FIG. 6B) in the sense amplifier 150 outputs a high level when the potential of the bit line BL is higher than a predetermined value, and the bit line. When the potential of BL is lower than a predetermined value, a low level is output. In this way, the binarized information (that is, storage / non-storage of the floating gate) written in the memory transistor 112 is read as the output potential of the buffer 627.

  Here, the ability to discharge charges from the bit line BL to the ground line GND varies depending on the characteristics of the memory transistor 112. Therefore, depending on the characteristics of the memory transistor 112, the potential of the bit line BL is not sufficiently lowered even when the memory transistor 112 is on, and erroneous reading may occur. On the other hand, in the present embodiment, the value of the constant current Iref supplied from the sense amplifier 150 to the bit line BL can be adjusted according to the characteristics of the memory transistor 112, thus preventing such erroneous reading. It becomes possible to do. That is, when the drain current when the memory transistor 112 is on is small, the trimming registers 515-1 to 515-3 are set so that the value of the reference current Iref supplied from the sense amplifier 150 to the bit line BL is small. On the contrary, when the drain current is large, the trimming registers 515-1 to 515-3 are set so that the value of the reference current Iref becomes large.

  As described above, according to the present embodiment, the constant current Iref supplied from the sense amplifier 150 to each bit line BL can be adjusted, so that erroneous reading due to variations in characteristics between devices of the memory transistor is suppressed. can do. Therefore, according to this embodiment, the yield of the semiconductor memory can be improved.

  Note that an nMOS transistor 611 having a floating gate structure (see FIG. 6A) may have the same structure and size as the nMOS transistor 112 in the memory matrix 110 (see FIG. 2). However, the nMOS transistor 611 is not used for data storage, and is therefore formed in a region different from the memory matrix 110.

  Setting of the trimming registers 515-1 to 515-3 (that is, charge accumulation in the nMOS transistor 611) is performed at the manufacturing stage of the semiconductor memory. That is, the drain current of the memory transistor 112 (see FIG. 2) is inspected in the inspection process during the manufacturing process, and the supply current to the bit line BL is determined according to the inspection result. The process of setting 515-3 is performed.

  As described above, in this embodiment, the characteristics of the pMOS transistors 511, 512-1 to 512-3 (see FIG. 5) are the same. Therefore, the currents Iref1, Iref2, and Iref3 supplied from the selection transistors 513-1 to 513-3 to the bit terminals all have the same value. However, by forming the pMOS transistors 512-1 to 512-3 so as to have different characteristics, the current supplied to the bit terminal can be controlled more finely. For example, if the gate widths of the pMOS transistors 511, 512-1 to 512-3 are 10: 9: 8: 7, the value of the reference current Iref (Iref1 + Iref2 + Iref3) output from the bit terminal is used as the drain current of the pMOS transistor 511. Can be selected from six types of 0.7 times, 0.8 times, 0.9 times, 1.5 times, 1.6 times, 1.7 times, and 2.4 times.

  As described above, in the present embodiment, three pMOS transistors 512-1 to 5122-3 are provided for each bit terminal of the sense amplifier 150 as transistors that generate a current supplied to the bit line BL. However, it goes without saying that two or more current generating pMOS transistors may be used.

Second Embodiment Next, a second embodiment of the present invention will be described with reference to FIGS.

  This embodiment is an example of a semiconductor memory in which the reference current Iref can be set for each bit line BL.

  FIG. 7 is a block diagram schematically showing the overall configuration of the semiconductor memory 700 according to the present embodiment. In FIG. 7, the components denoted by the same reference numerals as those in FIG. 1 are the same as those in FIG. 1.

  As shown in FIG. 7, the memory matrix 710 of this embodiment includes a memory cell area 720 for trimming registers in addition to the memory cell area 110 for data storage. The memory cell area 110 for data storage is the same as the memory matrix 110 of the first embodiment. The memory cell area 720 for the trimming register is provided with one row of memory transistors having the same size as the memory cell area 110, but is not provided with the word line WL or the control line CL.

  FIG. 8 is a circuit diagram showing a configuration of the sense amplifier 740 according to the present embodiment. In FIG. 8, the components given the same reference numerals as those in FIG. 5 are the same as those in FIG.

  The sense amplifier 740 of the semiconductor memory 700 includes a current mirror circuit 810 and a read circuit 820, as in the first embodiment. However, in this embodiment, some components of the current mirror circuit 810 are provided in the memory matrix 710 and the X decoder 730 (described later). The configuration of the readout circuit 820 is the same as that of the readout circuit 520 of the first embodiment (see FIG. 6B).

  As shown in FIG. 8, the current mirror circuit 810 of this embodiment includes pMOS transistors 811, 812-1 to 812-8, 813-1 to 813-8, a resistor 814, and trimming registers 815-1 to 515. -8. The pMOS transistors 812-1 to 812-8 and 813-1 to 813-8 are provided for each bit terminal. On the other hand, each of the pMOS transistor 811, the resistor 814, and the trimming registers 815-1 to 815-8 is provided in the sense amplifier 150.

  In the pMOS transistors 811, 812-1 to 812-8, the source is connected to the power supply line VDD, and the gate is connected to the drain of the pMOS transistor 811. The resistor 814 has one end connected to the drain of the pMOS transistor 811 and the other end connected to the ground line GND. In this embodiment, the characteristics of the pMOS transistors 811, 812-1 to 812-8 are the same. The switching pMOS transistors 813-1 to 813-8 have their sources connected to the drains of the corresponding pMOS transistors 812-1 to 812-8 and the drain shared by the node N 2 (see FIG. 5) of the readout circuit 820. It is connected. In this embodiment, the pMOS transistors 813-1 to 813-8 have the same characteristics. Therefore, the drain currents Iref1, Iref2,..., Iref8 when the pMOS transistors 83-1 to 813-8 are on have the same value.

  The internal configuration of the trimming registers 815-1 to 815-8 is shown in FIGS. The trimming register 815-1 includes an nMOS transistor 901 having a floating gate structure, a selection nMOS transistor 902, a constant current source 903, and an inverter 904. However, as shown in FIG. 9, the nMOS transistor 901 is provided in the memory cell region 720, and the nMOS transistor 902 is provided in the X decoder 730. The nMOS transistor 901 has a source connected to the ground line GND, and receives a reference potential Vref from the gate. The source of the nMOS transistor 902 is connected to the drain of the nMOS transistor 901. The drain of the nMOS transistor 902 is connected to the output terminal of the constant current source 903 and the input terminal of the inverter 904 via the terminal R1. The configuration of the other trimming registers 815-2 to 815-8 is the same as that of the trimming register 815-1.

  In the semiconductor memory 700 of this embodiment, when a column address (that is, an X address) is selected, the eight trimming register nMOS transistors 901 arranged in the selected column are also selected. The current Iref supplied to the bit line BL is determined according to the stored value of the selected nMOS transistor 901. That is, in this embodiment, the trimming registers 815-1 to 815-8 can be set for each column address.

  The storage value for the nMOS transistor 901 is set, for example, at the manufacturing stage of the semiconductor memory, as in the first embodiment.

  The drain current, that is, the cell current of the memory transistor 112 (see FIG. 9) varies depending on the position in the memory cell region 110 and the like even in the same device. This is because the diameter of the tunnel window (that is, the electron injection hole to the floating gate) of the memory transistor 112 is likely to be non-uniform between the central portion and the peripheral portion of the memory cell region. This is due to the fact that the threshold value varies. On the other hand, in the semiconductor memory of this embodiment, the reference current Iref can be set for each column address, and therefore, variation in cell current in the same device can be reduced.

Third Embodiment Next, a third embodiment of the present invention will be described with reference to FIGS.

  The overall configuration of the semiconductor memory according to the present embodiment is substantially the same as that of the apparatus according to the first embodiment, and thus the description thereof is omitted. The semiconductor memory according to the present embodiment is different from the semiconductor memory according to the first embodiment in the configuration of the current mirror circuit in the sense amplifier 150.

  FIG. 11 is a circuit diagram showing a configuration of the sense amplifier according to the present embodiment. In FIG. 11, components denoted by the same reference numerals as those in FIG. 5 are the same as those in FIG. 5.

  As shown in FIG. 11, the current mirror circuit 1110 according to this embodiment includes pMOS transistors 1101-1 to 1101-5, 1102-1 to 1102-5.

  In the pMOS transistors 1101-1 to 1101-5, the source is connected to the power supply line VDD, and the gate is connected to the gate and drain of the pMOS transistor 511. The pMOS transistor 1102-1 has a source connected to the drain of the pMOS transistor 1101-1, inputs the most significant bit A11 of the address from the gate, and outputs a current Iref1 from the drain. The pMOS transistor 1102-2 is connected at the source to the drain of the pMOS transistor 1101-2, receives the second upper bit A10 of the address from the gate, and outputs the current Iref2 from the drain. The pMOS transistor 1102-3 is connected at the source to the drain of the pMOS transistor 1101-3, receives the third upper bit A9 of the address from the gate, and outputs the current Iref3 from the drain. The pMOS transistor 1102-4 is connected at the source to the drain of the pMOS transistor 1101-4, receives the fourth upper bit A8 of the address from the gate, and outputs the current Iref4 from the drain. In the pMOS transistor 1102-5, the source is connected to the drain of the pMOS transistor 1101-5, the gate is grounded, and the current Iref5 is output from the drain. The sum of the output currents Iref1 to Iref5 of the pMOS transistors 1102-1 to 1101-5 is supplied as a reference current Iref to the readout circuit 520 (see FIG. 6B).

  In the present embodiment, the ratio of the gate widths of the current supply pMOS transistors 511, 1101-1 to 1101-5 is 10: 1: 0.5: 0.25: 0.125: 10. Therefore, Iref1 to Iref5 become Iref0 / 10, Iref0 / 20, Iref0 / 40, Iref0 / 80, and Iref0 (Iref0 is the drain current of the pMOS transistor 511). Thereby, detailed control of the current Iref becomes possible.

  As described above, in this embodiment, the on / off of the switching pMOS transistors 1102-1 to 1102-4 is controlled by the upper 4 bits of the address, and the switching nMOS transistor 1102-5 is always turned on. did. Accordingly, the number of switching transistors that are turned on changes according to the upper 4 bits of the address, and the value of the reference current Iref changes accordingly. The relationship between the upper 4 bits of the address value and the reference current Iref is shown in FIG. In the Y decoder 130 (see FIG. 1) of this embodiment, the word line corresponding to the smallest upper address value is arranged at the lowest stage (position closest to the sense amplifier 150) and is the largest, as in the first embodiment. The word line corresponding to the upper address value is arranged at the uppermost stage (position farthest from the sense amplifier 150). Therefore, the reference current Iref decreases as the distance between the selected word line WL and the sense amplifier 150 increases.

  As in the first embodiment, the reference current Iref is supplied to the bit line BL via the read circuit 520 (see FIG. 6B) and the X decoder 140. Then, when the memory transistor 112 (see FIG. 2) of the selected word line is on, it flows to the ground line GND through the memory transistor 112. Therefore, when the selected memory transistor 112 is on, the resistance increases according to the length of the bit line from the sense amplifier 150 to the selected memory transistor 112. As is well known, when the current is constant, the voltage drop increases as the resistance increases. Further, the read potential of the sense amplifier (the potential of the node N2 shown in FIG. 6B) is almost determined by the sum of the ground line GND and the voltage drop value. For this reason, the read low level increases in accordance with the length of the bit line from the sense amplifier 150 to the selected memory transistor 112. On the other hand, in this embodiment, the sense amplifier 150 is configured such that the reference current Iref decreases as the distance between the selected word line WL and the sense amplifier 150 increases, so that the read low level is made uniform. be able to.

  As described above, according to the present embodiment, the reference current Iref supplied from the sense amplifier 150 to each bit line BL can be adjusted according to the distance between the sense amplifier and the selected bit. It is possible to suppress erroneous reading due to variations in device characteristics. Therefore, according to this embodiment, the yield of the semiconductor memory can be improved.

  In the present embodiment, the reference current Iref is adjusted using the upper 4 bits of the address, but it is needless to say that the upper 3 bits or less or the upper 5 bits or more may be used.

  The present invention is not limited to a semiconductor memory using a memory transistor having a floating structure, and can be applied to any kind of nonvolatile semiconductor memory.

1 is a block diagram schematically showing an overall configuration of a semiconductor memory according to a first embodiment. FIG. 2 is a circuit diagram schematically showing an internal structure of a memory matrix shown in FIG. 1. FIG. 2 is a conceptual diagram schematically showing an address structure of the semiconductor memory shown in FIG. 1. FIG. 2 is a circuit diagram schematically showing a main part structure of an X decoder shown in FIG. 1. FIG. 2 is a circuit diagram showing an internal structure of the sense amplifier shown in FIG. 1. FIG. 6A is a circuit diagram showing the internal structure of the trimming register shown in FIG. 5, and FIG. 6B is a circuit diagram showing the internal structure of the readout circuit shown in FIG. It is a block diagram which shows roughly the whole structure of the semiconductor memory which concerns on 2nd Embodiment. FIG. 8 is a circuit diagram showing an internal structure of the sense amplifier shown in FIG. 7. FIG. 9 is a circuit diagram showing an internal structure of the trimming register shown in FIG. 8. FIG. 9 is a circuit diagram showing an internal structure of the trimming register shown in FIG. 8. It is a block diagram which shows roughly the principal part structure of the semiconductor memory which concerns on 3rd Embodiment. It is a table | surface for demonstrating operation | movement of the current mirror circuit which concerns on 3rd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor memory 110 Memory matrix 120 Address buffer 130 Y decoder 140 X decoder 150 Sense amplifier

Claims (4)

A current generation circuit that generates a reference current to be supplied to the bit line is
A first transistor having a first main electrode connected to a first power line and a second main electrode and a control electrode interconnected;
A resistor having one end connected to the second main electrode of the first transistor and the other end connected to a second power supply line;
A plurality of second transistors having a first main electrode connected to the first power supply line and a control electrode connected to a control electrode of the first transistor;
A third transistor provided for each second transistor, the first main electrode being connected to the second main electrode of the corresponding second transistor, and the reference current being output from the second main electrode;
A current control circuit for individually controlling on / off of the third transistor;
A semiconductor memory comprising: The current control circuit is
A non-volatile memory transistor having a first main electrode grounded and a reference potential applied to the control electrode;
A constant current source for supplying a constant current to the second main electrode of the nonvolatile memory transistor;
An inverter that inverts the potential of the second main electrode of the nonvolatile memory transistor and applies it to the control electrode of the third transistor;
The semiconductor memory according to claim 1, further comprising: The current control circuit is
A non-volatile memory transistor having a first main electrode grounded and a reference potential applied to the control electrode;
A first main electrode connected to the second main electrode of the nonvolatile memory transistor, and a column selection transistor for inputting a column selection signal from the control electrode;
A constant current source for supplying a constant current to the second main electrode of the column selection transistor;
An inverter for inverting the potential of the second main electrode of the column selection transistor and applying it to the control electrode of the third transistor;
The semiconductor memory according to claim 1, further comprising:   The semiconductor memory according to claim 1, wherein the current control circuit is an address line.