JPH0730076A - Non-volatile semiconductor memory and operation controlling method thereof - Google Patents

Abstract

PURPOSE:To obtain a flash memory capable of increasing data rewriting frequency by a method wherein a delay means delaying the impression time of the third level voltage on a source line from that of the first and second level voltages is to be provided. CONSTITUTION:The title non-volatile semiconductor memory is provided with a word line driving means 20 to impress a selected word line 13 with the first level voltage in the first operation mode time, a substrate driving means 22 to impress the specific region of a semiconductor substrate corresponding to the selected memory cells with the second level voltage furthermore, a source line driving means 21 to impress a selected source line with the third level voltage as well as a delaying means 24 to delay the impression time of the third level voltage on the source line from that of the first and second level voltages. Through these procedures, a depletion layer is spread in the semiconductor substrate while enabling the depletion layer to be injected with electrons from a source region 3. Finally, the electrons are to be injected in a floating gate 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device capable of electrically writing and erasing, and an operation control method thereof.

[0002]

2. Description of the Related Art Conventionally, a flash memory has been known as a memory device in which data can be freely written and which can be electrically erased. As an example of this flash memory, it is composed of one transistor and is capable of electrically collectively erasing written information charges.
EPROMs are described in US Pat. No. 4,868,619 and "An.
In-System Reprogrammable
32Kx8 CMOSFlash Memory "by
Virgil Niles Kynettette a
l. , IEEE Journal of Solid-
State Circuits, vol. 23, No.
5, proposed in October 1988.

FIG. 14 is a block diagram showing a general structure of a flash memory. Referring to FIG. 14, the flash memory includes a memory cell array 101, an X address decoder 102, a Y gate 103, a Y address decoder 104, an address buffer 105, a write circuit 106, a sense amplifier 107, and an input memory. Output buffer 10
8 and control logic 109.

The memory cell array 101 has therein a plurality of memory transistors arranged in rows and columns. An X address decoder 102 and a Y gate 103 are connected to the memory cell array 101.
Rows and columns of the memory cell array 101 are selected by the X address decoder 102 and the Y gate 103. The Y-gate 103 is connected to a Y-address decoder 104 that gives column selection information. The X address decoder 102 and the Y address decoder 104 each include an address buffer 10 in which address information is temporarily stored.
5 is connected.

A write circuit 106 for performing a write operation at the time of data input and a sense amplifier 107 for determining "0" or "1" from the current value flowing at the time of data output are connected to the Y gate 103. There is. An input / output buffer 108 for temporarily storing input / output data is connected to each of the writing circuit 106 and the sense amplifier 107.

A control logic 109 for controlling the operation of the flash memory is connected to the address buffer 105 and the input / output buffer 108. The control logic 109 controls based on a chip enable signal, an output enable signal and a program signal.

FIG. 15 is an equivalent circuit diagram showing a schematic structure of the memory cell array 101 shown in FIG. A flash memory having such a memory cell array 101 is called a NOR flash memory.

Referring to FIG. 15, a plurality of word lines WL ₁ , WL ₂ , ..., WL ₃ extending in the row direction and a plurality of bit lines BL ₁ , BL ₂ , ..., BL _j extending in the column direction. And are arranged so that they intersect with each other. At the intersections of the word lines and the bit lines, memory transistors Q11, Q12, ..., Qij each having a floating gate.
Is provided.

The drain of each memory transistor is connected to each bit line. The control gate of the memory transistor is connected to each word line. The sources of the memory transistors are connected to the source lines S1, S2, ..., Si. The sources of the memory transistors belonging to the same row are connected to each other as shown in FIG.
It forms the source line.

FIG. 16 is a sectional view showing the sectional structure of one memory transistor in the NOR flash memory as described above. FIG. 17 is a schematic plan view of a NOR flash memory. FIG. 18 shows the XVI in FIG.
It is sectional drawing which follows the II-XVIII line. The structure of the NOR flash memory will be described with reference to these drawings.

Referring to FIGS. 16 and 18, n-type impurity regions, for example, drain region 111 and source region 112 are spaced apart from each other on the main surface of p-type impurity region 110 provided on the silicon substrate. Has been formed. A control gate 113 and a floating gate 114 are formed in a region sandwiched between the drain region 111 and the source region 112 so as to form a channel.

The floating gate 114 is formed on the p-type impurity region 110 with a thin tunnel oxide film 115 having a film thickness of about 100Å interposed. The control gate 113 is formed on the floating gate 114 with an insulating film 116 interposed therebetween so as to be electrically separated from the floating gate 114.

Floating gate 114 is formed of polycrystalline silicon. The control gate 113 is composed of polycrystalline silicon or a laminated structure of polycrystalline silicon and a refractory metal.

The oxide film 117 is the floating gate 1
It is formed so as to cover 14 and the control gate 113. A smooth coat film 121 is formed on the oxide film 117, as shown in FIG.

Next, referring to FIG. 17, control gates 113 are formed so as to be connected to each other and extend in the lateral direction (row direction). This control gate 11
3 constitutes the word line 113. On the other hand, the bit line 118
Are arranged so as to be orthogonal to the word line 113. The bit line 118 is electrically connected to each drain region 111 via a drain contact 120.

Bit line 118, as shown in FIG.
Are formed on the smooth coat film 121. The bit line 118 is electrically connected to the drain region 111 common to the memory transistors 122a and 122b through the drain contact 120.

Referring again to FIG. 17, source region 112 extends in the direction in which word line (control gate) 113 extends and is surrounded by word line 113 and field oxide film 119. Is formed in. The drain region 111 is also formed in a region surrounded by the word line 113 and the field oxide film 119.

Next, the operation of the NOR flash memory having the above structure will be described with reference to FIG.

First, the write operation will be described. N above
In the OR flash memory, the state in which electrons are injected into the floating gate 114 is the write state.
In the writing operation, a voltage of about 5V is applied to the drain region 111 and a voltage of about 10V is applied to the control gate 113.

At this time, the source region 112 and the p-type impurity region 110 are kept at the ground potential (0V). As a result, a current of about several hundred μA flows through the channel of the memory transistor. Among the electrons flowing from the source region 112 to the drain region 111, the electrons accelerated in the vicinity of the drain region 111 become electrons having high energy in the vicinity of the drain region 111, that is, so-called channel hot electrons.

The electrons are injected into the floating gate 114 as indicated by the arrow in FIG. 16 by the electric field generated by the voltage applied to the control gate 113. In this way, the floating gate 11
Electrons are stored in the memory cell 4, and the threshold voltage V _th of the memory transistor becomes about 8 V, for example. This state is called a written state, "0".

Next, the erase operation will be described. In the NOR flash memory described above, the state in which electrons are extracted from the floating gate 114 is the erased state. In the erase operation, a voltage of about 5 V is applied to the source region 112, and the control gate 113 is -1.
A voltage of about 0 V is applied and the p-type impurity region 110 is held at the ground potential. At this time, the drain region 111 is held in a floating state.

Then, due to the electric field generated by the voltage applied to the source region 112, the electrons in the floating gate 114 pass through the thin tunnel oxide film 115 by the tunnel phenomenon, as shown by the arrow in FIG.

In this way, the floating gate 11
By pulling out the electrons in 4, the threshold voltage V _th of the memory transistor becomes, for example, about 2V.
This state is called an erased state, which is called "1". Since the source regions 112 of the respective memory transistors are connected to each other as shown in FIG. 17, all the memories can be erased collectively by this erase operation.

Next, the read operation will be described. In the read operation, a voltage of about 5V is applied to the control gate 113 and a voltage of about 1V is applied to the drain region 111. At this time, the source region 112 and the p-type impurity region 110 are held at the ground potential. Then, the determination of "1" or "0" is made depending on whether or not a current flows in the channel region of the memory transistor.

That is, when the memory transistor is in the written state, the threshold voltage V _th is as high as about 8 V, so that a channel is not formed during reading and no current flows. On the other hand, when the memory transistor is in the erased state, the threshold voltage V _th is as low as about 2 V, so that a channel is formed and a current flows during reading.

In the NOR flash memory described above, electrons are injected into the floating gate 114 by utilizing channel hot electrons. Since the injection of electrons by this channel hot electron is inefficient, NO
The R-type flash memory has a problem of high power consumption.

Further, the above NOR type flash memory has the following problems. 18, consider, for example, a case where memory transistors 122a and 122b are sequentially selected and written.

In this case, 5 V is applied to the drain region 111.
Voltage is applied to control gate 113
A voltage of about 0V is applied. Thereby, electrons are injected into the floating gate 114 of the memory transistor 122a by the mechanism described above. That is, writing is performed.

Next, the memory transistor 122b is selected to perform the write operation. Also in this case, the same voltage as that in the above case is applied to the drain region 111 and the control gate 113 in the memory transistor 122b. At this time, as shown in FIG. 18, the memory transistor 122a and the memory transistor 122b are
And share the drain region 111.

Therefore, the memory transistor 122b
By applying a voltage to the drain region 111 at the time of writing, the electrons injected into the floating gate 114 of the memory transistor 122a may be extracted to the drain region 111 due to a tunnel phenomenon.

The phenomenon as described above is called a drain disturb phenomenon. By this drain disturb phenomenon,
Since electrons are extracted from the floating gate of the written memory transistor, the memory transistor, which should have been in the written state, may be in the erased state. That is, it causes a malfunction of the flash memory.

A NAND flash memory has been proposed as a solution to the above problems of the NOR flash memory. This NAND flash memory is, for example, a NIKKEI ELECTRONICS
1992. 2.17 (no. 547) pp. 180
~ 181.

This NAND flash memory will be described below with reference to FIGS. 19 to 21. FIG. 19
FIG. 3 is an equivalent circuit diagram of a part of a memory cell array of a NAND flash memory. FIG. 20 is a partial cross-sectional view of the memory cell array of the NAND flash memory. FIG. 21 is a sectional structural view of a memory transistor included in the NAND flash memory.

First, referring to FIG. 19, in the NAND flash memory, select gate transistor 1
39a, 139b, 139c are provided, respectively. The select gate transistors 139a and 139
One of the impurity regions b and 139c is connected to the bit lines B1, B2 and B3, and the other impurity region is connected to the memory transistors 138a, 138b and 138c.

The select gate transistor 139a selects a group of eight memory transistors 138a arranged in series in the vertical direction. Similarly, the memory cells 138b and 138c are selected by the select gate transistors 139b and 139c. One of the memory transistors 138a, 138b, 138c is a select gate transistor 123a, 123b, 123c, respectively.
Grounded through.

Next, referring to FIG. 20, the silicon substrate 1
In the p-type impurity region 130 formed in the 26, a plurality of impurity regions 127 are formed at predetermined intervals.
The floating gate 129 and the control gate 128 are provided on the region between the impurity regions 127.
A memory transistor 138a including a memory cell is formed.

Next, the structure of the memory transistor 138a will be described in more detail with reference to FIG. On the main surface of p type impurity region 130 formed on the silicon substrate, as described above, a pair of impurity regions 127 are formed at intervals. By this impurity region 127,
A channel formation region of the memory transistor is defined.
The floating gate 1 is formed on the region between the pair of impurity regions 127 with the tunnel insulating film 135 interposed.
29 are formed.

On the floating gate 129,
A control gate 128 is formed with an insulating film 136 interposed. An oxide film 137 is formed so as to cover the control gate 128 and the floating gate 129.
Are formed.

The operation of the NAND flash memory having the above structure will be described below with reference to FIGS.

First, the write operation will be described. Referring to FIG. 19, a case for writing to the memory transistor 138a is connected to, for example, a word line W _8. First, the select gate S of the select gate transistor
₂ , bit line B1, source line and p-type impurity region 35
Is held at ground potential. Then, a voltage of about 10 V is applied to the selection gate S ₁ and the bit lines B2 and B3.

Then, a voltage of about 20 V is applied to the word line W ₈ and the other word lines W _{1 to} W ₇ are held at the ground potential. Thereby, as shown by in FIG.
In the memory transistor 138a having the word line W ₈ (control gate 128), the electrons existing in the channel region are channel FN (Fowler-Nordh).
injected into the floating gate 129 by eim). As a result, writing is performed in the memory transistor 138a. This is the write state “0”, and the threshold voltage V _th of the memory transistor at this time is about 3V.

Next, the erase operation will be described. Referring again to FIG. 19, when erasing is performed, bit line B
A voltage of about 20 V is applied to 1, B2, B3, select gates S ₁ , S ₂ , and p-type impurity region 130. At this time, the word lines W _{1 to} W ₈ are held at the ground potential. As a result, as shown in FIG. 21, the floating gate 12 of the memory transistor 138a in the written state.
From 9, the electrons are extracted into the channel region by the channel FN. Thereby, the memory transistor 138a
The threshold voltage V _th is about −2V. Thereby,
It will be erased.

Next, the read operation will be described. Referring to FIG. 19 again, the case of reading from memory transistor 138a having word line W ₈ will be described.
In this case, a voltage of about 1 V is applied to the bit line B1 to keep the source line and the p-type impurity region 130 at the ground potential. Then, the word line W ₈ is kept at the ground potential, and a voltage of about 5 V is applied to the word lines W _{1 to} W ₇ . Further, a predetermined voltage is applied to the select gates S ₁ and S ₂ to turn on the select gate transistors.

Since the word line W ₈ is held at the ground potential (0 V), when the memory transistor 138a having the control gate 128 connected to the word line W ₈ is in the erased state, the memory transistor 138a is turned on, In the written state, the memory transistor 138a is turned off.

On the other hand, the memory transistor 1 having the control gate 128 connected to the word lines W _{1 to} W ₇
38a, since the word lines W ₁ to _W-7 voltage of about 5V is applied, the write state, the memory transistor 138a regardless of the erase state is ON.

Therefore, the memory transistor 1 having the control gate 128 connected to the word line W ₈
When 38a is in the erased state, current flows through the channel region of each memory transistor 138a shown in FIG. Then, this current reaches the sense amplifier through the bit line B1.

On the other hand, the memory transistor 1 having the control gate 128 connected to the word line W ₈
When 38a is in the written state, the threshold voltage _Vth of this memory transistor 138a is increased to about 3V, so that no current flows through this memory transistor 138a. That is, the current is not guided to the sense amplifier. When the sense amplifier senses a current, the selected memory transistor is determined to be in the erased state, and when the sense amplifier does not sense the current, the selected memory transistor is determined to be in the written state.

The injection of electrons into the floating gate by the channel FN is more efficient than the case of using channel hot electrons. Therefore, NAN
The D-type flash memory can consume less power than the NOR-type flash memory.

The NAND type flash memory uses the channel FN at the time of writing. Therefore, it becomes unnecessary to apply a high voltage to the drain region of the memory transistor. As a result, it is possible to effectively avoid the drain disturb phenomenon which has been a problem in the NOR flash memory.

However, the above NAND flash memory also has the following problems. That is, in the NAND flash memory described above, it is necessary to pass a current through all of the plurality of memory transistors arranged in series during the read operation. Therefore, there is a problem that the read operation becomes slow. Moreover, since a high voltage of 20 V is used during writing and erasing, a circuit for generating such a high voltage is required in the device. Therefore, there is also a problem that high integration becomes difficult.

[0052]

On the other hand, the above N
As an improved example capable of solving the problems of the OR type flash memory and the NAND type flash memory, DI
NOR type (Divided bit line NO
R) A nonvolatile semiconductor memory device called a flash memory is disclosed in Japanese Patent Application No. 5-1 by the same applicant as the present applicant.
No. 03560 is proposed. Below, this DINOR
The flash memory will be described.

FIG. 22 is a block diagram showing a schematic structure of the DINOR type flash memory described above. Referring to FIG. 22, memory cell array 166 is divided into a plurality of blocks (block 0 to block n). This memory cell array 166 is formed in the p well region.

A plurality of main bit lines MB0 and MBi are arranged in the memory cell array 166. The main bit lines MB0 and MBi are supplied to the sense amplifier 15 via Y gate transistors YG0 and YGi in the Y gate 167, respectively.
7 and write circuit 156.

A predetermined number of sub bit lines (not shown) are provided for main bit lines MB0 and MBi. Word lines WL0 and WLi are arranged so as to intersect with the sub bit line. Memory transistors are provided at the intersections of the sub bit lines and the word lines WL0 and WLi.

The drain region of each memory transistor is connected to the corresponding sub-bit line, and the control gate of each memory transistor is connected to the corresponding word line WLi. The source region of the memory transistor is connected to the source line (not shown).

In the memory cell array 166, select gate transistors are formed in addition to the memory transistors. The sub bit line is connected to the main bit line via the select gate transistor. A source switch 161 is connected to the above source line.

Address buffer 160 receives an externally applied address signal, applies an X address signal to X decoder 163, and provides a Y address signal to Y decoder 158. The X decoder 163 selects one of the plurality of word lines WL _{0 to} WL _i in response to the X address signal. Y decoder 158 senses a plurality of main bit lines MBo to MBi in response to a Y address signal.
And write circuit 156.

At the time of reading, the sense amplifier 157 detects the data read on the main bit MBo and MBi lines,
The data is output to the outside via the data input / output buffer 151.
At the time of writing, externally applied data is applied to write circuit 156 via data input / output buffer 151, and write circuit 156 follows main bit line M in accordance with the data.
A program voltage is applied to Bo to MBi.

High voltage generation circuits 154 and 155 receive power supply voltage Vcc (for example, 5 V) from the outside and generate high voltages. Negative voltage generating circuits 152 and 153 receive power supply voltage Vcc from the outside and generate a negative voltage. Verify voltage generating circuit 164 receives power supply voltage Vcc supplied from the outside.
In response, a predetermined verify voltage is applied to the selected word line WLi at the time of verify.

The well potential generating circuit 165, when erasing,
A high voltage is applied to the p well region (memory cell array 166). Select gate decoder 162 selectively activates select gates SG _{0 to} SG _i in response to a part of the address signal from address buffer 160. The source switch 161 applies a high voltage to the source line at the time of erasing. Write / erase control circuit 150 controls the operation of each circuit in response to a control signal applied from the outside.

Next, the operation of the DINOR type flash memory having the above configuration will be described. First, the erase operation will be described. In the DINOR type flash memory, the state in which electrons are injected into the floating gate is the erased state. Then, first, the write / erase control circuit 150
A control signal designating a block erasing operation is applied to. Thereby, high voltage generation circuit 155 and negative voltage generation circuit 152 are activated.

The high voltage generation circuit 155 is the X decoder 163.
A high voltage (10 V) is applied to. The X decoder 163 applies a high voltage (10V) to the word lines of the selected block and 0V to the other word lines.

Negative voltage generating circuit 152 includes source switch 161, Y decoder 158 and well potential generating circuit 1.
Apply a negative voltage to 65. Y decoder 158 is Y gate 1
A negative voltage is applied to the Y gate transistors YGo and YGi in 67. As a result, the main bit lines MBo and MBi are brought into a floating state.

Well potential generating circuit 165 applies a negative voltage (-8V) to the p well region (memory cell array 166). The select gate decoder 162 turns off the selected select gate SGi. At this time, a negative voltage (-8V) is applied to the source line in the selected block via the source switch 161.

In this way, the above voltages are applied to the memory transistors in the selected block. As a result, all the memory transistors in the selected block are in the erased state.

Next, the write operation will be described. First,
A control signal designating a program operation is applied to write / erase control circuit 150. Thereby, high voltage generating circuit 154 and negative voltage generating circuit 153 are activated. The negative voltage generation circuit 153 gives a negative voltage to the X decoder 163. The X decoder 163 responds to the X address signal supplied from the address buffer 160, to the word line WLi.
Select. Then, a negative voltage (-8V) is applied to the selected word line WLi, and 0V is applied to the non-selected word line WLi.
Is applied.

The high voltage generation circuit 154 includes a Y decoder 15
8, write circuit 156 and select gate decoder 16
2 is given a high voltage. First, data “0” is externally applied to the write circuit 156 via the data input / output buffer 151 and latched. The Y decoder 158 responds to the Y address signal provided from the address buffer 160 to select the selected Y gate transistor Y in the Y gate 167.
A high voltage is applied to Gi and 0V is applied to the non-selected Y gate transistor YGi. As a result, the selected Y gate transistor YGi turns on.

Write circuit 156 applies a program voltage (5 V) corresponding to data "0" to main bit line MBi via Y gate transistor YGi. Further, the select gate decoder 162 turns on the selected select gate SGi and turns off the unselected select gate SGi.
Turn i off.

As a result, a predetermined sub bit line is connected to main bit line MBi. The source switch 161 puts the source line in a floating state. The well potential generation circuit 165 applies 0V to the p well region (memory cell array 166).

In this way, the above voltages are applied to the predetermined memory transistor. As a result, electrons are extracted from the floating gate of this memory transistor, and the threshold voltage of the memory transistor drops. At this time, 0V is applied to the drain region of the memory transistor connected to the non-selected bit line. As a result, the threshold voltage of the non-selected memory transistor is not affected by the write operation to the selected memory transistor.

Next, the read operation will be described. First,
A control signal designating a read operation is applied to write / erase control circuit 150. The X decoder 163 selects the word line WLi in response to the X address signal supplied from the address buffer 160, and applies 3V thereto. At this time, the non-selected word line WLi is kept at 0V.

The select gate decoder 162 turns on the selected select gate SGi and turns off the non-selected select gate SGi. Y decoder 15
Reference numeral 8 turns on the Y gate transistor YGi in the Y gate 167 in response to the Y address signal provided from the address buffer 160. The source switch 161 applies a ground potential to a predetermined source line.

In this way, the above predetermined voltage is applied to the selected memory transistor. Thereby, if the state of the memory transistor is "1", the read current flows through the main bit line MB _i . This read current is detected by the sense amplifier 157 and output to the outside through the data input / output buffer 151.

Next, referring to FIGS. 23 to 26, the above D
The structure and operation of the INOR type flash memory will be described in more detail. FIG. 23 is a schematic diagram of a DINOR type flash memory.

Referring to FIG. 23, p-type silicon substrate 18
At 0, a memory cell array area and a peripheral area are provided. In the memory cell array area, the memory transistor 1
87a, 187b, 187c, 187d are formed at intervals. The n-type source region 18 is formed in the memory cell array region of the main surface of the p-type silicon substrate 180.
4a, 184b and n-type drain regions 185a, 18
5b are formed at intervals.

The source region 184a becomes a common source region for the memory transistors 187a and 187b. Also,
The source region 184b is connected to the memory transistors 187c and 1
It becomes a common source region with 87d. Drain region 18
5a serves as a drain region common to the memory transistors 187b and 187c, and the drain region 185b serves as a drain region of the memory transistor 187d. The memory transistors 187a, 187b, 187c, 187
d has a floating gate 189 and a control gate 188, respectively.

Select gate transistor 186 is formed in the memory cell array region. The select gate transistor 186 has source / drain regions 183a and 183b. The source / drain region 183b is the memory transistor 187.
It also plays the role of the drain region of a.

Memory transistors 187a, 187b,
Sub-bit lines 190 made of polycrystalline silicon are formed on 187c and 187d. Sub bit line 190
Are connected to the above-mentioned source / drain regions 183b. The branch line 191a branched from the sub bit line 190 is connected to the drain region 185a, and the branch line 191b is connected to the drain region 185b.

A main bit line 192 made of aluminum or the like is formed on the sub bit line 190. The main bit line 192 is connected to the source / drain region 183 described above.
connected to a.

In the silicon substrate 180, a p well region 182 is formed so as to surround the memory cell array region. An n well region 181 is formed so as to surround this p well region 182. A MOS transistor 193 is formed in the peripheral region.

Next, with reference to FIG. 24, an example of the structure of the memory cell array region of the DINOR type flash memory will be described in more detail. FIG. 24 is a partial cross-sectional view of the memory cell array region of the DINOR type flash memory.

Referring to FIG. 24, p-type silicon substrate 20
At 1, a p-well region 210 is formed. Memory transistors 250 to 25 are formed on the p-well region 210.
7, 261, 262, select gate transistor 25
9, 260 are formed respectively.

In the p well region 210, an n type source region 223 and an n type drain region 224 of each memory transistor are formed at intervals. The select gate transistors 259 and 260 share the n-type impurity region 249.

Each memory transistor and select gate transistor is covered with a silicon oxide film 247. The region on the source region 223 is blocked by the silicon oxide film 247. On the other hand, the region above the drain region 224 and the impurity region 249 is the silicon oxide film 24.
Not blocked by 7. Each memory transistor has a floating gate 219 and a control gate 2
Equipped with 20.

The drain regions 224 of the memory transistors 250 to 257 are electrically connected by one sub bit line 227a. Memory transistor 26
The drain regions 224 of 1 and 262 are electrically connected by one sub-bit line 227b.

Impurity region 249 is electrically connected to connection conductive layer 248. In addition, the field oxide film 20
A dummy gate transistor (dummy memory transistor) 258 is formed on the gate electrode 6.

An interlayer insulating film 245 is formed on sub bit lines 227a and 227b. Interlayer insulating film 245
A main bit line 233 is formed on the top. Main bit line 23
3 is electrically connected to the connection conductive layer 248. An interlayer insulating film 246 is formed on the main bit line 233. Aluminum wirings 238a and 238 are formed on the interlayer insulating film 246.
b, 238c, 238d, 238e, 238f, 238
g are formed at intervals.

On the other hand, in the p-type silicon substrate 201, p
An n well region 207 is formed so as to cover the well region 210.

Next, the structure of the memory cell array region will be described with reference to FIG. FIG. 25 is an equivalent circuit diagram of the memory cell array region shown in FIG.

Referring to FIG. 25, in the embodiment shown in this figure, eight memory transistors 250 and 25 are provided.
1,252,253,254,255,256,257
Each drain region of is connected to the sub-bit line. The source region of each memory transistor is connected to the source line. The selection gate 1 connects / disconnects the main bit line and the sub bit line. Word lines 1-8
Serves as a control gate of each memory transistor.

Next, the structure and operation of the memory transistor will be described in more detail with reference to FIGS. FIG. 26 is a sectional view showing a memory transistor included in the DINOR type flash memory shown in FIG.

Referring to FIG. 26, a tunnel insulating film 213 is formed between p well region 210 and floating gate 219. An insulating film 215 made of an ONO film or the like is formed between the floating gate 219 and the control gate 220.

Next, referring to FIGS. 24 to 26,
When collectively erasing the memory transistors 250 to 257, keep the main bit line 233 in a floating state,
The select gate transistor 259 is turned off. As a result, the sub bit line 227a also becomes in a floating state.

Then, the source line and p-well region 21
A voltage of about −10 V is applied to 0. Then, a voltage of about 10 V is applied to the word lines 1 to 8 (the control gate 220 of each memory transistor whose drain regions are electrically connected to each other by the sub-bit line 227a).

As a result, as shown in FIG. 26, electrons in the channel region of the memory transistor are injected into the floating gate 219 by the channel FN phenomenon which is one of the tunnel effects. As a result, the value of the threshold voltage V _th of the memory transistor is up to 6
It becomes about V. This is the erased state.

Next, the write operation will be described. For example, to set the memory transistor 257 to the write state “0”, the select gate transistor 259 is turned on and a voltage of about 5 V is applied to the main bit line 233. As a result, the voltage of the sub bit line 227a also becomes about 5V.

Then, the p well region 210 is kept at the ground potential, and the source line is brought into a floating state. Further, a voltage of about −10 V is applied to the word line 8 to keep the word lines 1 to 7 at the ground potential.

As a result, as shown in FIG. 26, the electrons accumulated in the floating gate 219 of the memory transistor 257 are extracted to the drain region 224 by the drain FN phenomenon which is one of the tunnel effects. As a result, the threshold voltage V _th of the memory transistor 257 becomes about 1V. This is the write state "0".

Next, the read operation will be described. For example, when reading the memory transistor 257, the select gate transistor 259 is turned on and the main bit line 23
A voltage of about 1 V is applied to 3. Then, the source line and the p well region 210 are kept at the ground potential.

Then, a voltage of about 3 to 5 V is applied to the word line 8 to hold the word lines 1 to 7 at the ground potential. At this time, if the memory transistor 257 is in the erased state “1”, no channel is formed and no current flows through the bit line. On the other hand, the memory transistor 2
When 57 is in the written state "0", a channel is formed and a current flows through the bit line. Thereby, the write state / erase state is determined.

As described above, in the DINOR type flash memory, a negative voltage is applied to the p well region 210. Since there is the n-well region 207 around the p-well region 210, the p-well region 210 and the n-well region 207 are in the reverse bias state even if a negative voltage is applied. That is, even if a negative voltage is applied to the p well region 210, no voltage is applied to the peripheral circuit formation region.

In the erase operation, the p well region 21
A negative voltage is applied to 0, and a positive voltage is applied to the selected word line (control gate 220). As a result, the p-well region 210 and the control gate 220 are reduced while reducing the absolute value of the voltage applied to each component.
The potential difference between them is relatively large. As a result, it becomes possible to cause the channel FN effect as described above.

As shown in FIG. 24, sub-bit line 227a is connected to each drain region 224 of memory transistors 250-257. For this reason,
A large amount of read current can be taken during the read operation.
As a result, the read operation can be performed at a higher speed than that of the NAND flash memory.

Further, as shown in FIG. 26, since the write operation is performed by using the drain FN, it is possible to perform the write operation with higher efficiency than in the case of using channel hot electrons. . This makes it possible to reduce power consumption.

As described above, the DINOR flash memory is the NOR flash memory and the NAN.
It has characteristics that can solve the problems of the D-type flash memory. However, this DINOR type flash memory also has the following problems.

The problem will be described with reference to FIGS. 27 to 29. FIG. 27 is a timing chart showing a voltage pulse applied to the control gate (word line), the source line and the p-well region (substrate) at the time of erasing in the DINOR type flash memory described above. FIG. 28 is a diagram showing the relationship between the erase time and the threshold voltage V _th in the DINOR flash memory described above.
FIG. 29 is a diagram showing the relationship between the threshold voltage V _th and the number of times of rewriting in the DINOR type flash memory described above.

First, referring to FIG. 27, the above DINOR
In the flash memory of the type, at the time of erasing, a high voltage of about 10 V was applied to the control gate, and a voltage of about -8 V was simultaneously applied to the source line and the p well region (substrate). Therefore, at the time of erasing, a channel is formed between the source / drain of the memory transistor, and the electrons flowing in the channel receive the energy of the electric field near the drain and are injected into the floating gate.

As a result, as shown in FIG. 27, P
Even if a negative voltage of about -8 V was applied to the well (substrate), a relatively high voltage of about 10 V had to be applied to the control gate, though not as much as the NAND flash memory described above.

Therefore, the DINOR type flash memory
Power supply voltage V of about 5V _CCFrom about 10V
Complex voltage boost circuit for generating relatively high voltage
A road was needed. It is necessary to form such a booster circuit
Can be said to have an adverse effect on high integration.

In addition, since each voltage shown in FIG. 27 is applied to the DINOR type flash memory at the time of erasing, a high electric field is applied to the tunnel insulating film of the memory transistor. Therefore, the number of times of rewriting is inferior to that of the NOR flash memory or the NAND flash memory. More specifically, as shown in FIG. 29, it can be seen that the threshold voltage V _th of the memory transistor is changing after rewriting about 10,000 times.

Next, referring to FIG. 28, the above-mentioned DINO
In the R-type flash memory, it takes about 10 ^-2 seconds for the threshold voltage of the memory transistor to reach about 7 V by performing the erase operation. From the viewpoint of improving the performance of the flash memory, it can be said that it is preferable that the operation time of the flash memory is short.

The present invention has been made to solve the above problems. An object of the present invention is to provide a flash memory and an operation control method thereof that can improve the number of times data is rewritten.

Another object of the present invention is to provide a non-volatile semiconductor memory device and its operation control method capable of improving the performance by speeding up the operation of injecting electrons into the floating gate. .

Still another object of the present invention is to provide a non-volatile semiconductor memory device operable at a low voltage and an operation control method thereof.

Still another object of the present invention is to provide a nonvolatile semiconductor memory device having a structure advantageous for high integration.

[0117]

According to one aspect, a nonvolatile semiconductor memory device according to the present invention corresponds to memory cells formed on a semiconductor substrate and arranged in a plurality of rows and a plurality of columns, and corresponding to the plurality of rows. It includes a plurality of word lines provided and a source line commonly provided to the plurality of memory cells. Each of the memory cells includes a control gate connected to the corresponding word line, an impurity region connected to the source line, and a floating gate. The nonvolatile semiconductor memory device according to the present invention further includes a word line drive means for applying a voltage of a first level to a word line selected in the first operation mode, and a first line
Substrate driving means for applying a second level voltage to a predetermined region of the semiconductor substrate corresponding to the memory cell selected in the first operation mode, and a third level voltage for the source line selected in the first operation mode. A source line drive means for applying a voltage, and a timing of applying a first level voltage to the word line and a timing of applying a second level voltage to a predetermined region of the semiconductor substrate in the first operation mode, And a delay means for delaying the application timing of the third level voltage to the source line.

In the nonvolatile semiconductor memory device described above, preferably, the pulse width of the voltage pulse of the third level applied to the source line is applied to the word line and the predetermined region of the semiconductor substrate. Further provided is pulse control means for making the pulse width shorter than the voltage pulse of the level. Also, this pulse control means is preferably 1
Alternatively, it has means for applying a plurality of third level voltage pulses to the source line.

In another aspect, the nonvolatile semiconductor memory device according to the present invention has memory cells formed on a semiconductor substrate and arranged in a plurality of rows and a plurality of columns, and a plurality of words provided corresponding to the plurality of rows. A line, a plurality of bit lines provided corresponding to a plurality of columns, and a source line commonly provided to the memory cells. Each of the plurality of memory cells described above has a control gate connected to a corresponding word line,
It includes a drain connected to the corresponding bit line, a source connected to the source line, and a floating gate. Then, by injecting electrons into the floating gate, the erased state is obtained, and by extracting electrons from the floating gate, the written state is obtained. In another aspect, the nonvolatile semiconductor memory device according to the present invention is premised on having the above configuration.

This nonvolatile semiconductor memory device is
Further, word line drive means for applying a positive voltage to the selected word line in the erase mode, and substrate drive means for applying a negative voltage to a predetermined region of the semiconductor substrate corresponding to the memory cell selected in the erase mode. Source line drive means for applying a negative voltage to the selected source line in the erase mode, and the timing of applying the positive voltage to the word line and the timing of applying the negative voltage to the predetermined region of the semiconductor substrate in the erase mode On the other hand, the delay means for delaying the application timing of the negative voltage to the source line is provided.

According to one aspect of the operation control method for a nonvolatile semiconductor memory device according to the present invention, the nonvolatile semiconductor memory device has a plurality of memory cells formed on a semiconductor substrate and arranged in a plurality of rows and a plurality of columns. Each of the memory cells includes a plurality of word lines provided corresponding to a row and a source line commonly provided to the plurality of memory cells, and each memory cell has a control gate connected to the corresponding word line and a source line. It is assumed that the structure has a connected impurity region and a floating gate.

According to the operation control method of the non-volatile semiconductor memory device, the voltage of the first level is applied to the word line selected in the first operation mode, and the semiconductor corresponding to the selected memory cell is applied. A second level voltage is applied to a predetermined area of the substrate. Then, in the first operation mode,
The first and second lines are formed in a predetermined region of the word line and the semiconductor substrate.
After the voltage of the level is applied, the voltage of the third level is applied to the selected source line.

A voltage of the first polarity is preferably applied to the word line. Further, the voltage of the second polarity is preferably applied to the predetermined region of the semiconductor substrate. Further, the voltage of the second polarity is preferably applied to the source line.

The source line is preferably the word line and the above-mentioned first and second regions in a predetermined region of the semiconductor substrate.
While the voltage of the level is applied, one or more voltage pulses of the third level are applied.

The application time of the voltage of the above third level is
Preferably, it is shorter than the application time of the first and second voltages.

In another aspect, the operation control method of the non-volatile semiconductor memory device according to the present invention is based on the premise that the non-volatile semiconductor memory device has the following structure. That is, the nonvolatile semiconductor memory device includes memory cells formed on a semiconductor substrate and arranged in a plurality of rows and a plurality of columns, a plurality of word lines provided corresponding to the plurality of rows, and a plurality of word lines provided corresponding to the plurality of columns. A plurality of bit lines and a source line commonly provided to the memory cells. Each of the plurality of memory cells includes a control gate connected to the corresponding word line, a drain connected to the corresponding bit line, a source connected to the source line, and a floating gate. Then, by injecting electrons into the floating gate, the erased state is set, and by extracting electrons from the floating gate, the written state is set.

The nonvolatile semiconductor memory device having the above structure applies a positive voltage to the selected word line in the erase mode, and applies a negative voltage to a predetermined region of the semiconductor substrate corresponding to the selected memory cell. To do. Then, after applying the positive voltage to the word line and applying the negative voltage to the predetermined region of the semiconductor substrate as described above, the negative voltage is applied to the selected source line.

[0128]

The nonvolatile semiconductor memory device according to the present invention is
Equipped with a delay means. This makes it possible to delay the application timing of the voltage to the word line and the predetermined region of the semiconductor substrate and the application timing of the voltage to the source line. As a result, the depletion layer is expanded in the semiconductor substrate by applying a predetermined voltage to the word line and a predetermined region of the semiconductor substrate, and in that state, a predetermined voltage is applied to the source line to remove the depletion layer from the impurity region (source region). It becomes possible to inject electrons into the depletion layer.

The electrons thus injected from the impurity region into the depletion layer are accelerated by the electric field in the depletion layer generated by applying a predetermined voltage to the word line and a predetermined region of the semiconductor substrate, and are injected into the floating gate. To be done.

As a result, it is possible to lower the voltage applied to the word line as compared with the case of the channel FN in the DINOR type flash memory described above. Thereby, the electric field strength applied to the tunnel insulating film between the semiconductor substrate and the floating gate can be reduced, and the number of times of rewriting can be improved.

Since the voltage applied to the word line can be lowered, it is possible to simplify the high voltage generating circuit or omit the formation of the high voltage generating circuit. As a result, a nonvolatile semiconductor memory device advantageous for high integration can be obtained.

Furthermore, by shifting the timing of applying the voltage to the source line as described above, the erasing time can be shortened as compared with the case of the DINOR type flash memory. As a result, it is possible to obtain a high-performance nonvolatile semiconductor memory device.

According to the operation control method of the nonvolatile semiconductor memory device of the present invention, the predetermined voltage is applied to the source line after applying the predetermined voltage to the predetermined region of the word line and the semiconductor substrate. As a result, as in the case described above, it becomes possible to extremely efficiently inject electrons into the floating gate.

When a plurality of pulses of a predetermined voltage are applied to the source line, the threshold voltage of the memory cell can be easily increased.

Further, by delaying the timing of applying the voltage to the source line with respect to the timing of applying the voltage to the word line and the predetermined region of the semiconductor substrate, electrons can be injected into the floating gate by the substrate hot electron phenomenon. . As a result, it becomes possible to shorten the application time of the voltage to the source line when injecting electrons into the floating gate, as compared with the conventional case. This makes it possible to shorten the operation time for injecting electrons into the floating gate. As a result, a high-performance nonvolatile semiconductor memory device can be obtained.

[0136]

Embodiments of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram conceptually showing the characteristic structure of a flash memory in an embodiment based on the present invention. First, the characteristic configuration of the flash memory according to the present invention will be described with reference to FIG.

Referring to FIG. 1, a memory transistor in a flash memory according to the present invention has a p-type impurity region 1 formed in a semiconductor substrate and an n-type impurity region 1 formed on the surface of p-type impurity region 1. The source region 3 and the drain region 5, the tunnel insulating film 7 formed on the region between the source region 3 and the drain region 5, the floating gate 9 formed on the tunnel insulating film 7, and the floating region. A control gate (word line) 13 formed on the gate 9 via an insulating film 11 is provided.

A word line drive means 20 for applying a predetermined voltage to the control gate (word line) 13 is connected to the control gate 13. Further, the source region 3 is connected to a source line drive means 21 for applying a predetermined voltage to the source region 3. In addition, in the p-type impurity region 1, this p
Substrate drive means 22 for applying a predetermined voltage to the type impurity region 1 is connected.

The word line drive means 20, the source line drive means 21, and the substrate drive means 22 are connected to the pulse control means 23. The pulse control means 23 is for controlling the pulse of a predetermined voltage applied to the word line drive means 20, the source line drive means 21, and the substrate drive means 22.

Inside the pulse control means 23, a pulse width conversion means 25 and a delay means 24 are provided. The pulse width converter 25 converts the pulse width of the voltage pulse output from the pulse controller 23. Also,
By the delay means 24, the word line drive means 20, the substrate drive means 22 or the source line drive means 21.
The timing of the pulse signal output to is controlled.

An operation of injecting electrons into floating gate 9 in the flash memory having the above structure will be described. First, the word line drive means 20 and the substrate drive means 22 are used to control the control gate 13
And a predetermined voltage is applied to the p-type impurity region 1. Then, by the delay means 24, the word line drive means 20
The application timing of the predetermined voltage to the source region 3 by the source line drive means 21 is delayed by a predetermined time from the application timing of the voltage by the substrate drive means 22.

At this time, the pulse width of the voltage applied from the source line driving means 21 to the source region 3 is larger than the pulse width of the voltage applied by the word line driving means 20 and the substrate driving means 22 by the pulse width converting means 25. Is also considered short. Thereby, the electrons in the p-type impurity region 1 are injected into the floating gate 9.

Next, the structure of the flash memory according to the embodiment of the present invention having the above structure will be described more specifically with reference to FIG. FIG. 2 is a block diagram showing the configuration of a flash memory in one embodiment according to the present invention.

The flash memory in this embodiment is an application of the present invention to a DINOR type flash memory. Referring to FIG. 2, the difference between the configuration of the flash memory in this embodiment and the configuration of the DINOR type flash memory shown in FIG. 22 is that the flash memory in this embodiment includes a negative voltage pulse generation circuit 59. And having a V _WR generation circuit 55 instead of the high voltage generation circuit 155.

The negative voltage pulse generating circuit 59 is connected to the negative voltage generating circuit 52 and the source switch 61.
The negative voltage pulse generation circuit 59 is also connected to the write / erase control circuit 50. Then, in response to the signal from the write / erase control circuit 50, the negative voltage pulse generation circuit 59 transmits a voltage pulse having a predetermined pulse width at a predetermined time to the source line through the source switch 61.

By having the negative voltage pulse generating circuit 59, the timing of applying the voltage to the word line WLi or the p-type impurity region (memory cell array 66) and the timing of applying the voltage to the source line are shifted. It becomes possible.

The above V _WR generation circuit 55 is connected to the write / erase control circuit 50 and the X decoder 63. The V _WR generation circuit 55 is for generating a voltage applied to the word line WLi when performing a read operation.

[0148] Therefore, when the power supply voltage V _CC is 3V is, this V _WR generating circuit 55, the power supply voltage V _CC
Is boosted to generate a read voltage (V _WR ) of about 5V. Then, the voltage is transmitted to the selected word line WLi through the X decoder 63.

When the power supply voltage V _CC is 5V, the V _WR generation circuit 55 is a step-down circuit. That is, the voltage (about 3 V) applied to the word line WLi when injecting electrons into the floating gate (performing the erase operation).
_Will function as a circuit for generating from the power supply voltage V _CC .

The other structure is similar to that of the DINOR type flash memory shown in FIG. That is, the flash memory according to the present embodiment includes the write / erase control circuit 50, the data input / output buffer 51, the negative voltage generation circuits 52 and 53, the high voltage generation circuit 54, and the write circuit 5.
6, sense amplifier 57, Y decoder 58, address buffer 60, source switch 61, select gate decoder 62, X decoder 63, verify voltage generation circuit 64
And a well potential generation circuit 65 connected to a memory cell array (p-type impurity region) 66 in which a memory transistor is formed.

Next, the correspondence between FIG. 1 and FIG. 2 will be described. The source line drive means 21 in FIG. 1 corresponds to the negative voltage generation circuit 52, the negative voltage pulse generation circuit 59, and the source switch 61. The word line drive means 20 in FIG. 1 corresponds to the negative voltage generation circuit 53, the V _WR generation circuit 55 and the X decoder 63. The substrate drive means 22 corresponds to the negative voltage generating circuit 52 and the well potential generating circuit 65. The pulse control means 23 corresponds to the write / erase control circuit 50.

Next, the erase operation of the flash memory shown in FIG. 2 will be described. FIG. 3 is a flow chart for explaining the erase operation of the flash memory shown in FIG. FIG. 4 is a flow chart for explaining an erase operation and a verify operation of the flash memory shown in FIG.

First, the erase operation will be described with reference to FIG. Referring to FIG. 3, first, a block address is input to select a block in memory cell array 66 (step S10). And 0 on the source line
V is applied (step S11).

Next, a voltage of -8V is applied to the p-well (p-type impurity region) in which a predetermined memory transistor is formed, and a voltage of 3V is applied to all word lines WLi in the selected block. At this time, 0 V is applied to the non-selected word line WLi.
Is applied. Further, a voltage of -8V is applied to the select gate (step S12). As a result, the depletion layer in the p-type impurity region is expanded.

Then, after a lapse of a predetermined time, a voltage pulse of -8 V is applied to the source line in the selected block (step S13). As a result, electrons are injected from the source region into the p-type impurity region. Then, it is determined whether or not the number of voltage pulses applied to the source line has reached a designated number (step S14), and when the number of designated pulses has been reached, resetting is performed (step S15), and the erase operation is completed. To do. If the number of specified pulses has not been reached, a voltage pulse of -8 V is input again to the source line in the selected block.

Next, with reference to FIG. 4, the erase operation when the verify operation is performed will be described. Similar to the above case, a predetermined block is selected by inputting a block address (step S20). Then, 0 V is applied to the source line (step S21).
In this state, a voltage of -8V is applied to the p-well (p-type impurity region), and 3V is applied to all word lines WLi in the selected block.
Voltage is applied. Further, 0V is applied to the non-selected word line, and a voltage of -8V is applied to the select gate (step S22).

Then, after a lapse of a predetermined time, a voltage pulse of -8 V is input to the source line in the selected block (step S23). Then, the voltage applied to each of the above elements is released, and the initial state is restored (step S24).

Then, it is determined whether or not the number of pulses applied to the source line has reached the designated number of pulses (step S).
25). When the number of designated pulses is reached, the erase operation is finished.

On the other hand, if the specified number of pulses has not been reached, the verify voltage is applied to the selected word line WLi (step S26). Then, it is confirmed whether all the memory transistors in the selected block are off (step S27). Then, when all the memory transistors in the selected block are in the off state, the erase operation ends. However, when all the memory transistors in the selected block are not in the off state, the above erasing operation is repeated again.

Next, using FIGS. 5 to 10 and Table 1,
The erase operation of the flash memory according to the present invention will be described in more detail. Table 1 shows an example of voltage application conditions during each operation of the flash memory in this embodiment.

[0161]

[Table 1]

Referring to Table 1, the voltage application conditions at the time of writing and reading of the flash memory in this embodiment are D
The same as in the case of the INOR type flash memory, but the voltage application condition at the time of erasing is different. As shown in Table 1,
According to the present invention, the voltage (V _CG ) applied to the word line at the time of erasing is 3 V, which is considerably lower than that in the DINOR type flash memory. The reason and its effect will be described later in detail.

FIG. 5 shows the control gate (word line).
3 is a timing chart showing a voltage (V _CG ) applied to a source, a voltage (V _S ) applied to a source line, and a voltage (V _SUB ) applied to a p-well (p-type impurity region). FIG. 6 is a modification of the timing chart shown in FIG. 7 to 10 are schematic cross-sectional views for explaining the mechanism of the erase operation of the memory transistor when a predetermined voltage is applied to each element at the timing shown in FIG.

First, referring to FIGS. 5 and 7, control gate (word line) voltage V _CG is 0 V and source voltage V is
_{When S} is 0 V and the p-well (substrate) voltage V _SUB is 0 V, as shown in FIG. 7, the vicinity of the junction surface between the source region 3 and the drain region 5 and the p-type impurity region (p-well) 1 The depletion layer 2 exists only in the area.

Next, referring to FIGS. 5 and 8, 3V is applied to control gate 13 and -8V is applied to p-type impurity region 1. As a result, as shown in FIG. 8, the interface between the p-type impurity region 1 and the source region 3 and the drain region 5 is reverse-biased. As a result, the depletion layer 2 expands.

Then, as shown in FIG. 5, the control gate voltage V _CG and the p-well (substrate) voltage V _SUB become steady after a predetermined time t1 has elapsed. After reaching this stationary state, applying a source voltage V _S of -8V to the source region 3. At this time, the drain region 5 is held in a floating state or -8V is applied. As a result, as shown in FIG.
Electrons are injected into the depletion layer 2 from.

The electrons are accelerated by the electric field in the depletion layer 2, pass through the tunnel insulating film 7, and are injected into the floating gate 9. As described above, since the electrons can be injected into the floating gate 9 by utilizing the electric field in the depletion layer 2, the control gate voltage V _CG is shown in Table 1.
And, as shown in FIG. 5, it is possible to reduce the voltage to about 3V. (Substrate Hot Electron Phenomenon) As a result, it becomes unnecessary to use a high voltage of about 10 V at the time of erasing as in the case of the DINOR type flash memory. As a result, it is not necessary to provide a complicated circuit for generating the above high voltage in the flash memory. As a result, a flash memory advantageous for high integration can be obtained. Further, since the electric field strength applied to the tunnel insulating film 7 can be reduced as compared with the case of the DINOR type flash memory, the number of times of rewriting can be improved.

Now, referring to FIG. 5 again, the application timing of the source voltage V _S as described above will be described. As described above, the source voltage V _S is equal to the control gate voltage V _CG
And p-well (substrate) voltage V _SUB is applied after the steady state. More specifically, as shown in FIG. 5, after the point a1 in the pulse waveform of the control gate V _CG and after the point a3 in the pulse waveform of the p-well (substrate) V _SUB , the pulse of the source voltage V _S It is sufficient to control so that the point a2 in the waveform exists.

Therefore, by the above mechanism,
It becomes possible to effectively inject electrons into the floating gate 9. The time t2 from point a2 of the pulse waveform of the source voltage V _S to the source voltage V _S becomes -8V from 0V, in current is about 100 msec. However, preferably, this t2 is 1 μsec or less. More preferably, this t2 is 100 ns.
It is about ec.

Further, the time t3 during which the source voltage V _S is held at −8 V is currently about 1 μsec to several μsec. This time t3 is preferably 1 μsec or less. More preferably, this t3 is several hundreds nse.
It is about c.

In the embodiment shown in FIG. 5, the application time of the control gate voltage V _{CG and} the application time of the p-well (substrate) voltage V _SUB are equal, but they may be different. . Further, the application time t4 is
Preferably, it is about 10 μsec.

Also, the source voltage V_SVoltage of -8V
The point b2 for returning to 0V is the control gate voltage V
_CGTiming of returning voltage from 3V to 0V and p well
(Substrate) voltage V_SUBTiming to return the voltage from -8V to 0V
It is preferably before b3. That is, the controller
Roll gate voltage V_CGAnd p-well (substrate) voltage V
_SUBIs at a steady state of 3V or -8V,
Source voltage V_SIs preferably applied
I can say.

Therefore, as shown in FIG. 6, the source voltage V _S is applied at a predetermined timing t5 after the control gate voltage V _CG and the p-well (substrate) voltage V _SUB are in the steady state. It may be one that is done. More specifically, as shown in FIG.
The point a2 in the pulse waveform of the source voltage V _S is
Points a1 and a3 in the pulse waveform of the control gate voltage V _CG and the p-well (substrate) voltage V _SUB
It may be present after the elapse of a predetermined time t5 from. Also in this case, the same effect as the above case can be obtained.

Referring again to FIGS. 5 and 10, after the source voltage V _S is applied and a predetermined time t3 elapses, FIG.
As shown by 0, the inversion layer 4 is formed in the channel region of the memory transistor. Then, the potential of the inversion layer 4 becomes a potential of about -8V.

After the inversion layer 4 is formed in this manner, the depletion layer 2 becomes smaller than that shown in FIG. 9, and the implantation mechanism as described above does not occur. That is,
If electrons are to be injected into the floating gate 9 in this state, it is necessary to apply a high voltage of about 10 V to the control gate 13, as in the case of the DINOR type flash memory described above. Therefore,
In the state shown in FIG. 10, no electrons are injected into the floating gate 9 only by applying a low voltage of about 3 V to the control gate 13 as in the present embodiment.

Next, a modification of the timing chart shown in FIG. 5 will be described with reference to FIG. With reference to FIG. 11, in the present modification, the pulse of the source voltage V _S is applied to the source region a plurality of times. in this way,
By applying multiple pulses to the source region,
The threshold voltage V _th in the erased state of the memory transistor can be made higher than in the above case.

In the embodiment shown in FIG. 11, the pulse of the source voltage V _S is applied to the source region twice, but it may be applied three times or more. Further, the timing of point b2 back to 0V from -8V to have the last pulse of the source voltage V _S, points b1 and p-well control gate voltage V _CG is returned to 0V from 3V (substrate) voltage V _SUB from -8V It is preferable to be before the point b3 at which the voltage returns to 0V. The same applies to the timing charts shown in FIGS. 5 and 6.
In addition, by repeating the control shown in FIGS. 5 and 6, the threshold voltage V after erasing of the memory transistor is also increased.
can increase _th .

Next, the effect of the present invention will be described with reference to FIGS. 12 and 13. FIG. 12 is a diagram showing the relationship between the erase time and the threshold voltage V _th of the flash memory in this embodiment. FIG. 13 is a diagram showing the relationship between the number of times of rewriting of the flash memory and the threshold voltage V _th in this embodiment.

First, referring to FIG. 12, in the present embodiment.
According to flash memory, about 10 ^-6in sec time,
Threshold voltage V of memory transistor after erasure_thIs about 7
It is about V. That is, DINOR type flash
The erase time is significantly longer than that of the memory (10 msec)
Can be shortened. That is, a high-performance flag
You will be able to obtain a flash memory.

Next, referring to FIG. 13, according to the flash memory of the present embodiment, the threshold voltage V _th of the memory transistor is equal to that of the DINOR flash memory even when the number of rewrites reaches 10,000 times. You can see that it has not changed as in the case. That is, the number of times of rewriting can be improved as compared with the DINOR type flash memory. That is, a high-performance and highly reliable flash memory can be obtained.

As the flash memory in the above embodiment, the flash memory having n-channel memory transistors has been described. However, the present invention can be applied to a flash memory having a p-channel memory transistor.

In the above embodiment, DINO
A flash memory having a configuration capable of performing the same operation as the R-type flash memory has been disclosed. However, the present invention is not limited to this, and the present invention can be applied to any memory device having a floating gate and performing an operation of injecting electrons into the floating gate.

[0183]

As described above, according to the present invention,
It becomes possible to lower the voltage applied to the control gate when injecting electrons into the floating gate. Thereby, the electric field strength applied to the tunnel insulating film can be reduced, and the number of times of rewriting can be increased.

Since the nonvolatile semiconductor memory device can be operated with the low voltage as described above, it is possible to simplify or omit the conventional circuit for generating the high voltage. . As a result, it is possible to obtain a non-volatile semiconductor memory device advantageous for high integration.

Since electrons are injected into the floating gate (substrate hot electron effect) by utilizing the electric field in the depletion layer spreading in a predetermined region of the semiconductor substrate, electrons can be efficiently injected into the floating gate. Is possible. As a result, the time required to inject electrons into the floating gate can be significantly shortened as compared with the conventional case. That is, the time required for the operation of the nonvolatile semiconductor memory device can be shortened.

As described above, according to the present invention, it is possible to obtain a nonvolatile semiconductor memory device which is advantageous for high integration and has high performance and high reliability.

[Brief description of drawings]

FIG. 1 is a block diagram schematically showing a characteristic configuration of the present invention.

FIG. 2 is a block diagram showing a configuration of a flash memory in one embodiment based on the present invention.

FIG. 3 shows a flash memory according to the present invention with a DINO
9 is a flowchart for explaining an erase operation when the same erase operation as in the R-type flash memory is performed.

FIG. 4 is a flow chart for explaining an erase operation and a verify operation when a flash memory according to an embodiment of the present invention is made to perform an erase operation similar to that of a DINOR type flash memory.

FIG. 5 is a timing chart when performing the erase operation of the flash memory in one embodiment according to the present invention.

6 is a diagram showing a first modification of the timing chart shown in FIG.

FIG. 7 is a sectional view of a memory transistor in an initial state before an erase operation is performed in the flash memory according to the present invention.

FIG. 8 is a cross-sectional view of a memory transistor showing a state in which a depletion layer is expanded by applying a predetermined potential to a control gate and a p-type impurity region.

FIG. 9 shows a flash memory according to the present invention,
FIG. 6 is a cross-sectional view of a memory transistor showing a state where electrons are injected into a floating gate.

10 is a cross-sectional view of the memory transistor showing a state where an inversion layer is formed in the channel region of the memory transistor after the operation shown in FIG. 9 is completed.

11 is a diagram showing a second modification of the timing chart shown in FIG.

FIG. 12 is a diagram showing the relationship between the erase time and the threshold voltage V _th of the flash memory according to the present invention.

FIG. 13 is a diagram showing the relationship between the number of rewrites and the threshold voltage V _th in the flash memory according to the present invention.

FIG. 14 is a block diagram showing a general configuration of a flash memory.

FIG. 15 is an equivalent circuit diagram showing a schematic configuration of a memory cell array of a NOR flash memory.

FIG. 16 is a cross-sectional structural diagram of a memory transistor of a NOR flash memory.

FIG. 17 is a schematic plan view showing a planar arrangement of a NOR flash memory.

18 is a diagram showing a cross section taken along line XVIII-XVIII in FIG.

FIG. 19 is an equivalent circuit diagram showing a part of a memory cell array of a NAND flash memory.

FIG. 20 is a partial cross-sectional view of a memory cell array of a NAND flash memory.

FIG. 21 is a cross-sectional structure diagram of a memory transistor of a NAND flash memory.

FIG. 22 is a block diagram showing a schematic configuration of a DINOR type flash memory.

FIG. 23 is a schematic diagram showing a schematic configuration of a DINOR type flash memory.

FIG. 24 is a partial cross-sectional view of a memory cell array of a DINOR type flash memory.

FIG. 25 is an equivalent circuit diagram of the memory cell array shown in FIG. 24.

FIG. 26 is a sectional structural view of a memory transistor in a DINOR type flash memory.

FIG. 27 is a timing chart in the erase operation of the DINOR flash memory.

FIG. 28 is a diagram showing the relationship between the erase time and the threshold voltage V _th of a DINOR type flash memory.

FIG. 29 is a diagram showing the relationship between the number of times of rewriting of the DINOR type flash memory and the threshold voltage V _th .

[Explanation of symbols]

 1 p-type impurity region 2 depletion layer 3 source region 4 inversion layer 5 drain region 7 tunnel insulating film 9 floating gate 11 insulating layer 13 control gate

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G11C 16/06 H01L 21/8247 29/788 29/792 6866-5L G11C 17/00 530B H01L 29 / 78 371

Claims (9)

[Claims] 1. A memory cell formed on a semiconductor substrate and arranged in a plurality of rows and a plurality of columns, a plurality of word lines provided corresponding to the plurality of rows, and a plurality of word lines provided commonly to the plurality of memory cells. Each of the memory cells includes a control gate connected to the corresponding word line, an impurity region connected to the source line, and a floating gate. Sometimes the first word line is selected
A word line drive means for applying a voltage of a second level, and a substrate drive means for applying a voltage of a second level to a predetermined region of the semiconductor substrate corresponding to the selected memory cell in the first operation mode. , In the selected first source line in the first operation mode,
Source line driving means for applying a voltage of a level of, and the first line to the word line in the first operation mode.
With respect to the application timing of the voltage of the level and the application timing of the voltage of the second level to the predetermined region of the semiconductor substrate,
A non-volatile semiconductor memory device, further comprising: a delay unit that delays a timing of applying the voltage of the third level to the source line. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the pulse width of the voltage pulse of the third level applied to the source line is applied to the word line and a predetermined region of the semiconductor substrate. The nonvolatile semiconductor memory device according to claim 1, further comprising pulse control means for making the pulse width shorter than the pulse width of the voltage pulse of the second level. 3. The non-volatile semiconductor memory device according to claim 2, wherein the pulse control means includes means for applying one or a plurality of voltage pulses of the third level to the source line. 4. A memory cell formed on a semiconductor substrate and arranged in a plurality of rows and a plurality of columns, a plurality of word lines provided corresponding to the plurality of rows, and a plurality of word lines provided corresponding to the plurality of columns. A plurality of bit lines and a source line common to the memory cells, each of the plurality of memory cells being connected to a control gate connected to a corresponding word line and a corresponding bit line. A drain, a source connected to the source line, and a floating gate, in which electrons are injected into the floating gate to be in an erased state, and electrons are withdrawn from the floating gate to be in a written state. A semiconductor memory device comprising: a word line drive means for applying a positive voltage to the selected word line in an erase mode; Substrate driving means for applying a negative voltage to a predetermined region of the semiconductor substrate corresponding to the selected memory cell in the erase mode, and a source line for applying a negative voltage to the selected source line in the erase mode Drive means, and in the erase mode, the negative voltage applied to the source line with respect to the application timing of the positive voltage to the word line and the application timing of the negative voltage to a predetermined region of the semiconductor substrate. A non-volatile semiconductor memory device, comprising: a delay unit that delays the application time of. 5. A memory cell formed on a semiconductor substrate and arranged in a plurality of rows and a plurality of columns, a plurality of word lines provided corresponding to the plurality of rows, and a plurality of word lines provided commonly to the plurality of memory cells. An operation of the non-volatile semiconductor memory device including a control gate connected to a corresponding word line, an impurity region connected to the source line, and a floating gate. A control method, wherein a first operation is performed on the selected word line in the first operation mode.
The voltage of the second level is applied to a predetermined region of the semiconductor substrate corresponding to the selected memory cell, and the word line and the semiconductor are applied in the first operation mode. Applying a voltage of the third level to the selected source line after applying the voltage of the first and second levels to a predetermined region of the substrate, and controlling the operation of the nonvolatile semiconductor memory device. Method. 6. A voltage of a first polarity is applied to the word line, a voltage of a second polarity is applied to a predetermined region of the semiconductor substrate, and a voltage of the second polarity is applied to the source line. Is applied,
The operation control method for a nonvolatile semiconductor memory device according to claim 5. 7. The source line is provided with one or more of the third levels while the voltage of the first and second levels is applied to a predetermined region of the word line and the semiconductor substrate. The operation control method for a nonvolatile semiconductor memory device according to claim 5, wherein a voltage pulse is applied. 8. The application time of the voltage of the third level is
The operation control method for a nonvolatile semiconductor memory device according to claim 5, wherein the application time is shorter than the application time of the first and second voltages. 9. A memory cell formed on a semiconductor substrate and arranged in a plurality of rows and a plurality of columns; a plurality of word lines provided corresponding to the plurality of rows; and a plurality of word lines provided corresponding to the plurality of columns. A plurality of bit lines and a source line common to the memory cells, each of the plurality of memory cells being connected to a control gate connected to a corresponding word line and a corresponding bit line. A drain, a source connected to the source line, and a floating gate, in which electrons are injected into the floating gate to be in an erased state, and electrons are withdrawn from the floating gate to be in a written state. A method for controlling the operation of a semiconductor memory device, comprising: applying a positive voltage to the selected word line in an erase mode to select the selected word line. Applying a negative voltage to a predetermined region of the semiconductor substrate corresponding to a memory cell; and applying the positive voltage to the word line and applying the negative voltage to a predetermined region of the semiconductor substrate during the erase mode. And a step of applying a negative voltage to the selected source line after applying the voltage.