JP2508888B2 - Nonvolatile semiconductor memory device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a flash E ² PROM which can be collectively erased electrically.

[Conventional technology]

The flash E ² PROM injects electrons from the vicinity of the drain of the memory transistor at the time of writing to make it have a high threshold voltage, and at the time of erasing, pulls out electrons from the source to make it have a low threshold voltage. In addition, writing is performed in byte or word units, and erasing is collectively performed in the entire chip. At the time of this erasing, a memory transistor with a fast erasing and a memory transistor with a slow erasing appear due to process variations. If the erasing time is made sufficiently long in accordance with the memory transistor with slow erasing, the threshold voltage of the memory transistor with fast erasing becomes negative. In reading, whether the current flows or does not flow through the memory transistor is determined to determine whether it is in the erased state or the written state. Even if one of the memory transistors connected to the bit line has a negative threshold voltage. Even if the memory transistor is in a non-selected state and the gate potential (word line potential) is 0 V, a very large current flows and correct information cannot be read. Therefore, a method of automatically controlling erasing inside the chip has been considered. In this method, a short erase pulse is applied, then reading is performed, and if there is a non-erased memory transistor, the operation of applying the erase pulse again is repeated until all memory cells are erased.

FIG. 2 is a flowchart showing automatic erasing, FIG. 3 is a block system diagram showing the entire nonvolatile semiconductor memory device, and FIG.
FIG. 5 is a block system diagram showing the erase control circuit of FIG.
The drawing is a circuit diagram showing a part of the sense amplifier, write circuit, Y gate, Z gate, and memory cell array of FIG.

In FIGS. 3 and 5, 1,2,3 are memory transistors, 4,5,6 are bit lines, 7 is a word line, 8 is a source line, 9,10,11 are Y gate lines, and 12,13. , 14 is Y gate, 15,1
6, 17 are NAND gates, 18, 19 and 20 are inverters, 21 is a Y decoder composed of NAND gates 15 to 17 and inverters 18 to 20,
22 is a Z decoder, 23 is a Z gate, 24 is a write transistor, 25 is a sense amplifier, 26 and 29 are P channel transistors, 27, 28 and 30 are N channel transistors, 31 is an inverter, and 32 is an output terminal of read data RD. , 33 is a high voltage V _pp supply terminal, 34 is a writing circuit, and 40 is data input / output.
DQ buffer, 41 buffer of control signal ER, 42 erase control circuit, 43 memory cell array, 44 array source switch, 45 row decoder, 46 address buffer to which address data is input, 47 high voltage V _pp Is a high voltage control circuit to which is input. In FIG. 4, 42 is an erase control circuit, 421 is an address counter that outputs address data to the decoders 21, 22, 45, 422 is an erase verify circuit into which read data RD is input, and 423 is a high voltage V _pp . An erase pulse generation circuit that inputs and outputs an erase pulse to the array source switch 44.

Next, the operation of the conventional example will be described with reference to FIGS. As described above, in the flash E ² PROM, erasing is automatically controlled inside the chip. Here, this erasure will be described. Erasing includes an erase pulse applying operation for applying a relatively short erase pulse to the sources of all memory transistors, and an erase verify operation for determining whether or not all memory transistors have been erased. When the control signal ER that enables erasing is input, it enters the erasing mode,
First, erase pulse application operation is performed (step S in FIG. 2).
1). The erase control circuit controls the entire erase operation. In the erase pulse application operation, the word line 7 of the memory transistor
To "L" level, turn off all Y gates 12,13,14,
A high voltage is applied from the array source switch 44 to the sources of all memory transistors. In this state, electrons are extracted from the floating gate of the memory transistor to the source, and the threshold voltage of the memory transistor becomes low.
Next, the erase verify operation is automatically performed (second
Step S2 in the figure). In erase verify, erase control circuit
The address data generated by the address counter 421 in 42 is applied to the row decoder 45, Y decoder 21, and Z decoder 22. One word line 7 is selected by the row decoder 45, and one Y gate is selected by the Y decoder 21 and the Z decoder 22.
12, one Z gate 23 is selected and one bit line 4
Are connected to one sense amplifier 25. Here, the sense amplifier 25 is activated to read the information of the selected memory transistor 1. If the read data of the memory transistor is "1" (erased state), the address counter 421 generates the next address data, and the information of the memory transistor at the next address is read (FIG. 2). Step S3). If the read data of the memory transistor is “0” (write state),
The erase verify operation is stopped and the erase pulse applying operation is resumed (steps S1 and S2 in FIG. 2). When the read data of all the memory transistors become "1", the erase mode ends (step S3 in FIG. 2).

[Problems to be Solved by the Invention]

Since the conventional device is configured as described above, at the time of erase verify, only the data of one address is read as in the normal read. Therefore, it takes a long time to perform the erase verify, which causes a long erase time. Further, as the capacity increases and the number of memory transistors to be verified increases, this time becomes even longer.

The present invention has been made in view of such a point,
The purpose is to obtain a non-volatile semiconductor memory device in which the erase time is shortened.

[Means for solving the problem]

In order to achieve such an object, the present invention provides a plurality of lines,
Memory cells arranged in a matrix in a plurality of columns, electrically writable and erasable, and a plurality of word lines arranged corresponding to each row of the memory cells and commonly connected to the memory cells in each row, A plurality of bit lines arranged corresponding to each column of the memory cells and commonly connected to the memory cells of each column, and provided respectively corresponding to the bit lines, between the corresponding bit line and the common node. Connected to a common node, and a plurality of transfer gates connected to the Y-decoder for inputting an address signal and selectively controlling ON / OFF of the transfer gate by the address signal, and reading at the time of erase verify and reading A current amplification type sense amplifier having different sensitivities is provided.

[Action]

In the non-volatile semiconductor memory device according to the present invention, the read sensitivity of the sense amplifier is made different at the time of erase verify and at the time of read. Therefore, at the time of erase verify, the sense output can be performed at the optimum level for erase verify.

〔Example〕

An embodiment of a nonvolatile semiconductor memory device according to the present invention will be described with reference to the drawings. Description of the same parts as those in the conventional example will be omitted. FIG. 1 is a block system diagram showing an embodiment of the present invention. In the figure, 35, 36, and 37 are NAND gates, and 38 is at "L" level when the erase verify is started.
A signal input terminal 39 is a P-channel transistor, and the P-channel transistor 39 has a size higher than the transistor 29 in current supply capability.

Next, the operation will be described. In erase mode,
Since the erase pulse applying operation is similar to that of the conventional example, the description thereof is omitted. When the erase verify operation starts, the signal ▲ ▼
Becomes the “L” level, so the NAND gate of the Y decoder 21
35, 36, 37 bring all the Y gate lines 9, 10, 11 to "H" level, and the Y gates 12, 13, 14 are turned on. At the same time, one Z gate 23 is selected by the Z decoder 22, and the Z gate 23 is selected.
All bit lines 4, 5 and 6 connected to are connected to the sense amplifier 25. In the sense amplifier 25, the signal ▲ ▼ is “L”
Since the P-channel transistor 39 is turned on, even if the number of bit lines to be sensed is increased, it is possible to read with the same sense sensitivity as when there is one bit line. For example, when the memory transistors 1 and 2 are in the erased state and the memory transistor 3 is still in the written state, current flows to the bit lines 4 and 5, but not to the bit line 6, so the sense amplifier 25 is set to the written state. judge. Memory transistor 1,2,
If all 3 are in the erased state and current flows through all of the bit lines 4, 5 and 6, it is determined to be the erased state. The address counter 421 (see FIG. 4) counts only addresses excluding the Y address.

In this embodiment, the case where all the Y gates are selected has been described, but if two or more gates are selected at the same time, the erase verify can be similarly speeded up.

〔The invention's effect〕

As described above, according to the present invention, the sense sensitivity at the time of erase verify in the sense amplifier is made different from the sensor sensitivity at the time of reading, so that there is an effect that a sensing operation suitable for erase verify can be performed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a nonvolatile semiconductor memory device according to the present invention, FIG. 2 is a flow chart showing automatic erasing, FIG. 3 is a block system diagram showing the entire chip, and FIG. 4 is an erasing control circuit. FIG. 5 is a circuit diagram showing a conventional nonvolatile semiconductor memory device. 1-3 ... memory transistors, 4-6 ... bit lines,
7 ... Word line, 8 ... Source line, 9-11 ... Y gate line, 12-14 ... Y gate, 15-17, 35-37 ... NAND gate, 18-20 ... Inverter, 21 ... … Y decoder, 22 ……
Z decoder, 23 ... Z gate, 24 ... writing transistor, 25 ... sense amplifier, 26,29,39 ... P-channel transistor, 27,28,30 ... N-channel transistor, 31 ...
… Inverter, 32 …… Output terminal, 33 …… Supply terminal, 34…
… Writing circuit, 38… Input terminal.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Yoshikazu Miyawaki 4-chome, Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Corporation ELS Research Institute (72) Shinichi Kobayashi 4-chome, Mizuhara Itami City, Hyogo Prefecture No. 1 Mitsubishi Electric Corporation LSI Research Laboratory (56) Reference JP-A-57-100690 (JP, A) JP-A-63-7600 (JP, A) JP-A-62-84499 (JP, A) JP-A-2-158999 (JP, A)

Claims (3)

(57) [Claims] 1. An electrically writable and erasable memory cell, which is arranged in a matrix in a plurality of rows and a plurality of columns, and is arranged so as to correspond to each row of the memory cells, and is shared by the memory cells in each row. A plurality of connected word lines, a plurality of bit lines arranged corresponding to each column of the memory cells and commonly connected to the memory cells of each column, and a plurality of bit lines provided corresponding to the bit lines, respectively. A plurality of transfer gates connected between corresponding bit lines and a common node, a Y decoder for inputting an address signal and selectively turning on / off the transfer gate by the address signal, and the common node And a current amplification type sense amplifier having different read sensitivities in erase verify and read. Apparatus. 2. A plurality of memory transistors having a control gate electrode, a floating gate electrode, a source electrode and a drain electrode, which are arranged in a matrix in a plurality of rows and a plurality of columns, and which are electrically writable and erasable. A plurality of word lines connected to the control gate electrodes of a plurality of memory transistors arranged in corresponding rows and a plurality of memory transistors arranged in a plurality of columns and arranged in a corresponding column. A plurality of bit lines connected to the drain electrodes, a Y gate transistor connected between the corresponding bit line and a common node, and an address signal, and the address signal causes the Y
Y for selectively turning on / off the gate transistor
A nonvolatile semiconductor memory device comprising: a decoder; and a sense amplifier which is connected to the common node and operates with a sense sensitivity different from a sense sensitivity at the time of reading when receiving an erase verify definition signal. 3. A plurality of memory transistors having a control gate electrode, a floating gate electrode, a source electrode and a drain electrode, which are arranged in a matrix in a plurality of rows and a plurality of columns, and which are electrically writable and erasable. A plurality of word lines connected to the control gate electrodes of a plurality of memory transistors arranged in corresponding rows and a plurality of memory transistors arranged in a plurality of columns and arranged in a corresponding column. A plurality of bit lines connected to the drain electrodes, a Y gate transistor connected between the corresponding bit line and a common node, and an address signal, and the address signal causes the Y
Y for selectively turning on / off the gate transistor
A decoder, a first transistor connected between the common node and a power supply node, inverter means connected between the gate electrode of the first transistor and the common node, an output node and the common node A second transistor whose gate electrode is connected to the gate electrode of the first transistor, is connected between the power supply node and the output node, and receives the erase verify definition signal, and is read at the time of reading. A non-volatile semiconductor memory device comprising: a sense amplifier having a current supply unit having a current supply capability different from that of an output node.