KR930006738A - Electrically Erasable and Programmable Nonvolatile Semiconductor Memory with Automatic Write-Verify Controller - Google Patents

Abstract

The NAND-cell type EEPROM includes an array of memory cells M connected to a bit line BL. Each cell includes one transistor having a floating gate and a control gate electrode, and electrons are tunneled from or to the floating gate to write data. The sense / latch circuit FF is connected to the bit line BL, and selectively performs a sense operation and a latch operation of the write data. The program controller 2 is provided for writing data in the selected memory cell in the designated area and reading the data written in the selected cell to verify whether the final threshold voltage is within an acceptable range. If it is insufficient, the data is rewritten there. The write-in data setting portions Qn9 and Qn10 perform logic operations on read data from the selected cell and write data latched to the sense / latch circuit means FF, and all bit lines according to the verified actual write state. It is provided for automatically updating the rewrite data stored in the sense / latch circuit FF.

The sense / latch circuit includes a CMOS flip-flop that acts as a data-latch circuit at the start of the verify operation, and functions as a sense amplifier once it has been reset.

Description

Electrically Erasable and Programmable Nonvolatile Semiconductor Memory with Automatic Write-Verify Control

Since this is an open matter, no full text was included.

1 is a schematic illustration of the overall arrangement of a NAMD-cell type electrically erasable and programmable read only memory in accordance with one preferred embodiment of the present invention;

FIG. 6 is a timing diagram showing a potential change occurring in a main constituent element according to the illustrative example of the present invention during the read operation on the even row of the embodiment of the present invention; FIG.

Claims (19)

The carrier from the carrier storage layer for data writing or with a semiconductor substrate 11, a plurality of bit lines BL on the substrate, an insulated carrier storage layer and a control gate electrode disposed insulated on the carrier storage layer Selectively performing a data latch operation to latch a row and column array of memory cells, a sensing operation, and a write data, each comprising a transistor capable of tunneling charge carriers to a storage layer and connected to said bit line on said substrate. Sense / latch circuit means (FF) coupled to the bit line, write data is written into selected memory cells or cells of the memory cells included in a specified region for a predetermined period of time, and a final threshold voltage is selected Within the selected memory cell or cells to verify whether it is within range A program reading means (2, 3, 4,) and the selected memory cell or cell for rewriting the write data into the insufficiently written memory cell transistor if the memory is read and if an insufficiently written memory cell transistor is found. Perform a logic operation on the contents of the data and the read data corresponding to the write data latched in the sense / latch circuit means FF, and detect / latch for each bit line according to the actual write state currently being verified. Data setting means (Qn9, Qn10) for automatically updating the write data stored in the circuit means (FF), wherein the sensing / latch circuit means (FF) serves as a latch circuit at the start of the verify operation. An electrically erasable feature, which is retained and resets, functions as a sense amplifier circuit and includes a flip-flop circuit (FF). And programmable non-volatile semiconductor devices. The complementary metal oxide semiconductor (CMOS) flip of claim 1, wherein the flip-flop circuit FF has nodes N1 and N2 coupled to bit lines BLi through transfer gates Qn7 and Qn8. An apparatus comprising a flop circuit. 3. An apparatus according to claim 2, wherein said CMOS flip-flop circuit (FF) is provided in adjacent ones of said bit lines (BL). 4. The CMOS flip-flop circuit of claim 3, wherein the CMOS flip-flop circuit includes a first MOS transistor of a first conductivity type and a second MOS transistor (Qn5, Qn6) of a second conductivity type, wherein the first MOS transistor and the second MOS transistor are each other. Device characterized in that it is cross-linked. 2. The flop circuit FF of claim 1, wherein the flop circuit FF is connected to a corresponding one of the bit lines BL, and has opposite conductivity type first MOS transistors Qn5 and Qn6 and second MOS transistors Qn19 and Qn20. Device comprising a complementary metal oxide semiconductor (CMOS). 3. An apparatus according to claim 2, wherein said data setter means comprises charger means for selectively charging bit line BLi in accordance with the data currently being latched in said CMOS flip-flop circuit FF. . 7. The gate driving circuit according to claim 6, wherein said data setter means is coupled to said node (N1) of said CMOS flip-flop circuit (FF), a first current transfer electrode coupled to a corresponding bit line, and a second current. And a first MOS transistor Qn10 having a transfer electrode and a second MOS transistor Qn9 arranged between the second current transfer electrode and the power supply voltage Vcc and responsive to the verification control clock signal XAV. Made by the device. 2. An apparatus according to claim 1, wherein the array of rows and columns of memory cells is divided into a plurality of subarray portions (1A, 1B) on the substrate. A memory cell array arranged in rows and columns and divided into a plurality of cell portions each including a plurality of memory cell transistors each having a charge storage layer and a control gate, a control line connected to a row of memory cells at a control gate, the cell Optionally, the data transmission line connected to the portions, the row decoder connected to the control line, the column decoder connected to the data transmission line, the address buffer connected to the row decoder and the column decoder, the sensing operation and the latching operation of the write data are selectively provided. Sensing / latch circuit means connected to the data transmission line for performing write data to a selected memory cell or cells of the memory cells included in a specified area for a predetermined length of time period, and a pseudo threshold voltage is set The selected memory cell to verify whether it is within range Reads the contents of the cells and, if an insufficiently written memory cell transistor is found, program controller means for rewriting write data into the insufficiently written memory cell transistor and the contents of the selected memory cell or cells and the sensing / Perform a logic operation on the read data corresponding to the write data latched by the latch circuit means FF, and perform a logic operation on the sense / latch circuit means FF for all data transmission lines according to the current verified and actual write state. Data setter means (Qn9, Qn10) for automatically updating stored rewrite data, wherein said sense / latch circuit means is held as a latch circuit at the beginning of a verify operation and reset to the sense amplifier after being reset. An electrically erasable, characterized in that it comprises a functioning flip-flop circuit. Programmable read only memory system. 10. The memory of claim 9 wherein the flip-flop circuit FF comprises a complementary metal oxide semiconductor field effect transistor or CMOS flip-flop circuit having a node coupled to a data transfer line through a transfer gate. system. 11. The memory system of claim 10 wherein said data setter means comprises circuitry for selectively charging a data bit line (BLi) currently latched in said CMOS flip-flop circuit (FF). 12. The device of claim 11, wherein the data setter means comprises: a first MOS having a gate electrode coupled to the node of the CMOS flip-flop circuit, a first current transfer electrode coupled to a corresponding data transfer line, and a second current transfer electrode; And a second MOS transistor having a transistor and a gate electrode arranged between the second current transfer electrode and a power supply voltage and responsive to a verify control clock signal. The memory cell transistors of claim 10, wherein the memory cell transistors are connected to each other in series in each cell portion having one end selectively coupled to a corresponding one of the data transfer lines and the other end selectively coupled to a common source potential. Memory system, characterized in that. 15. The memory system of claim 13 wherein the one end is a drain of a memory cell transistor and the other end is a source of another memory cell transistor. 12. The memory system of claim 10 wherein the array of memory cells is arranged on a semiconductor substrate having a predetermined conductivity type. In a memory cell matrix comprising a plurality of memory cell transistors arranged in rows and columns, each having a charge storage layer, a control gate, a first current transfer electrode coupled to a predetermined potential, and a second current transfer electrode. A control line connected to a row of memory cells, a data transfer line connected to a column of memory cells at a second current transfer electrode, a row decoder connected to a control line, a column decoder connected to a data transfer line said row decoder and a connection to said decoder A sensing / latch circuit means connected to said data transmission line to selectively perform an address buffer, a sensing operation and a latching operation of write data, a selected memory cell of said memory cells included in a specified region for a predetermined length of time period Or write data into cells, and a range in which the final threshold voltage is selected Program controller means for reading the contents of said selected memory cell or cells to verify whether they belong to, and if an insufficiently written memory cell transistor is found, rewriting write data into an insufficiently written memory cell transistor; Perform a logic operation on the contents of the selected memory cell or cells and the read data corresponding to the write data latched in the sense / latch circuit means FF, and transfer all data according to the actual write state currently being verified. Data setter means (Qn9, Qn10) for automatically updating rewrite data stored in said sense / latch circuit means (FF) for a line, wherein said sense / latch circuit means starts at the verify operation. Retained as a latch circuit, reset and then function as a sense amplifier Flip-electrically erasable and programmable read only memory system comprising a flop circuit. 17. The memory system of claim 16 wherein the flip-flop circuit (FF) comprises a complementary metal oxide semiconductor field effect transistor or CMOS flip-flop circuit having a node in a data transfer line through a transfer gate. 18. The apparatus of claim 17, wherein the data setter means comprises an optional discharge circuit for selectively discharging the bit line BLi in accordance with the data currently latched in the CMOS flip-flop circuit FF. Memory system. 19. The apparatus of claim 18, wherein the data setter means has a gate electrode coupled to the node of the CMOS flip-flop circuit, a first current transfer electrode coupled to a corresponding data transfer line, and a second current transfer electrode. And a second MOS transistor having a MOS transistor and a gate electrode arranged between the second current transfer electrode and the ground line, the gate electrode responsive to a verify control clock signal. ※ Note: The disclosure is based on the initial application.