JP3142335B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM), and more particularly to a nonvolatile semiconductor memory device (EEPROM).
EEPRO having memory cell array of AND cell configuration
About M.

[0002]

2. Description of the Related Art As one type of EEPROM, a NAND cell type EEPROM capable of high integration is known. In this method, a plurality of memory cells are connected in series in such a manner that their sources and drains are shared by adjacent ones and connected to a bit line as one unit. A memory cell is usually a FETMOS in which a charge storage layer and a control gate are stacked.
Having a structure. The memory cell array is integrally formed in a p-type well formed on a p-type substrate or an n-type substrate. NA
The drain side of the ND cell is connected to a bit line via a selection gate, and the source side is also connected to a source line (reference potential wiring) via a selection gate. The control gates of the memory cells are arranged continuously in the row direction to form word lines.

The operation of this NAND cell type EEPROM is as follows. The data write operation is performed in order from the memory cell located farthest from the bit line. A high voltage Vpp (= about 20 V) is applied to the control gate of the selected memory cell, and the intermediate potential VppM (= 10 V
V), and 0 V or an intermediate potential is applied to the bit line according to data. When 0V is applied to the bit line,
The potential is transmitted to the drain of the selected memory cell,
Electron injection occurs from the drain to the floating gate. As a result, the threshold value of the selected memory cell shifts in the positive direction. This state is, for example, "1". When an intermediate potential is applied to the bit line, electron injection does not occur, so that the threshold value does not change and remains negative. This state is "0".

[0004] Data erasure is performed simultaneously on all memory cells in a NAND cell. That is, all control gates and select gates are set to 0 V, the bit lines and source lines are set in a floating state, and a high voltage of 20 V is applied to the p-type well and the n-type substrate.
Is applied. As a result, in all the memory cells, electrons of the floating gate are emitted to the p-type well, and the threshold value shifts in the negative direction.

In a data read operation, the control gate of the selected memory cell is set to 0 V, the control gates and select gates of the other memory cells are set to the power supply potential Vcc (= 5 V), and whether a current flows in the selected memory cell is determined. This is done by detecting

As is apparent from the above description of the operation, NA
In the ND cell type EEPROM, unselected memory cells act as transfer gates during write and read operations. From this viewpoint, the threshold voltage of the written memory cell is restricted. For example, a preferable range of the threshold value of the memory cell in which “1” is written is about 0.5 to 3.5 V. In consideration of a change over time after data writing, a variation in manufacturing parameters of a memory cell, and a variation in power supply potential, the threshold distribution after data writing is required to be in a smaller range.

However, in the conventional method of writing data in all memory cells under the same conditions while fixing the writing potential and writing time, it is difficult to keep the threshold range after "1" writing within an allowable range. . For example, the characteristics of memory cells vary due to variations in the manufacturing process. Therefore, from the viewpoint of writing characteristics, there are memory cells that are easily written and memory cells that are hardly written. On the other hand, there has been proposed a method of performing writing while adjusting the writing time so that the threshold value of each memory cell falls within a desired range while performing verification.

However, in the conventional circuit technology, there is a problem that a flip-flop for operating a data latch or a sense amplifier is provided at both ends of the bit line in order to realize this method, thereby increasing the circuit area.

[0009]

As described above, the conventional N
In the AND cell type EEPROM, when data is written, it is difficult for the memory cell to be within the allowable threshold range which is limited because the memory cell acts as a transfer gate. To solve this, the control circuit area increases. There was a problem.

According to the present invention, a NAND cell type EEPROM capable of setting a small threshold distribution of a memory cell in a written state without increasing the area of a control circuit.
The purpose is to provide.

[0011]

In a NAND cell type EEPROM according to the present invention, a charge storage layer and a control gate are stacked on a semiconductor substrate, and electrical rewriting is performed by transferring charges between the charge storage layer and the substrate. A memory cell array in which memory cells are arranged, a data latch / sense amplifier provided at one end of the memory cell array in the bit line direction for performing a sense operation and a latch operation of write data, and a predetermined range of the memory cell array. Verify control means for setting a unit write time in a memory cell and simultaneously writing data, then reading the memory cell data and rewriting when there is a memory cell with insufficient writing; The data of the read memory cell and the write data latched by the data latch and sense amplifier Taking logic is characterized by comprising a means for automatically setting the rewriting data of the data latch and sense amplifier for each bit in response to a write state.

[0012]

According to the present invention, after performing data writing, a predetermined verify potential (for example, set at an intermediate level between the power supply potential and the ground potential) is applied to the control gate of the memory cell to set the threshold voltage of the memory cell. It is evaluated by the bit line control circuit. Then, if there is a memory cell that has not reached the desired threshold value, a write operation is added only to that memory cell. After that, the threshold value is evaluated again. This operation is repeated, and when it is confirmed that the threshold values of all the memory cells are within the desired allowable range, the write operation is completed.

As described above, according to the present invention, the data write time is shortened, and the data write is repeated little by little while checking the progress of the data write. The threshold voltage distribution of the cell array can be reduced. In addition, the bit line control circuit compares latch data with verify read data and automatically controls additional verify writing. Therefore, the bit line control circuit is almost equivalent to a conventional bit line control circuit of a NAND type EEPROM having no write verify function. And an increase in chip area can be suppressed.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of the present invention.
1 shows a configuration of an AND cell type EEPROM. A bit line control circuit 2 is provided for performing data write, read, rewrite, and verify read with respect to the memory cell array 1. This bit line control circuit 2 is connected to a data input / output buffer 6 and receives as an input the output of a column decoder 3 that receives an address signal from an address buffer 4. A row decoder 5 is provided for controlling a control gate and a selection gate for the memory cell array 1, and a substrate potential for controlling a potential of a p substrate (or a p-type well) on which the memory cell array 1 is formed. A control circuit 7 is provided.

The bit line control circuit 2 is mainly composed of a CMOS flip-flop, and latches data to be written, senses the potential of the bit line, senses a verify read after writing, and re-executes the operation. Latch the write data.

FIGS. 2A and 2B are a plan view and an equivalent circuit diagram of one NAND cell part of the memory cell array.
3A and 3B are cross-sectional views taken along the lines AA 'and BB' of FIG. 2A, respectively. In a p-type silicon substrate (or p-type well) 11 surrounded by an element isolation oxide film 12, a plurality of N
A memory cell array composed of AND cells is formed. Focusing on one NAND cell, in this embodiment, eight memory cells M1 to M8 are connected in series to constitute one NAND cell. In each of the memory cells, a floating gate 14 (14 ₁ , 14 ₂ ,..., 14 ₈ ) is formed on a substrate 11 via a gate insulating film 13, and a control gate 16 (1
6 ₁ , 16 ₂ ,..., 16 ₈ ) are formed. N which is the source / drain of these memory cells
The memory cells are connected in series so that the adjacent ones of the pattern diffusion layers 19 are shared.

The drain side of the NAND cell, respectively to the source side, a floating gate, selected simultaneously formed with the control gate gate 14 ₉ of the memory cells, 16 ₉ and 14 _10, 16 ₁₀
Is provided. The substrate on which the elements are formed is covered with a CVD oxide film 17, on which a bit line 18 is provided. The bit line 18 is in contact with the drain-side diffusion layer 19 at one end of the NAND cell. The control gates 14 of the NAND cells arranged in the row direction are commonly arranged as control gate lines CG1, CG2,..., CG8. These control gate lines become word lines. Select gate 14
_9, 16 ₉ and 14 _10, 16 ₁₀ are also arranged in each row direction successively selected gate lines SG1, SG2.

FIG. 4 shows an equivalent circuit of a memory cell array in which such NAND cells are arranged in a matrix.

FIG. 5 shows a specific configuration of the bit line control circuit 2 in FIG. E-type, p-channel MOS transistors Qp1, Qp as data latch and sense amplifier
p2, an E type, n channel MOS transistor Qn5,
It has a CMOS flip-flop FF constituted by Qn6. The CMOS flip-flop FF is provided at a ratio of one to two bit lines. CMOS
The two nodes N1 and N2 of the flip-flop FF are
And bit lines BL2i (i = 0, 1, 2,...) And B via n-channel MOS transistors Qn7, Qn8, respectively.
L2i + 1. n channel MOS transistor Q
n7 and Qn8 are controlled by control signals φA and φB, respectively, to connect and disconnect between the CMOS flip-flop FF and the bit line.

Each of the bit lines BL2i and BL2i + 1 is provided with a series circuit of an E type, n-channel MOS transistors Qn9 and Qn10 and Qn11 and Qn12 between the power supply Vcc. Among these, the gate of the MOS transistor Qn10 is controlled by one node N1 of the CMOS flip-flop FF, and the MOS transistor Qn1
The gate of 1 is controlled by the other node N2. Verify read signals φAV and φBV which become “H” at the time of verify read are input to the gates of the remaining MOS transistors Qn9 and Qn12, respectively. By these MOS transistors, bit lines BL2i
Alternatively, BL2i + 1 is charged to Vcc-Vth (Vth is the threshold value of the E-type n-channel MOS transistor). The bit lines BL2i and BL2i + 1 are provided with precharge E-type, n-channel MOS transistors Qn13 and Qn14 controlled by precharge signals φPB and φPA.

The E type, n-channel MOS transistors Qn3 and Qn4 are controlled by an equalizing signal
This is for equalizing the two nodes N1 and N2 of the MOS flip-flop FF. The E type, n channel MOS transistors Qn1 and Qn2 are connected to the column signal CSL.
i, the input / output lines IO, / IO and the CMOS
This is a transfer gate to which a flip-flop FF is connected to input and output data.

VSW is the potential of the n-type well where the p-channel MOS transistors Qp1 and Qp2 of the flip-flop FF are formed, and is usually Vcc.
M (= 10V). VSP applied to the common source node of the p-channel MOS transistors Qp1 and Qp2 is usually Vcc, and becomes the intermediate potential VM during writing and temporarily becomes (1/2) Vcc during reading. VSN applied to the common source node of n-channel MOS transistors Qn5 and Qn6 is normally 0 V, and temporarily becomes (1/2) Vcc during reading.
When the bit line BL2i is selected at the time of reading, the precharge potentials VSA and VSB are about VSA = 3V and VSB = (1 /
2) When Vcc is reached and bit line BL2i + 1 is selected at the time of reading, VSA = (1/2) Vcc and VSB = about 3V. Further, VSA and VSB become the intermediate potential VM at the time of writing, and become 0 V at the time of resetting the bit line after writing and erasing.

Next, the EEPROM constructed as described above will be described.
Will be described with reference to FIGS. 6 and 7
8 shows the read operation timing, and FIGS. 8 and 9 show the write / write verify read operation timing.

In the read operation, first, the signals φA and φB become “L”, and the CMOS flip-flop FF is disconnected from the bit line BL. Precharge signals φPA, φPB
Becomes "H", and the bit line is precharged. FIG.
In the example shown in FIG. 7, first, even-numbered bit lines BL
2i is selected, and in the next read cycle, the odd-numbered bit line BL2i + 1 is selected. Hereinafter, the first read cycle will be described.

The bit lines BL2i and BL2i + 1 are precharged to 3V and 0V, respectively, by the precharge signals φPA and φPB. When the precharge is completed, φPA becomes “L”, and the bit line BL2i enters a floating state. Thereafter, a desired voltage is output from the row decoder 5 to the selection gate and the control gate. For example, the control gate CG2 shown in FIG.
Is selected, CG1, CG3 to CG8 are Vcc, CG2
Is 0V, and SG1 and SG2 are Vcc. According to the data of the memory cell, when "1", the threshold value of the memory cell is positive and no cell current flows, and the potential of the bit line BL2i becomes 3
V. In the case of data "0", a cell current flows and the potential of the bit line BL2i drops to 2.5V or less.

Here, the control gate and the selection gate are reset to 0 V. Voltage VSB is (1/2) Vcc
(= 2.5 V), and the bit line BL2i + 1 becomes (1/2)
After the CMOS flip-flop is precharged to Vcc and equalized by setting .phi.E to "H" and VSP and VSN to (1/2) Vcc, the signals .phi.A and .phi.B become "H" and the bit line BL2i , BL2i + 1 and a CMOS flip-flop are connected. When VSP becomes Vcc and VSN becomes 0 V, the bit line voltage is differentially sensed, and the read data is latched as it is.

When the column selection signal CSLi becomes "H", the read data is output to the IO and / IO lines, transmitted to the data output buffer 6, and taken out. When the odd-numbered bit line BL2i + 1 is selected, the operations of φA and φB, φPB and φPA, and VSA and VSB may be switched.

Next, the write operation will be described. FIG.
9 and FIG. 9 show a write / write verify read operation excluding a data load operation of the write data from the input / output buffer 6 of the bit line control circuit 2 when an even-numbered bit number BL2i is selected. Prior to writing, all the control gates of the memory cells are set to 0 V, and the data is collectively erased by setting the p substrate (or p-type well and n substrate) on which the memory cells are formed to a high voltage VPP (up to 20 V). Write data is transferred from the data input / output buffer 6 to the CMOS flip-flop FF via the input / output lines IO and / IO.
, First, the precharge signals φPA, φPB
Becomes VM, and VSA, VSB, VSP and VSW become VM.
As a result, all the bit lines become VM-Vth. Also C
The two nodes of the MOS flip-flop FF become 0 V and VM according to the data.

When the signal φPA becomes 0 V and the signal φA becomes VM, the bit line BL2i is set to VM when the data is “0” and to 0 V when the data is “1” according to the write data. For example, when the control gate CG2 shown in FIG. 4 is selected by the row decoder 5, SG1, CG1, CG
3 to CG8 are set to VM, CG2 to Vpp, and SG2 to 0V.

After a certain period of time (.about.40 .mu.sec), after the control gates CG1 to CG8 and the selection gate SG1 are reset to 0 V, the signal .phi.A becomes 0 V, the bit line BL2i is disconnected from the CMOS flip-flop, and the voltages VSA, V
When SB becomes 0V and signals φPA and φPB become Vcc, all the bit lines are reset to 0V. VSP and VSW are V
cc.

Next, a write verify read operation is performed. The verify read operation is performed in substantially the same manner as a normal read operation, except that, for example, 0.5 V is applied to a selected control gate instead of 0 V, and a verify signal φAV is output. First, when the precharge signal φPA is 5V
And the bit line BL2i is precharged to 3V.
The precharge signal φPA becomes “L” and the bit line BL2i
Is in a floating state. The control gate and the selection gate are selected by the row decoder 5, and SG1, CG1, CG3
CG8 is set to Vcc, and CG2 is set to, for example, 0.5V. In normal reading, if the threshold value of the memory cell is 0 V or more, "1" is read, but in verify reading, 0.5 is read.
If it is not more than V, it cannot be read as "1".

Thereafter, VSB is (1/2) Vcc (up to 2.5
V), whereby the bit line BL2i + 1 becomes (1/2)
Vcc, and the bit line BL2i is charged to Vcc-Vth by the verify signal .phi.AV if "0" is written. Equalize signal φE is “H”, VSP and VSN
Is set to (1/2) Vcc and the CMOS flip-flop is reset. Then, .phi.A and .phi.B become "H", nodes N1 and N2 are connected to bit lines BL2i and BL2i + 1, respectively, and VSP is set to Vcc. , VSN become 0 V and the bit line BL2i
Is read out. The read data is latched and becomes the next rewrite data. At this time, the rewrite data is converted from the data of the memory cell at the time of the verify read by the previous write data. This is shown in the following (Table 1).

[0034]

[Table 1] The write operation is repeated a certain number of times for the verify read / rewrite described above, and ends. For example, 100 times. According to this verify read / rewrite, if the data of the memory cell is "0" after "1" write, "1"
Is rewritten. That is, when the threshold value of the memory cell is not 0.5 V or more, "1" writing is performed to increase the threshold value again. If the data of the memory cell is "1" after writing "1", "0"
Is rewritten. That is, if the threshold value of the memory cell is 0.5 V or more, a "0" write operation is performed so that the threshold value of the memory cell does not increase any more during rewriting. Rewriting after "0" writing always performs "0" rewriting. Only when the threshold value of the memory cell to which "1" is written does not reach 0.5 V, "1" writing is performed again, and an unnecessary threshold value of the memory cell to which "1" is written. Can be suppressed.

The control gates CG1 to CG8 and the select gates SG1,
The potential of SG2 is as shown in (Table 2). In Table 2, the control gate CG2 is selected and the bit line BL2i is selected.
Shows the potential relationship when is selected.

[0036]

[Table 2] In this manner, in the embodiment, the unnecessary increase in the threshold value of the memory cell at the time of "1" write by the verify write can be prevented, so that the reliability of the NAND EEPROM is improved and the control circuit area is reduced. The increase can be effectively suppressed.

FIG. 10 shows a main configuration of a second embodiment of the present invention, which is a specific configuration of the bit line control circuit 2. As shown in FIG. The CMOS flip-flop FF constituting the data latch and sense amplifier in this embodiment is a signal synchronous CMOS inverter composed of E-type, p-channel MOS transistors Qp3, Qp4 and E-type, n-channel MOS transistors Qn17, Qn18. , E-type, p-channel MOS transistors Qp5, Qp6 and a signal synchronous CMOS inverter composed of E-type, n-channel MOS transistors Qn19, Qn20.

The output node of the CMOS flip-flop FF and the bit line BLi are connected via an E-type, n-channel MOS transistor Qn21 controlled by a signal φF.

Between the bit lines BLi and Vcc, an E type controlled by the output node of the flip-flop FF,
An n-channel MOS transistor Qn22 and an E-type, n-channel MOS transistor Qn23 controlled by a signal φV are connected in series. By these transistors, the bit line BLi is charged to Vcc-Vth in accordance with the data of the CMOS flip-flop at the time of verify reading.

E type, p channel MOS transistor Qp7 and D type, n channel MOS transistor QD1
Is a circuit for precharging the bit line BLi to Vcc. The transistor QD1 is provided to prevent a high voltage from being applied to the transistor Qp7 during erasing or writing. The E-type, n-channel MOS transistor Qn24 is a reset transistor for resetting the bit line BLi to 0V.

The two nodes of the CMOS flip-flop FF are connected to input / output lines IO, / IO via E-type transfer gates n-channel MOS transistors Qn15 and Qn16 which are controlled by a column selection signal CSLi.
It is connected to the.

The operation of the bit line control circuit of this embodiment will now be described.

FIG. 11 shows the operation timing at the time of reading. The signal φF becomes "L" and the bit lines BLi and C
MOS flip-flop FF is cut off. When the precharge signals φP and / φP become “H” and “L”, respectively, the bit line BLi is precharged to Vcc.
Thereafter, the selection gates SG1, SG2 and the control gate CG1
To CG8, a voltage is output from the row decoder 5. For example, if CG2 is selected, SG1, SG2, CG1
, CG3 to CG8 become Vcc, and CG2 becomes 0V. When the data of the memory cell is "0", the bit line BLi is at "L" level, and when the data is "1", it remains at "H" level.

After the selection gate and the control gate are reset to 0 V, the signals φSP and φRP become “H”, φSN and φRN become “L”, and the CMOS flip-flop FF becomes inactive. φF becomes “H”, and the potential of the bit line BLi is transmitted to the output line of the CMOS flip-flop FF. Then, .phi.SP becomes "L" and .phi.SN becomes "H", the potential of the bit line BLi is sensed, and .phi.RP becomes "L" and .phi.RN becomes "H", and the sensed data is latched. The latched read data is output to the input / output lines IO and / IO when the column selection signal CSLi becomes "H".

FIG. 12 shows the operation during write / write verify. Write data is input / output lines IO, / I
After latching from O into the CMOS flip-flop FF, the precharge signal φP becomes “H” and / φP becomes “L”, and the bit line BLi is precharged to Vcc.
The voltage VMB changes from Vcc to the intermediate potential VM (up to 10 V). Thereafter, the signal φF becomes VM, and the bit line BLi becomes 0 V or VM depending on the latched data. The voltage is 0 V for "1" programming and VM for "0" programming.
At this time, the selection gate SG1 is VM, SG2 is 0V, and if the control gate is CG2, CG1 becomes VM, C
G2 is the high voltage Vpp (up to 20V) and CG3 to CG8 are VM
It is.

Select gates SG 1 and SG 2, control gate C
When G1 to CG8 are reset to 0V, the signal .phi.F becomes "L" and the reset signal .phi.R becomes "H", and the bit line BLi is reset to 0V. Subsequently, a verify read operation is performed.

In the verify read operation, similarly to the normal read operation, first, the precharge signal φP becomes “H” and / φP becomes “L”, and the bit line BLi is precharged to Vcc. Thereafter, the selection gate and the control gate are driven by the row decoder 5. After the selection gates SG1 and SG2 and the control gates CG1 to CG8 are reset, the verify signal φV becomes "H", and Vcc-Vth is output only to the bit line BLi to which "0" has been written.

Thereafter, φSP and φRP become “H”, φSN and φRN
Becomes "L" and .phi.F becomes "H". After the signal φSP becomes “L” and φSN becomes “H” and the bit line potential is sensed, the signal φRP becomes “L” and φRN becomes “H”, and the rewrite data is latched. At this time, the relationship between the write data, the data in the memory cell, and the rewrite data is as described in the previous embodiment (Table 1).

The write / write verify operation is repeated, for example, about 100 times, and the operation ends. Erasure in this example,
Bit line BLi during write, read, and verify read
, Select gates SG1 and SG2, control gates CG1 to CG
The potential of G8 is shown in (Table 3). Here, a case where CG2 is selected is shown.

[0050]

[Table 3] In the above embodiment, the threshold evaluation criterion in the verify operation is set to 0.5 V, but this can be set to another appropriate value in relation to the allowable threshold distribution. The same applies to one writing time. For example, in order to make the final threshold distribution smaller, one writing time is made shorter and the writing / verifying operation is repeated little by little. do it. In the embodiment, the NAND cell type EEPROM using the tunnel injection has been described. However, the NAND cell type EEPROM using the other method such as hot electron injection may be used.
If M, the present invention is effective.

The embodiment of FIG. 5 can be applied to the case where the cell array is of the open bit line type.

FIG. 13 shows a configuration of a NAND cell type EEPROM according to the third embodiment of the present invention. The basic configuration is the same as the embodiment of FIG. 1, but in this embodiment,
The cell array 1 is divided into two blocks 1A and 1B,
A bit line control circuit 2 is provided commonly to these cell array blocks 1A and 1B.

FIG. 14 shows the configuration of the bit line control circuit 2. The basic configuration is the same as that of the previous embodiment shown in FIG. In this embodiment, two nodes N1 and N2 of a CMOS flip-flop FF constituting a data latch / sense amplifier are connected to transfer gate MOS transistors, respectively.
Via transistors Qn7 and Qn8, bit lines BLai (i = 0, 2,...) In cell array blocks 1A and 1B,
BLbi (i = 0, 1,...).

Also, in this embodiment, unlike FIG.
An activation n-channel MOS transistor Qn25 controlled by a clock φN is provided at a common source node on the NMOS side of the OS flip-flop FF.
An activation p-channel MOS transistor Qp8 controlled by the clock φP is provided at the S-side common source node.

Next, the EEPROM constructed as above will be described.
Will be described with reference to FIGS. 15 and 16 show read operation timings, and FIGS. 17 and 18 show write / write verify read operation timings.

In the read operation, first, the signals φA and φB become “L”, and the CMOS flip-flop FF is disconnected from the bit line BL. The precharge signals φPA and φPB become “H”, and the bit line is precharged. FIG.
In the example shown in FIG. 16, the bit line BLai of the cell array block 1A is selected first, and the bit line BLbi of the cell array block 1B is selected in the next read cycle. Hereinafter, the first read cycle will be described.

The bit lines BLai and BLbi are precharged to 3 V and 2 V, respectively, by the precharge signals φPA and φPB. When the precharge is completed, φPA and φPB become “L”, and the bit lines BLai and BLbi enter a floating state. Thereafter, a desired voltage is output from the row decoder 5 to the selection gate and the control gate. For example, control gate C
When G2 is selected, CG1, CG3 to CG8 are Vcc,
CG2 becomes 0V, and SG1 and SG2 become Vcc. According to the data of the memory cell, when the value is "1", the threshold value of the memory cell is positive, so that no cell current flows and the potential of the bit line BLai remains at 3V. In the case of data "0", a cell current flows and the potential of the bit line BLai drops to 2 V or less.

Thereafter, when φP goes to the “H” level, φN goes to the “L” level, and φE goes to the “H” level, after the CMOS flip-flop FF is equalized, the signals φA and φB go to “H”. Bit line BLa
i, BLbi and a CMOS flip-flop are connected.
When .phi.P becomes "L" level and .phi.N becomes "H" level, the bit line voltage is differentially sensed and the read data is latched as it is.

When the column selection signal CSLi becomes "H", the read data is output to the IO and / IO lines, transmitted to the data output buffer 6, and taken out. When the bit line BLbi of the cell array block 1B is selected, the operations of φPB and φPA and the operations of VSA and VSB may be switched.

Next, the write operation will be described. FIG.
7 and FIG. 18 show the write / read operation of the bit line control circuit 2 except for the operation of loading the write data from the input / output buffer 6.
The write verify read operation is shown when the number of bits BLai on the cell array block 1A side is selected. Prior to writing, all the control gates of the memory cells are set to 0 V, and the p substrate (or p substrate) on which the memory cells are formed is formed.
(Type well and n-substrate) at a high voltage VPP (up to 20 V), and data is collectively erased. Write data is transferred from the data input / output buffer 6 to the CMOS via the input / output lines IO and / IO.
After being latched by the flip-flop FF, first, the precharge signals φPA and φPB become “H” level. As a result, all the bit lines are reset.

Thereafter, when φA and VSW become VM (（10 V), the bit line BLai becomes VM when it is “0” and becomes 0 V when it is “1” according to the data. When, for example, the control gate CG2 is selected by the row decoder 5, SG1
, CG1, CG3 to CG8 are VM, CG2 is Vpp, S
G2 is set to 0V.

After the control gates CG1 to CG8 and the selection gate SG1 are reset to 0 V after a predetermined time (up to 40 μsec), the signal φA becomes 0 V, the bit line BLai and the CMOS flip-flop are disconnected, and the signal φPA becomes “ When the signal level goes high, all bit lines are reset to 0V. VSW becomes Vcc.

Next, a write verify read operation is performed. As in the previous embodiment, 0V is applied to the selected control gate.
Is applied in place of, for example, a verify signal φAV
Is output. First, the bit line BLai is set to 3V, BLbi
Is precharged to 2 V, and then the precharge signal φ
When PA and φPB go to “L” level, bit lines BLai and BL
bi is floating. The control gate and the selection gate are selected by the row decoder 5, and SG1, CG1, CG3
CG8 is set to Vcc, and CG2 is set to, for example, 0.5V. In normal reading, if the threshold value of the memory cell is 0 V or more, "1" is read, but in verify reading, 0.5 is read.
If it is not more than V, it cannot be read as "1".

Thereafter, if the bit line BLai has been "0" -written, the verify signal φAV causes Vcc-
Charged to Vth. Here, the voltage level of the precharge performed by the verify signal may be higher than the precharge voltage of the selected bit line. After the CMOS flip-flop is reset by the equalizing signal .phi.E, .phi.A and .phi.B become "H", the nodes N1 and N2 are respectively connected to the bit lines BLai and BLbi, and .phi.P becomes "L".
Level, .phi.N attains "H" level, and the data on bit line BLai is read. The read data is latched and becomes the next rewrite data. At this time, the rewrite data is converted from the data of the memory cell at the time of the verify read by the previous write data. This data conversion is the same as in the previous embodiment (Table 1).

The write operation is repeated a certain number of times, for example, 100 times, and the verify read / rewrite is completed. The verify read / rewrite of this embodiment also suppresses an unnecessary rise in the threshold value of the memory cell to which "1" is written, as in the previous embodiment.

The potentials of the control gates CG1 to CG8 and the select gates SG1 and SG2 at the time of erasing, writing, verify reading and reading in this embodiment are as shown in Table 4. Table 4 shows the potential relationship when the control gate CG2 is selected and the bit line BLai is selected.

[0067]

[Table 4] The present invention can be applied to a NOR type flash EEPROM. The embodiment will be described below.

FIG. 19 shows a memory cell array of a flash EEPROM according to a fourth embodiment of the present invention.
To lower the threshold value of the memory cell (set the data to "1"), about -12
A voltage of V is applied, and Vcc is applied to the drain. At this time, 0 V is applied to the drain of the memory cell that does not want to change the threshold value by sharing the control gate with the selected memory cell.

At one end of the bit line, a bit line control circuit including a data latch and sense amplifier shown in FIG. 20 is provided to latch data as to whether or not to change the threshold value of the memory cell. I have.

In this embodiment, after the operation of lowering the threshold value of a certain memory cell is performed, a predetermined verify voltage is applied to the control gate of the memory cell to evaluate the threshold value of the memory cell. If there is a memory cell that has not reached the desired threshold value, the operation of lowering the threshold value is performed again only for that memory cell. By repeating this operation, it is confirmed that the threshold value of the memory cell is within a desired allowable range, and the verify operation is completed.

FIG. 20 shows a CMOS flip-flop which serves as a data latch and sense amplifier connected to bit lines BLai and BLbi in each of cell array blocks 1A and 1B when the memory cell array is divided into two blocks 1A and 1B. 3 shows a configuration of a bit line control circuit including FFs. The basic configuration is the same as FIG. 5 of the previous embodiment. E type, n-channel MOS transistor Qn31,
Qn32, Qn34 and Qn35 are elements for verify reading. E type, n channel MOS transistor Q
n33 and Qn36 are for precharging and resetting the bit line.

The write and verify operations of this embodiment will now be described with reference to the timing chart of FIG. First, memory cells are erased for each word line prior to data writing. This data erasing is performed by applying a high voltage Vpp to the word line WLi that commonly connects the control gates of the memory cells.
(Up to 20 V) and 0 V to the bit line. As a result, electrons are injected into the floating gate of the memory cell, and the threshold becomes higher than Vcc.

Data writing is performed for one page at a time. First, the precharge signal φPA goes to “L” level, and the bit line BLai floats. Next, the word line WLaj becomes about -12V. When φA goes to the “H” level, the bit line BLai is at Vcc when “1” is written (electrons are emitted from the floating gate), and when “0” is written (electrons in the floating gate are not emitted), the bit line BLai is at Vcc. 0
V. After the word line is reset, φPA becomes “H”
Level, the bit line is reset, and the writing ends.

Next, a verify read operation is performed. First, VA becomes about 3 V, VB becomes about 2 V, and the bit line BL
ai is precharged to about 3V and BLbi is precharged to about 2V.
Further, φPA and φPB become “L” level, and bit line B
Lai and BLbi become floating. Then, the word line is set to a verify voltage of about 3.5 V and reading is performed. When "0" is written in the memory cell, the bit line BLai remains at 3V. When "1" is written to the memory cell and the threshold voltage is equal to or higher than 3.5 V, the potential of the bit line BLai decreases.

After the word line goes to 0 V, φAV goes to “H”.
Become a level. If "0" data is latched, that is, if "0" is to be written to the memory cell, or if "1" has already been written and it is not necessary to write "1" more than necessary, Both the MOS transistors Qn31 and Qn32 are turned on, and the bit line BLai becomes 0V. However, it does not have to be 0 V as long as it is lower than the potential of the dummy bit line. When "1" is written, the MOS transistor Qn3
Since 2 is off, the potential of the bit line BLai does not change.

When φP and φN become (）) Vcc, φφ
E becomes “H” level, and the flip-flop FF is equalized. φP becomes Vcc and φN becomes 0 V, and the bit line potential is read out and latched as it is to become the next rewrite data.

At this time, the relationship among the write data, the read data, and the rewrite data is the same as that described in the previous embodiment (Table 1).

In this embodiment, the cell array is p
Formed in a p-type well, and -12 V,
Vcc may be applied to the selected word line, and -12 V may be applied to the unselected word lines.

When "writing" described in the embodiment is changed to "erasing", the n-channel MOS transistor Q
By omitting n31, Qn32, Qn34, Qn35, the threshold distribution after erasing can be reduced by the same method as in the embodiment.

Next, the row decoder used in the above embodiment will be described. FIG. 22 shows the NA in FIGS.
The specific configuration of the row decoder 5 of the ND cell type EEPROM is shown.

The row decoder is an E type, n channel M
An enable circuit including OS transistors Qn41 and Qn42 and E-type and p-channel MOS transistors Qp11 and Qp12, and an E-type and n-channel MOS transistor Qn4
3, a transfer circuit comprising Qn44 and an E type, p-channel MOS transistor Qp13, Qp14. Address signal ai and decoder enable signal RDENB
Thereby, the row decoder is activated and a block is selected. At the time of erasing, φER becomes “H” and operates. Also,
The voltage VppRW is Vcc at the time of reading, and Vcc at the time of erasing / writing.
pp (〜20 V).

The E type, n channel MOS transistors Qn50 to Qn69 and the E type, p channel MOS transistors Qp20 to Qp29 have select gate potentials SG1D, SG2D.
And the control gate potentials CG1D to CG8D and the potential of Vuss,
A transfer gate that receives and outputs the output of the row decoder. Vuss, SG1D, SG2D, CG1D to CG8D are signals common to each row decoder.

Select gates SG1 and SG2 and control gates CG1 to CG during reading, writing, erasing and verify reading
G8, bit line, signals SG1D, SG2D, CG1D to CG8
Table 5 shows the potentials of D, Vuss, and VppRW. (Table 5)
Shows a case where the control gate CG2 is selected and the bit line BLai is selected.

[0084]

[Table 5] FIG. 23 shows another embodiment of the row decoder 5, and each potential is as shown in (Table 6). FIG. 24 shows still another embodiment of the row decoder 5, which is an E-type, p-channel MOS transistor Qp30 in the configuration of FIG.
To Qp39. In the configuration of FIG. 23, the potential of the non-selection control gate at the time of erasing is Vpp-VH1,
As long as the data holding characteristics of the memory cell are not adversely affected, the circuit area is smaller than that of FIG.

[0085]

[Table 6] Although the power supply voltage is set to 5 V in the bit line control circuit 2 shown in FIGS. 5, 10, and 14, an embodiment in which the power supply voltage is operated at a low voltage such as 3 V of two batteries will be described below. First, n-channel MOS transistors Qn10 and Qn11
Threshold voltage Vth of another E type, n channel MOS
It is assumed to be lower than the threshold value of the transistor. This is because if the threshold value remains high, the voltage transfer efficiency is poor. This Vth should be Vcc−Vth (VRH)> VRH Vth (VRL)> − VRL.

VRH is a bit line voltage of "H" level at the time of reading, and VRL is a bit line voltage of "L" level. Vcc =
When VRH = 1.4V and VRL = 1.2V at 3V, Vth
(1.4 V) <1.6 V, Vth (1.2 V)>-1.2
V. Here, VB indicated as Vth (VB) indicates a back bias voltage. Other E-type, n-channel MO
Since the leak current increases when Vth is lowered, the S transistor is normally used without changing Vth. For this purpose, the circuits shown in FIGS. 25 and 26 are used as driving circuits for the signals φPA, φPB, φAV, φBV, φA, φB, φE.

In the circuit shown in FIG. 25A, the "H"
The level can be higher than Vcc. That is, FIG.
As shown in (b), after waiting for a delay time τ1 after the input signal Vin becomes Vcc, the D-type, n-channel
The voltage of the gate of the S-transistor QD2 becomes 0 V, and τ2 time later, the capacitor C1 raises the voltage Vout higher than Vcc.

The circuit shown in FIG. 26A is obtained by attaching a high voltage (for example, a voltage such as 10 V (VM) or 20 V (Vpp) used for writing) to the circuit shown in FIG. In this case, as shown in FIG. 26B, the gate of the D-type, n-channel MOS transistor QD3 becomes 0 V after τ1 hour after the input signals Vin3 and Vin2 become Vcc, and the output is further outputted by the capacitor C2 after τ2 time. Vout is boosted from Vcc. In the case of outputting a high voltage, as shown in FIG. 26 (c), after Vin3 becomes Vcc, Vin1 is set to 0V and the gate of QD3 is set to 0V. Thereafter, if Vin4 is set to Vcc, VM or Vpp is output from the high voltage switching circuit.

The bit line control circuit 2 thus configured
27 to 30 are shown in FIGS. Except that each signal is boosted as needed, it is the same as FIG. 15 to FIG. 18, and detailed description is omitted.

FIG. 14 shows another embodiment for reducing the power supply.
Will be described as an example. Here, Qn10 and Qn11 are normal E type, n channel MOS transistors,
It is composed of MOSs Qn5, Qn6, Qn25, Qp1, Qp2, and Qp8, and boosts the VSW voltage of the flip-flop at the time of verify reading. This verify operation is shown in FIG. V
This is the same as FIG. 30 except that the SW is boosted.

FIG. 32 shows various embodiments of the bit line control circuit 2 of the NAND type EEPROM.
n9, Qn10, Qn22, Qn23 in FIG. 10, Qn9, Q in FIG.
This diagram schematically shows the relationship between the n10 or Qn11 and Qn12 transistors, the CMOS flip-flop FF, and the selected bit line. Thus, even if the n-channel MOS transistor is a p-channel MOS transistor, it can be easily realized only by changing the connection of the transistors.

FIG. 33 shows various embodiments of the bit line control circuit 2 of the flash EEPROM, and shows the relationship between Qn31, Qn32 or Qn34, Qn35 of FIG. 20, the CMOS flip-flop FF, and the selected bit line. is there.
Also in this case, even if the n-channel MOS transistor is a p-channel MOS transistor, it can be easily realized only by changing the connection of the transistors.

In FIG. 5, for example, the drain of the MOS transistor Qn9 is set to the power supply voltage Vcc. However, this voltage may be higher than the "H" level voltage of the bit line at the time of reading. Similarly, in FIG. 20, the MOS transistor Qn32
Are grounded, it is sufficient that this voltage is not more than the "L" level of the bit line at the time of reading.

FIG. 34 shows the EEPR constructed as described above.
5 shows a flowchart at the time of OM write / write verify operation. In (a), first, write data is input in a page mode, and then write is performed. Thereafter, write verify reading is performed. If the output data is all "1", the writing is completed, and if not, rewriting is performed.

In (b), after writing / writing verification is repeated n times (for example, 10 times), all “1” s are determined. As a result, data is not output each time, so that when the total number of repetitions is large, the total writing time is shortened.

[0096]

As described above, according to the present invention, the memory finally written is controlled by performing the write verify control without increasing the circuit area and without performing unnecessary additional writing. An EEPROM can be obtained in which the threshold voltage distribution of cells can be set in a small range.

[Brief description of the drawings]

FIG. 1 is a NAND cell type EEPROM according to a first embodiment;
A block diagram showing a configuration of the OM;

FIG. 2 is a plan view and an equivalent circuit diagram showing an AND cell configuration according to the first embodiment;

FIG. 3 is a sectional view taken along line AA ′ and BB ′ in FIG.

FIG. 4 is an equivalent circuit diagram of a memory cell array according to the first embodiment;

FIG. 5 is a diagram illustrating a configuration of a bit line control circuit unit according to the embodiment;

FIG. 6 is a timing chart showing a data read operation of an even-numbered column in the embodiment.

FIG. 7 is a timing chart showing a data read operation of an odd-numbered column in the embodiment;

FIG. 8 is a timing chart showing data write and verify read operations in the embodiment.

FIG. 9 is a timing chart showing rewrite and verify read operations in the embodiment.

FIG. 10 is a diagram illustrating a configuration of a bit line control circuit unit according to a second embodiment;

FIG. 11 is a timing chart showing a data read operation in the second embodiment;

FIG. 12 is a timing chart showing data write and verify operations in the second embodiment;

FIG. 13 shows a NAND cell type EEP according to a third embodiment.
Block diagram showing a configuration of a ROM,

FIG. 14 is a diagram illustrating a configuration of a bit line control circuit unit according to a third embodiment;

FIG. 15 is a timing chart showing a read operation of an even-numbered column in the third embodiment;

FIG. 16 is a timing chart showing a read operation of an odd-numbered column in the third embodiment;

FIG. 17 is a timing chart showing a data write operation in the third embodiment;

FIG. 18 is a timing chart showing a verify read operation in the third embodiment;

FIG. 19 is a NOR type EEPROM according to a fourth embodiment;
Diagram showing the cell array configuration of

FIG. 20 is a diagram illustrating a configuration of a bit line control circuit unit according to a fourth embodiment;

FIG. 21 is a timing chart showing a write and verify operation in the fourth embodiment;

FIG. 22 is a diagram showing a specific configuration of a row decoder of a NAND cell type EEPROM;

FIG. 23 is a diagram showing a specific configuration of a row decoder of a NAND cell type EEPROM;

FIG. 24 is a diagram showing a specific configuration of a row decoder of a NAND cell type EEPROM;

FIG. 25 is a diagram showing a specific configuration of a driving circuit for boosting a signal potential;

FIG. 26 is a diagram showing a specific configuration of a driver circuit for boosting a signal potential;

FIG. 27 is a timing chart showing a data read operation of an even-numbered column;

FIG. 28 is a timing chart showing a data read operation of an odd-numbered column;

FIG. 29 is a timing chart showing a data write operation;

FIG. 30 is a timing chart showing a verify read operation;

FIG. 31 is a timing chart showing a verify read operation;

FIG. 32 is a diagram showing a specific configuration of a bit line control circuit of a NAND type EEPROM;

FIG. 33 is a diagram showing a specific configuration of a bit line control circuit of a flash EEPROM;

FIG. 34 is a flowchart showing the write / write verify operation of the EEPROM.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... memory cell array, 2 ... bit line control circuit, 3 ... column decoder, 4 ... address buffer, 5 ... row decoder, 6 ... data input / output buffer, 7 ... substrate bias circuit, FF ... CMOS flip-flop (data latch and sense Amplifier).

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Hideko Ohira 1 Kosuka Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba Research Institute, Inc. (56) References JP-A-2-249197 JP-A-2-142000 (JP, A) JP-A-2-126497 (JP, A) JP-A-1-118297 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 16 / 00-16/34

Claims (24)

(57) [Claims] 1. A memory cell array in which a charge storage layer and a control gate are laminated on a semiconductor substrate, and memory cells in which memory cells are electrically rewritten by transferring charges between the charge storage layer and the substrate are formed. A data latch / sense amplifier, which is provided at one end of the cell array in the bit line direction and performs a sense operation and a latch operation of write data, and simultaneously writes data by setting a unit write time to a predetermined range of memory cells of the memory cell array Verifying means for reading the memory cell data and rewriting when there is a memory cell with insufficient writing, and, during a write verify operation, the data of the read memory cell and the data latch and sense By taking the logic with the write data latched by the amplifier, the bit The nonvolatile semiconductor memory device characterized by comprising a means for automatically setting the rewriting data Taratchi and sense amplifiers. 2. The data latch and sense amplifier is a CMO
S flip-flop, one node of which is connected to a bit line via a transfer gate, one end of which is connected to the bit line as means for automatically setting the rewrite data, and whose gate is one of the CMOS flip-flops. A first MOS transistor connected to the node, provided between the other end of the MOS transistor and a power supply;
Second MOS controlled by verify control clock
2. The nonvolatile semiconductor memory device according to claim 1, further comprising a transistor. 3. A plurality of nonvolatile memory cells, and a plurality of nonvolatile memory cells each holding control data of a first logic level or a second logic level for determining whether or not to apply a write voltage to each of the memory cells. A data circuit, wherein the write voltage is applied to a memory cell corresponding to a data circuit holding control data of a first logic level among the plurality of data circuits, The data circuit holding the control data of the first logic level detects the write state of the corresponding memory cell,
When the plurality of data circuits detect that the corresponding memory cell has reached a predetermined write state, the plurality of data circuits change the logic level of the held control data from the first logic level to the second logic level. Non-volatile semiconductor storage device. 4. A method according to claim 1, further comprising the step of causing the plurality of data circuits to initially hold initial control data, wherein the initial control data of the first logic level indicates that the corresponding memory cell has reached the predetermined write state. 4. The non-volatile semiconductor memory device according to claim 3, wherein the level is changed to a second logic level when detected. 5. The nonvolatile semiconductor memory device according to claim 4, wherein said initial control data is transferred to said plurality of data circuits via at least one input line. 6. A data buffer circuit for transferring said initial control data to said plurality of data circuits.
6. The non-volatile semiconductor storage device according to claim 5, wherein: 7. The data circuit according to claim 3, wherein a data circuit holding control data of a first logic level among the plurality of data circuits simultaneously detects a write state of a corresponding memory cell. Non-volatile semiconductor storage device. 8. When the plurality of data circuits detect that a corresponding memory cell has reached a predetermined write state, the plurality of data circuits change the logic level of the held control data from a first logic level to a second logic level. 4. The non-volatile semiconductor memory device according to claim 3, wherein said non-volatile semiconductor memory device is changed simultaneously. 9. The write voltage is simultaneously applied to a memory cell corresponding to a data circuit holding control data of a first logic level among the plurality of data circuits. Nonvolatile semiconductor memory device. 10. A semiconductor device, comprising: a plurality of bit lines connected to each of said plurality of nonvolatile memory cells; wherein said plurality of data circuits are connected to corresponding memory cells based on control data held therein. 4. The nonvolatile semiconductor memory device according to claim 3, wherein the voltage of the line is selectively changed. 11. The nonvolatile memory according to claim 10, wherein said plurality of data circuits selectively change a voltage of a bit line connected to a corresponding memory cell at the same time based on control data held. Semiconductor memory device. 12. A method of applying a write voltage to a memory cell corresponding to a data circuit holding control data of a first logic level, and a memory cell by a data circuit holding control data of a first logic level. The detection of the write state to the memory and the change of the logic level by the data circuit holding the control data of the first logic level are performed until all the plurality of data circuits hold the control data of the second logic level. 4. The non-volatile semiconductor storage device according to claim 3, wherein the operation is continued. 13. A plurality of bit lines, a plurality of word lines, a plurality of bit lines, and a plurality of word lines,
A plurality of non-volatile memory cells each having a charge storage layer; a row decoder coupled to the plurality of word lines for applying a write voltage to a selected word line; first and second input terminals and output terminals respectively Has,
A plurality of sense circuits each having a second input terminal coupled to the corresponding bit line; and a plurality of feedback circuits each coupled to the corresponding sense circuit. 1) outputting a second level to the output terminal in response to a first level of a first input terminal; (2) outputting a first state of a memory cell transferred via a corresponding bit line; Outputting the first level to the output terminal in response to the second level of the first input terminal; and (3) outputting the second state of the memory cell transferred via the corresponding bit line to the first level. Outputting a second level to the output terminal in response to a second level of the input terminal of the feedback circuit, wherein each of the feedback circuits: (1) holds first control data having a first logic level Therefore, the first level of the corresponding output terminal In response, a second level is output to a corresponding first input terminal, and (2) a second level of the corresponding output terminal for retaining second control data having a second logic level. Outputs a first level to a corresponding first input terminal in response to the control signal, and the feedback circuit corresponding to the sense circuit comprises: (1) a first control circuit for determining a write control voltage applied to a corresponding bit line; (2) When the first control data is held, a write control voltage that causes charge accumulation in the charge accumulation layer of the memory cell is applied to the corresponding bit line. When the second control data is held, a write control voltage for suppressing the accumulation of charges in the charge storage layer of the memory cell is applied to the corresponding bit line, and (3) the first control data is If so, the corresponding bit The first state of the memory cell that has not reached the predetermined write state is sensed via the scan line to hold the first control data, and the second state of the memory cell that has reached the predetermined write state is sensed.
Changing the first control data held by sensing the state of (2) to the second control data, and (4) holding the second control data when the second control data is held; A nonvolatile semiconductor memory device characterized by the above-mentioned. 14. A plurality of bit lines, a plurality of word lines, a plurality of bit lines, and a plurality of word lines,
A plurality of non-volatile memory cells each having a charge storage layer; a row decoder coupled to the plurality of word lines for applying a write voltage to a selected word line; first and second input terminals and output terminals respectively Has,
A plurality of sense circuits each having a second input terminal coupled to the corresponding bit line; and a plurality of feedback circuits each coupled to the corresponding sense circuit. 1) in response to a first state of the memory cell transferred via the corresponding bit line and a first level of the output terminal,
Outputting a first level to the output terminal; (2) responding to a second state of the memory cell transferred via the corresponding bit line and the first level of the output terminal,
Outputting a second level to the output terminal; (3) outputting a second level to the output terminal in response to the second level of the output terminal; Outputting a second level to a corresponding first input terminal in response to a corresponding first level of the output terminal to retain first control data having a first logic level; Ii) outputting a first level to a corresponding first input terminal in response to a second level of the corresponding output terminal to retain second control data having a second logic level; The feedback circuit corresponding to the sense circuit holds (1) first control data or second control data that determines a write control voltage applied to a corresponding bit line, and (2) stores the first control data. If stored, charge accumulation in memory cells When a write control voltage that causes charge accumulation is applied to the corresponding bit line and the second control data is held, a write control voltage that suppresses charge accumulation in the charge accumulation layer of the memory cell is applied. (3) When the first control data is held, the first state of the memory cell that has not reached the predetermined write state is sensed via the corresponding bit line, and 1 of the memory cell holding the control data and reaching a predetermined write state.
Changing the first control data held by sensing the state of (2) to the second control data; (4) holding the second control data if the second control data is held; A nonvolatile semiconductor memory device characterized by the above-mentioned. 15. A plurality of bit lines, a plurality of word lines, a plurality of bit lines, and a plurality of word lines,
A plurality of non-volatile memory cells each having a charge storage layer; a row decoder coupled to the plurality of word lines for applying a write voltage to a selected word line; A plurality of sense circuits each having a second output terminal and a third input terminal, each of which has a second output terminal and a third input terminal, and a first output terminal A third input terminal is connected, and a first input terminal is connected to the second output terminal. Each of the plurality of input terminals is connected to a corresponding sense circuit and holds the first control data or the second control data. Wherein each of the sense circuits comprises: (1) a first control circuit which is held in response to a first state of a memory cell transferred via a corresponding bit line; Holding data, (2) Changing the held first control data to the second control data in response to the second state of the memory cell transferred via the corresponding bit line; (3) changing the second control data to In the case of holding, the held second control data is held as it is, and the feedback circuit corresponding to the sense circuit comprises: (1) a first control circuit for determining a write control voltage applied to a corresponding bit line; (2) When the first control data is held, a write control voltage that causes charge accumulation in the charge accumulation layer of the memory cell is applied to the corresponding bit line. When the second control data is held, a write control voltage for suppressing the accumulation of charges in the charge storage layer of the memory cell is applied to the corresponding bit line, and (3) the first control data is If you have Via a bit line, a first state of a memory cell that has not reached a predetermined write state is sensed and first control data is held, and a second state of a memory cell that has reached a predetermined write state is sensed. Changing the held first control data to the second control data, and (4) when holding the second control data, holding the second control data as it is. Non-volatile semiconductor storage device. 16. A system comprising means for initially storing initial control data in a set of a plurality of sense circuits and feedback circuits, wherein the first control data of the initial control data is the first control data when the second state is sensed. 16. The non-volatile semiconductor memory device according to claim 13, wherein the control data is changed to the second control data. 17. The nonvolatile semiconductor memory device according to claim 16, wherein said initial control data is transferred to a set of said plurality of sense circuits and feedback circuits via at least one input line. 18. The nonvolatile semiconductor memory device according to claim 17, further comprising at least one data buffer circuit for transferring said initial control data to said pair of sense circuits and feedback circuits. 19. A set of a plurality of sense circuits and a feedback circuit, which holds first control data, simultaneously detects a write state of a corresponding memory cell. The nonvolatile semiconductor memory device according to any one of the above. 20. A set of a plurality of sense circuits and a feedback circuit, when sensing a second state, holds a first state held.
16. The nonvolatile semiconductor memory device according to claim 13, wherein said control data is simultaneously changed to said second control data. 21. The method according to claim 13, wherein the set of a plurality of sense circuits and feedback circuits simultaneously apply the write control voltage to the corresponding bit line based on the control data held. The nonvolatile semiconductor memory device according to any one of the above. 22. A combination of a plurality of sense circuits and a feedback circuit selectively changing a voltage of a corresponding bit line based on held control data. 3. The nonvolatile semiconductor memory device according to 1. 23. The nonvolatile memory according to claim 22, wherein said plurality of sets of sense circuits and feedback circuits selectively and simultaneously change the voltages of the corresponding bit lines based on the control data held. Semiconductor storage device. 24. Application of a write control voltage to a corresponding bit line of a set of a plurality of sense circuits and feedback circuits, detection of a write state of a memory cell, and second control of held first control data The change to the data is performed when all of the sets of the plurality of sense circuits and the feedback circuit
16. The nonvolatile semiconductor memory device according to claim 13, wherein the control is continued until said control data is held.