JP3356439B2 - Non-volatile semiconductor memory system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

 [Object of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable nonvolatile semiconductor memory (EEPROM), and more particularly to a memory system using an EEPROM having a memory cell array having a NAND cell configuration.

[0002]

2. Description of the Related Art As one type of EEPROM, a NAND cell type EEPROM capable of high integration is known. In this method, a plurality of memory cells are connected in series in such a manner that their sources and drains are shared by adjacent ones, and are connected to a bit line as one unit. A memory cell usually has an FETMOS structure in which a charge storage layer and a control gate are stacked. The memory cell array is integrally formed in a p-type well formed in a p-type substrate or an n-type substrate. NAN
The drain side of the D cell is connected to a bit line via a selection gate, and the source side is also connected to a source line (reference potential wiring) via a selection gate. The control gates of the memory cells are continuously connected in the row direction to form word lines.

The operation of this NAND cell type EEPROM is as follows. The data write operation is performed in order from the memory cell located farthest from the bit line. A high voltage Vpp (= about 20 V) is applied to the control gate of the selected memory cell, and the intermediate potential VppM (= 1) is applied to the control gate and the selection gate of the memory cell on the bit line side from the high voltage Vpp.
0V) and apply 0V to the bit line according to the data.
Alternatively, an intermediate potential is applied. When 0 V is applied to the bit line, the potential is transmitted to the drain of the selected memory cell, and electrons are injected from the drain to the floating gate. As a result, the threshold value of the selected memory cell shifts in the positive direction. This state is, for example, data “1”.
When an intermediate potential is applied to the bit line, electron injection does not occur, so that the threshold value does not change and remains negative. This state is data "0".

[0004] Data erasure is performed simultaneously on all memory cells in a NAND cell. That is, all control gates and select gates are set to 0 V, the bit lines and source lines are set in a floating state, and a high voltage of 20 V is applied to the p-type well and the n-type substrate. As a result, in all the memory cells, electrons of the floating gate are emitted to the p-type well, and the threshold value shifts in the negative direction.

In a data read operation, the control gate of the selected memory cell is set to 0 V, and the control gates and select gates of the other memory cells are set to the power supply potential Vcc (= 5 V). This is done by detecting

As is apparent from the above description of the operation, NA
In the ND cell type EEPROM, unselected memory cells function as transfer gates during write and read operations.
From this viewpoint, the threshold voltage of the written memory cell is restricted. For example, a preferable range of the threshold value of the memory cell in which “1” is written is 0.5 to 3.0.
It is about 5V. In consideration of a change over time after data writing, a variation in manufacturing parameters of a memory cell, and a variation in power supply potential, it is required that the threshold distribution after data writing be in a smaller range.

However, in the conventional method of writing data in all memory cells under the same condition while fixing the write potential and the write time, it is difficult to keep the threshold range after "1" writing within the allowable range. . For example, the characteristics of memory cells vary due to variations in the manufacturing process. Therefore, from the viewpoint of writing characteristics, there are memory cells that are easily written and memory cells that are hardly written.
Conventionally, in general, writing is performed on all memory cells under the same condition with a sufficient write time so that sufficient writing is performed on memory cells that are difficult to write. In this case, writing is performed more than necessary in a memory cell which is easily written, and the threshold voltage becomes higher than an allowable range.

As described above, the conventional NAND cell type EEP
The ROM has a problem in that, when data is written, it is difficult for the memory cell to fall within a limited allowable threshold range because the memory cell acts as a transfer gate. Also conventional
In general, in EEPROM, data is written to a memory cell.
Data latch and read data from memory cells
Provided separately with the sense amplifier with the memory cell array interposed
This is one of the factors that hinder high integration.
Was.

SUMMARY OF THE INVENTION An object of the present invention is to provide an EEPROM system capable of performing efficient data writing and keeping the threshold value of a memory cell in a written state within a desired range. The present invention also provides data
EEP with high integration by using both switches and sense amplifiers
It is intended to provide a ROM.

[0010]

SUMMARY OF THE INVENTION The present invention is an EEPROM system having a write verify control circuit which is electrically rewritable and checks a data write state.
Means for setting a predetermined unit write time for one page of memory cells and simultaneously writing data; means for performing a write verify operation on one page of memory cells to which data has been written ; memory
If there is an insufficiently written memory cell in the cell group,
The same page until there are no insufficient memory cells
Data writing and writing by setting the same unit writing time
Means for repeating the verify operation and the data of the i-th page.
After the data writing is completed, similarly for the (i + 1) th page
Means for repeating data write and write verify operations
When writing data of the (i + 1) th page,
Total write time required for writing
Means for setting the data write time of
It is characterized by.

The present invention also relates to a nonvolatile memory cell array.
And a data input buffer for writing data and
Data latch and sense amplifier for reading data
EEPROM having a buffer and a data output buffer
And a circuit that doubles as a data latch and sense amplifier
Input terminal is connected to the bit line of the memory cell array.
A first clock signal synchronous inverter, and an input terminal.
The output terminals are each the first clock signal synchronous input.
A second clock connected to the output and input terminals of the inverter
Data latch composed of a clock signal synchronous inverter
It is characterized by having a sense amplifier.

[0012]

In the EEPROM according to the present invention, after data is written, a predetermined verify potential (for example, set between the power supply potential and the ground potential) is applied to the control gate of the memory cell by the write verify control circuit. The threshold of the memory cell can be evaluated. According to the present invention, in a system using such an EEPROM, a writing operation is added for each page if at least one memory cell in the page does not reach a desired threshold value.
Thereafter, the threshold value is evaluated again. The data write and verify operations are repeated, and when it is confirmed that the threshold values of all the memory cells are within a desired allowable range, the write operation of the page is terminated.

In such data write and write verify operations, the unit write time is set in advance, but after the data write of the i-th page is completed, the (i + 1) -th
When writing data to a page, the total writing time required for writing data to the i-th page is set as the first data writing time. By setting the total time required for writing the previous page as the initial data writing time and thereafter performing the data writing and the verify operation in the same manner as the previous page, useless repetition of the verify operation can be omitted. Therefore, according to the present invention,
Data writing is performed very efficiently, and the threshold distribution of all memory cells can be kept within a desired range after the data writing is finally completed. EEPR according to the present invention
In OM, the data latch and the sense amplifier are
A data rack with a lock signal synchronous inverter
And as a sense amplifier,
EPROM is highly integrated.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a NAND cell type EEPROM system configuration according to an embodiment of the present invention. 1 is EEPROM
A control circuit LSI chip 2 controls data rewriting of the EEPROM chip 1 in accordance with an algorithm described later in detail.

FIGS. 2A and 2B are a perspective view and a plan view of an LSI memory card which is a specific example of the system configuration of FIG. Here, four EEPROM chips 1 and one control circuit LSI chip 2 are mounted on the card body 3.
4 is an external terminal.

FIG. 3 shows the configuration of a NAND cell type EEPROM in this embodiment. Memory cell array 2
A bit line control circuit 26 is provided to perform data writing and reading for 1. The bit line control circuit 26 is connected to the data input / output buffer 25. The control gate control circuit 23 outputs a predetermined control signal to a control gate line selected by the row decoder 22 of the memory cell array 21 in accordance with each of data write, erase, read, and verify operations. The substrate potential control circuit 24 normally sets the p-type well where the cell is formed to 0.
V, which is controlled to Vpp (up to 20 V) during erasing.
The input address is transmitted to the row decoder 22 and the column decoder 27 through the address buffer 28.

FIGS. 4A and 4B are a plan view and an equivalent circuit diagram of one NAND cell portion of the memory cell array.
FIGS. 5A and 5B are sectional views taken along the lines AA 'and BB' of FIG. 4A, respectively. A memory cell array including a plurality of NAND cells is formed on a p-type silicon substrate (or p-type well) 11 surrounded by an element isolation oxide film 12. Focusing on one NAND cell, in this embodiment, eight memory cells M1 to M8 are connected in series to form one NAND cell. In each of the memory cells, a floating gate 14 (141, 142,..., 148) is formed on a substrate 11 via a gate insulating film 13, and a control gate 16 (161, 161) is formed thereon via an interlayer insulating film 15.
162,..., 168) are formed.
The n-type diffusion layers 19, which are the source and drain of these memory cells, are adjacent to each other and are commonly used, and the memory cells are connected in series. Select gates 149, 169, and 1 formed simultaneously with the floating gate and control gate of the memory cell are provided on the drain side and the source side of the NAND cell, respectively.
4 10 and 16 10 are provided. The substrate on which the elements are formed is covered with a CVD oxide film 17, on which the bit lines 1 are formed.
8 are provided. The bit line 18 is in contact with the drain-side diffusion layer 19 at one end of the NAND cell.

Control gates 1 of NAND cells arranged in the row direction
6 are arranged in common as control gate lines CG1, CG2,..., CG8. These control gate lines become word lines. Select gates 149, 169 and 1410, 16
10 also have select gate lines SG1, S1 continuously in the row direction.
It is located as G2. FIG. 6 shows such a NAND
2 shows an equivalent circuit of a memory cell array in which cells are arranged in a matrix.

FIG. 7 shows a specific configuration of the bit line control circuit 26 in FIG. E-type p-channel MOS transistor Q as sense-up and data latch circuit
p1, Qp2, Qp3, Qp4 and E-type n-channel MOS transistors Qn1, Qn2, Qn3, Qn4
Has a CMOS flip-flop.
More specifically, a p-channel MOS transistor
Qp1, Qp2 and n-channel MOS transistor Qn
1 and Qn2, the input terminal is the transfer gate Q
The first clock connected to bit line BLi via n7
And a p-channel MOS transistor
Transistors Qp3, Qp4 and n-channel MOS transistor
Star Qn3 and Qn4 are input terminals and output terminals
Are the output terminals of the first clock synchronous inverter, respectively.
And a second clock signal synchronous input connected to the input terminal.
Make up the barter. These first and second clock signals
When both the synchronous inverters are activated, the data
Flip-flop operation as a latch is performed
Become.

E type n channel MOS transistor Q
n7 is a sense amplifier / data latch circuit and bit line BLi
Is a transfer gate for controlling the data transfer. At the time of reading, the clock φCD becomes “H”, and at the time of writing, the clock φCD becomes VM (〜１０10 V).
Data transfer is performed by the transistor Qn7.

E type p channel MOS transistor Q
p5 is a bit line precharge transistor. When the control signal / PRE becomes "L", the MOS transistor Np5 is turned on, and the bit line BLi is set to Vcc = 5V.
Precharge to.

E type n channel MOS transistor Q
n8 is a reset transistor. Control signal RES
When ET becomes "H", the MOS transistor Qn8 is turned on, and the bit line BLi is reset to the ground potential.

D type n channel MOS transistor Q
D1 is for preventing a high potential from being applied to the transistors Qp5 and Qn8 when data is erased when a high potential is applied to the memory cell. The MOS transistor QD1 is turned off by setting the clock φCU to "L". As a result, no high potential is applied to the MOS transistors Qp5 and Qn8.

Next, the operation of the control circuit of FIG. 7 in each mode will be described. During standby, for example, RESET
“H”, control signal / PRE is “H”, clock φCU is
“H”, clock φCD is “H”, column select signal CSL
i is “L”, clock φA1 is “L”, clock φA2 is
“H” (or “L”), clock φB1
“H”, clock φB2 is “L”, VBT is Vcc, bit
Line BLi is 0V, and the gates of transistors Qp4 and Qn3 are
Vcc is in a reset state. At the time of data reading, the clocks φA1 and φB1 are “H” and the clocks φA2 and φB2
Becomes "L" and the flip-flop is in a non-operation state. At this time, the column selection signal CSLi is “L”, the clock φCD is “H”, the clock φCU is “H”, and the control signal / P
RE is "H", RESET is Ri Oh in the "L", VBT is Vcc
It is. Next, the control signal / PRE becomes "L", and the bit line BLi is precharged to Vcc. Control signal/
When PRE becomes "H" and the bit line BLi is in a floating state, the word line is set to a predetermined potential to read data from the memory cell. Bit line BL depending on data
i becomes "H" or "L". Clock φA2 is set to “H”, φ
Assuming that B1 is "L", data is latched if the bit line BLi is "H". Thereafter, when the clock φA1 is set to “L” and the clock φB2 is set to “H”, if the bit line BLi is “L”, data is latched at this time. By setting the column selection signal CSLi to “H”, data is transferred to the input / output lines IO and / IO.

At the time of data writing, first, the clock φC
D becomes “L”, and the bit line BLi and the flip-flop are disconnected. Next, the column selection signal CSLi is selected by the address signal, and the data is latched. Bi
When one page of data is latched by the cut line BLi (i = 1, 2,..., M), the clock φCD becomes “H”. The clocks φCD and VBT change from the power supply potential Vcc to the intermediate potential VM (（10 V), and the bit line becomes VM or OV depending on the data. When writing is completed, VBT
And φCD become Vcc, φA1 and φB1 become “H”, φ
A2 and φB2 go to “L”, and RESET goes to “H” to be reset. At the time of data erasure, the clocks φCU and φCD become “L”, and the bit line BLi
Is disconnected from the bit line control circuit.

FIGS. 8 and 9 are diagrams showing a specific configuration of the row decoder 22 in FIG. In FIG. 8, one NAND cell block is selected by an address ai and an enable signal RDENB by a NAND gate G1. The output of the gate G1 is
, And connected to the node N1 via a transfer gate composed of an E-type n-channel MOS transistor Qn9 and an E-type p-channel MOS transistor Qp6. The E-type n-channel MOS transistor Qn10 and the E-type p-channel MOS transistor Q
It is connected to the node N1 via a transfer gate consisting of p7. These transfer paths are controlled by the control signal ERAS.
E and / ERASE are selected depending on the case of reading and writing and the case of erasing.

D type n channel MOS transistor Q
D3 and QD6 are for boosting the nodes N1 and N3, respectively. I-type n-channel MOS transistor QI1, E-type n-channel MOS transistor Qn11,
The circuit constituted by Qn12 is a pump circuit for transferring the high potential Vpp to the node N3. D-type n-channel MOS transistors QD2, QD4, QD5 are for electrically isolating nodes N5 and N1, N1 and N2, and N2 and N3, respectively.

In FIG. 9, an E type n channel MOS
Transistors Qn14, Qn16, Qn18, Qn20, Qn22
, Qn24, Qn26, Qn28, Qn30, Qn32 are for selectively grounding the select gate and the control gate. E type n-channel MOS transistor Qn1
3, Qn15, Qn17, Qn19, Qn21, Qn23, Qn2
5, Qn27, Qn29 and Qn31 output the output of the control gate control circuit 23 in FIG. 3 to the selection gates SG1 and SG, respectively.
2, for selectively transferring data to the control gates CG1 to CG8. The operation of each mode of the decoder circuit section in FIGS. 8 and 9 will be described below.

When reading data, the erase signal ERAS is used.
E is "L" and / ERASE is "H". When the address signal ai and the enable signal RDENB are set to "H" and selected, the nodes N5, N1, N2 and N3 are set to Vcc,
Node N4 is at 0V. At this time, the clock φL is "H". Thereafter, the clock φL becomes “L”,
Further, when the clock φB becomes "H", the nodes N1 and N1
3 has a potential (Vcc + Vth) higher than the power supply Vcc, and a desired read voltage is output to the selection gates SG1 and SG2 and the control gates CG1 to CG8. For example, if the control gate CG2 is selected, SG1, SG2, CG1, C2
G3 to CG8 become Vcc, and CG2 becomes 0V. In the case of verify read, the voltage of the selected control gate CG2 becomes 0.5V.

In the case of data writing, ERASE is "L" and / ERASE is "H". Therefore, in the block selected as in the case of reading, the nodes N1, N2,
N3 and N5 are at Vcc, and the node N4 is at 0V. Thereafter, when the output φR of the ring oscillator is output, the nodes N1, N2, N3 and N5 of the selected block are set at Vpp (up to 2
0V). Thereafter, the clock φL changes to “L”, the clock φB changes to “H”, and the nodes N1 and N3
+ Vth, and a desired potential is output to the selection gates SG1, SG2 and the control gates CG1 to CG8. For example, when the control gate CG3 is selected, SG1 becomes VM (Ｖ1
0V), CG1, CG2 are VM, CG3 is Vpp, CG4
CG8 becomes VM and SG2 becomes 0V.

In the case of data erasure, the erase signal ERASE
Becomes "H" and / ERASE becomes "L". As a result, the nodes N1, N2, N3 and N5 of the selected block are set to 0.
V, the node N4 becomes Vcc, and the selection gates SG1 and SG
2. The control gates CG1 to CG8 become 0V. In the non-selected block, the nodes N1 and N3 are connected to V
pp + Vth, and the select gates SG1 and SG2 and the control gates CG1 to CG8 become Vpp.

In the above operation, the cell p is formed.
The potential Vwell applied to the mold well is controlled by the output of the substrate potential control circuit 27 in FIG. This gives p
The mold well potential Vwell becomes Vpp only at the time of data erasing, and is kept at 0 V otherwise.

In the system shown in FIG. 1 having the NAND cell type EEPROM having the above configuration and the basic operation mode, data write and write state confirmation (verify) are basically performed by the algorithm shown in FIG. . Here, when 512 memory cells (that is, column addresses 0 to 511) along one control gate line are set to one page, the unit write time is set to 40 μsec, and data write and verify operations are repeated in page mode. 2 shows a basic algorithm for writing data for one page.

First, N indicating the number of times of data writing is N = 1.
Is set to 0, the read address in the page is set to 0 (S1), the write mode is set (S2), the data for one page is set (S3), and 1 is set by the write pulse of 40 μsec.
Data writing for the page is performed (S4).

When the writing is completed, the mode is set to the write verify mode (S5), and the data in one page is sequentially read to check whether the writing state is sufficient (S7). If the writing is insufficient, it is determined whether or not N> 100 (S8). If NO, N is stepped up (S9), and the address in the page is reset to 0 (S10). The writing (S2, S3, S4) and the verify operation (S5, S6) are repeated again. Like this one
The writing and verifying operations are repeated little by little by shortening the writing time.

When it is confirmed by the verify operation that the data write state is sufficient, it is determined whether or not the address in the page has reached 511 (S11).
The read address is stepped up (S2), and the verify read operation is repeated for the next address.

By repeating the above operation, one page, 5
When it is confirmed that the data writing to all the 12 memory cells is sufficient (S11), the verify read mode is released (S13), and the data writing for one page is completed.

If the data writing is not completed even after repeating the data writing 100 times (S8), it is considered that there is some abnormality in the memory cell, the verify read mode is released (S14), and the writing is completed. Becomes

FIG. 11 shows an algorithm for writing and verifying data for one block (in the case of 8 NAND cells, page numbers 0 to 8) based on the algorithm of FIG. This algorithm sets the first write time for writing data on an arbitrary page to the total write time on the previous page, that is, in step S25, sets the data write time to 40 μsec per unit write time of 40 μsec.
It is characterized in that c × N is set. N is a value stored as the total number of write repetitions of the previous page (however, N = 1 for the first page).

This is a result of considering that even if there is a process variation in the threshold value of the memory cell in the EEPROM chip, the variation in one block in the chip is small with respect to the variation between the chips. is there. That is, if it is necessary to write n times of data for a certain page, it is naturally predicted that the same number of times of writing is necessary if the same writing is performed for the next page.
This is intended to omit the repetition of useless write and verify operations.

First, for the first page, N = 1 and page number = 0 are set ( S21 ), as in FIG. 10, the in-page read address = 0 (S22), the write mode setting (S23), Data setting for one page (S2
After 4), data writing is performed (S25). At this time, the data write time is set to a unit write time of 40 μsec.
Thus, initially, the write time is 40 μsec, similar to the algorithm of FIG.

When the data writing is completed, the mode is set to the verify mode (S26), the data is sequentially read, and it is confirmed whether or not the writing state is sufficient (S28). If the writing is insufficient, it is determined whether N> 100 (S29), and if NO, N is stepped up (S29).
30), the address in the page is reset to 0 (S31),
The data for one page is set again (S32), and 40 μse
The data writing of c is performed (S33), and the verify operation is repeated (S26, S27, S28). The number of repetitions N described above is stored in a counter or the like.

When it is confirmed that the write state is sufficient (S8), it is determined whether the in-page read address has reached 511, and if NO, the read address is stepped up (S35). ), Read verify is performed sequentially.

When data writing for one page is completed,
It is determined whether the page number has reached 7 (S3
6) If there is a remaining page, the page number is stepped up (S37), and the process returns to step S22 again. Then, data writing and verification are performed as in the previous page. At this time, in step (S25), the total write time in the previous page, that is, if N repeated writes have been performed in the previous page, this is stored and 40 μsec × N is set as the first data write time. Is done. Thereafter, the data write and verify operations are repeated as in the previous page. When it is determined that the data writing for all pages is completed (S36), the verify read mode is released (S38), and the data writing for one block is completed.

N = 10 for data write and verify operations
If the process is not completed even after repeating 0 times (S29), FIG.
In the same manner as in the above, it is considered that there is some abnormality, the verify read mode is released (S39), and the write operation ends.

As described above, the EEPRO of this embodiment
In the M system, by setting the first data write time of the next page in consideration of the number of times of data write of the previous page, it is possible to efficiently write data without repeating unnecessary write and verify. As a result, the threshold distribution of the memory cell to which the data is finally written can be set to a desired range.

Table 1 summarizes the potential relationship of each part in the above operation modes. Here, the case where the control gate line CG2 at the time of programming and programming verification is selected is shown.

[0049]

[Table 1]

In the embodiment, the threshold evaluation criterion in the verify operation is set to 0.5 V. However, this can be set to another appropriate value in relation to the allowable threshold distribution.
The same applies to the unit writing time of 40 μsec. For example, in order to finally set the minimum value of the threshold distribution more accurately, one writing time is shortened and the writing / verifying operation is repeated little by little. What should I do? Steps S10 and S31 in FIGS. 10 and 11 can be omitted. In the embodiment, the NAND cell type EEPROM using the tunnel injection has been described. However, the EEPROM using another method such as hot electron injection.
However, the present invention is effective. In addition, the present invention can be variously modified and implemented without departing from the spirit thereof.

[0051]

As described above, according to the present invention, by performing the write verify control while considering the time required for writing in the previous page, it is possible to efficiently write data and finally write the data. EEPRO capable of keeping the threshold distribution of the selected memory cell within a desired range
An M system can be provided. Also according to the invention
If the data latch and the sense amplifier
Data latch and sense amplifier using
Configuration as an EEPROM circuit,
Integralization can be achieved.

[Brief description of the drawings]

FIG. 1 is a diagram showing an EEPROM system configuration according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration in which the system of the embodiment is applied to a memory card.

FIG. 3 is a block diagram showing the configuration of the EEPROM of the embodiment.

FIG. 4 is a plan view and an equivalent circuit diagram of one NAND cell of the memory cell array of FIG. 3;

FIG. 5 is a sectional view taken along line AA ′ and line BB ′ in FIG.

FIG. 6 is an equivalent circuit diagram of the memory cell array of FIG. 3;

FIG. 7 is a diagram showing a configuration of a bit line control circuit of FIG. 3;

FIG. 8 is a diagram showing a part of the configuration of the row decoder unit in FIG. 3;

FIG. 9 is a diagram showing the rest of the configuration of the row decoder unit of FIG. 3;

FIG. 10 is an exemplary view showing a basic write verify algorithm of the system according to the embodiment;

FIG. 11 is a diagram showing a more specific write verify algorithm.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... NAND cell type EEPROM, 2 ... control circuit, 21
... Memory cell array, 22 row decoder, 23 control gate control circuit, 24 substrate potential control circuit, 25 data input / output buffer, 26 bit line control circuit, 27 column decoder, 28 address buffer.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Masaki Momomi 1, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Inside Toshiba Research Institute, Inc. No. 1 Toshiba Semiconductor System Technology Center Co., Ltd. (72) Inventor Shinji Saito 580-1 Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba Semiconductor System Technology Center Co., Ltd. (56) References JP-A-63- 271797 (JP, A) JP-A-63-231799 (JP, A)

Claims (1)

(57) [Claims] A nonvolatile memory cell array in which electrically rewritable memory cells are arranged; a data latch / sense amplifier connected to a bit line of the memory cell array; and a data latch / sense amplifier and a column selection transistor. A non-volatile semiconductor memory including a data input / output line connected through the data input / output line and a data input / output buffer connected to the data input / output line, wherein the data latch and sense amplifier has an input terminal connected to the bit line. And a second clock signal synchronous inverter having an input terminal and an output terminal connected to the output terminal and the input terminal of the first clock signal synchronous inverter, respectively. Prior to sensing the bit lines, the first and second clock signal synchronous inverters. Both the first and second clock signal synchronous inverters are activated to latch the data after sensing the bit line, and both the data latch and sense amplifier and the A nonvolatile semiconductor memory, wherein data transfer to and from a data input / output buffer is controlled by the column selection transistor.