JPH06120454A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To provide an NAND cell type EEPROM which sets the threshold distribution of the memory cell in a writing condition to be small without increasing the area of the control circuit. CONSTITUTION:An EEPROM is provided with a memory cell array, a data latch/sense amplifier, a verify control mechanism and rewriting data automatically setting mechanism. The data latch/sense amplifier FF is constituted of a first inverter whose output terminal is connected with the bit line (node N1) of the memory cell array and a second inverter whose input terminal and output terminal are connected with the output terminal (node N2) and the input terminal of the first inverter, respectively. At the time of detecting a logical level of the bit line during the writing verify reading operation, a transistor Qn 20 among the transistors Qn 19 and Qn 20 between the output terminal of the first inverter and grounding potential is permitted to be in a non-volatile condition and a transistor Qp5 among the transistors Qp5 and Qp6 between the output terminal of the first inverter and power source potential is permitted to be in an active condition.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM), and more particularly to an N-type nonvolatile semiconductor memory device (EEPROM).
EEPRO having a memory cell array of AND cell configuration
Regarding M.

[0002]

2. Description of the Related Art A NAND cell type EEPROM capable of high integration is known as one of EEPROMs. This is to connect a plurality of memory cells in series such that their sources and drains are shared by adjacent ones and connect them to a bit line as a unit. A memory cell is usually a FETMOS in which a charge storage layer and a control gate are stacked.
Have a structure. The memory cell array is integrated and formed in a p-type well formed on a p-type substrate or an n-type substrate. NA
The drain side of the ND cell is connected to the bit line via the selection gate, and the source side is also connected to the source line (reference potential wiring) via the selection gate. The control gates of the memory cells are continuously arranged in the row direction to form word lines.

The operation of this NAND cell type EEPROM is as follows. The data write operation is performed in order from the memory cell farthest from the bit line. A high voltage Vpp (= 20V is applied to the control gate of the selected memory cell.
Is applied to the control gate and the select gate of the memory cell on the bit line side of the intermediate potential VppM (= 1).
0V) is applied to the bit line, and 0 is applied to the bit line according to the data.
V or an intermediate potential is applied. When 0V is applied to the bit line, the potential is transmitted to the drain of the selected memory cell, and electrons are injected from the drain to the floating gate. This shifts the threshold value of the selected memory cell in the positive direction. This state is, for example, "1". When an intermediate potential is applied to the bit line, electron injection does not occur,
Therefore, the threshold value does not change and remains negative. This state is "0".

Data erasing is simultaneously performed on all memory cells in the NAND cell. That is, all control gates and select gates are set to 0V, bit lines and source lines are set in a floating state, and a high voltage of 20V is applied to the p-type well and n-type substrate
Is applied. As a result, in all memory cells, electrons in the floating gate are emitted to the p-type well, and the threshold value shifts in the negative direction.

In the data read operation, the control gate of the selected memory cell is set to 0V, the control gates and the selection gates of the other memory cells are set to the power supply potential Vcc (= 5V), and whether or not a current flows in the selected memory cell. It is performed by detecting whether or not.

As is clear from the above description of the operation, the NA
In the ND cell type EEPROM, the unselected memory cells act as transfer gates during write and read operations. From this point of view, the threshold voltage of the programmed memory cell is limited. For example, the preferable range of the threshold value of the memory cell programmed with "1" is 0.5 to 3.5V.
It will be about. Considering changes with time after data writing, variations in manufacturing parameters of memory cells, and variations in power supply potential, the threshold distribution after data writing is required to be in a smaller range.

However, in the method of fixing the write potential and the write time and writing data in all the memory cells under the same condition, it is difficult to keep the threshold value range after "1" write in the allowable range. For example, the characteristics of memory cells vary due to variations in the manufacturing process. Therefore, looking at the write characteristics, there are memory cells that are easy to write and memory cells that are hard to write.

On the other hand, the present inventors have already proposed a method of writing while adjusting the write time and performing verification so that the threshold value of each memory cell is written within a desired range. Proposed (Japanese Patent Application No. 3-343)
363). The configuration of the bit line control circuit according to this method is shown in FIG. 22, and the operation timing is shown in FIGS. However, in order to realize this method, Qn22,
It is necessary to provide a circuit for recharging the bit line at the time of verify reading such as Qn23, which causes a problem that the circuit area increases.

[0009]

As described above, the conventional N
In the AND-type EEPROM, since the memory cell acts as a transfer gate at the time of data writing, it is difficult to keep it within the allowable threshold range that is limited, and in order to solve this, the control circuit area increases. There was a problem.

The present invention has been made in consideration of the above circumstances, and an object thereof is to set a small threshold distribution of memory cells in a written state without increasing the area of a control circuit. NAND cell type EE
It is to provide a PROM.

[0011]

In order to solve the above problems, the EEPROM of the present invention has the following structure.

That is, the present invention provides a memory cell array in which a charge storage layer and a control gate are stacked on a semiconductor substrate, and memory cells arranged in an array for electrical rewriting by transfer of charges between the charge storage layer and the substrate. , A data latch / sense amplifier provided at one end of the memory cell array in the bit line direction for performing a sense operation and a latch operation of write data, and a unit write time is set in a predetermined range of memory cells of the memory cell array at the same time. Verify control means for reading the memory cell data after data writing and rewriting when there is a memory cell that is not sufficiently written, and data and data latch of the read memory cell during the write verify read operation. Also, the logic of the write data latched in the sense amplifier is taken to determine the bit depending on the write state. EEPR and means for automatically setting the rewriting data of the data latch and sense amplifier for each
In the OM, a data latch / sense amplifier has a first clock signal synchronous inverter whose output terminal is connected to a bit line of a memory cell array, and an input terminal and an output terminal of the first clock signal synchronous inverter, respectively. And a second inverter or a second clock signal synchronous inverter connected to the input terminal, the output of the first clock synchronous inverter when detecting the logic level of the bit line during the write verify read operation. At least one of the transistors between the terminal and ground potential
One of them is inactivated, and at least one of the transistors between the output terminal of the first clock synchronous inverter and the power supply potential is activated.

[0013]

In the present invention, after writing data, a predetermined verify potential (for example, set between the power supply potential and the ground potential) is applied to the control gate of the memory cell to set the threshold voltage of the memory cell. It is evaluated by the bit line control circuit. Then, if there is a memory cell that has not reached the desired threshold voltage, the write operation is added only to that memory cell. After that, the threshold voltage is evaluated again. This operation is repeated, and when it is confirmed that the threshold voltages of all the memory cells are within the desired allowable range, the write operation is ended.

As described above, according to the present invention, by shortening one data writing time and repeating the data writing in small increments while checking the degree of progress thereof,
The threshold voltage distribution of the memory cell array in which data writing is finally completed can be made small. Further, since the bit line control circuit compares the latch data with the verify read data and automatically controls the verify additional write, the same circuit as the bit line control circuit of the conventional NAND cell type EEPROM having no write verify function. It can be realized by the area, and the increase of the chip area can be prevented.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a NAN in one embodiment of the present invention.
The structure of a D-cell type EEPROM is shown. A bit line control circuit 2 is provided for performing data write / read, rewrite, and verify read with respect to the memory cell array 1. The bit line control circuit is connected to the data input / output buffer 6 and receives as an input the output of the column decoder 3 which receives the address signal from the address buffer 4. In addition, a row decoder 5 for controlling a control gate and a select gate for the memory cell array 1 is used.
And a substrate potential control circuit 7 for controlling the potential of the p substrate (or p type well) in which the memory cell array 1 is formed.

The bit line control circuit 2 is mainly composed of a CMOS flip-flop, and has a sensing operation for latching data for writing and reading the potential of the bit line, a sensing operation for verify reading after writing, and a re-operation. Latch the write data.

2A and 2B are a plan view and an equivalent circuit diagram of one NAND cell portion of the memory cell array,
3A and 3B are cross-sectional views taken along the lines AA 'and BB' of FIG. 2A, respectively. A plurality of NAs are formed on the p-type silicon substrate (or p-type well) 11 surrounded by the element isolation oxide film 12.
A memory cell array composed of ND cells is formed.
Explaining one NAND cell, in this embodiment, eight memory cells M1 to M8 are connected in series to form one NAND cell. Each memory cell has a floating gate 1 on a substrate 11 with a gate insulating film 13 interposed therebetween.
4 (14 ₁ , 14 ₂ , ..., 14 ₈ ) are formed, and the control gate 16 (16 ₁ , 1
6 ₂ , ~, 16 ₈ ) are formed and configured. The n-type diffusion layers 19 serving as the source / drain of these memory cells are connected in series so that adjacent ones are commonly used.

Select gates 14 ₉ , 16 ₉ and 14 ₁₀ , 16 ₁₀ formed at the same time as the floating gate and the control gate of the memory cell on the drain side and the source side of the NAND cell, respectively.
Is provided. The substrate on which the elements are formed is covered with the CVD oxide film 17, and the bit line 18 is provided on the substrate. The bit line 18 is in contact with the drain side diffusion layer 19 at one end of the NAND cell. The control gates 14 of the NAND cells arranged in the row direction are commonly connected to the control gate line C.
They are arranged as G1, CG2, ..., CG8. These control gate lines become word lines. Selection gate 14 ₉ ,
16 ₉ and 14 ₁₀ and 16 ₁₀ are also arranged continuously in the row direction as select gate lines SG1 and SG2.

FIG. 4 shows an equivalent circuit of a memory cell array in which such NAND cells are arranged in a matrix.

FIG. 5 shows a specific configuration of the bit line control circuit 2 in FIG. The CMOS flip-flop FF constituting the data latch and sense amplifier in this embodiment is
E type, p channel MOS transistors Qp3, Qp4 and E type, n channel MOS transistors Qn17, Qn1
Signal synchronous CMOS inverter composed of 8 (second clock synchronous inverter) and signal synchronous CMOS composed of E type, p channel MOS transistors Qp5, Qp6 and E type, n channel MOS transistors Qn19, Qn20 And an inverter (first clock synchronous inverter).

The output node of the CMOS flip-flop FF and the bit line BLi are connected via an E type, n-channel MOS transistor Qn21 controlled by the signal φF.

E type, p channel MOS transistor Qp7 and D type, n channel MOS transistor QD1
Is a circuit for precharging the bit line BLi to Vcc. The transistor QD1 is provided to prevent a high voltage from being applied to the transistor Qp7 during erasing or writing. The E type n-channel MOS transistor Qn24 is a reset transistor for resetting the bit line BLi to 0V.

Two nodes of the CMOS flip-flop FF are input / output lines IO and / IO via the E type n channel MOS transistors Qn15 and Qn16 which are transfer gates controlled by the column selection signal CSLi.
It is connected to the.

The operation of the bit control circuit of this embodiment will be described below.

FIG. 6 shows the operation timing at the time of reading. The signal φF becomes "L", and the bit lines BL1 and C
The MOS flip-flop FF is separated. The bit lines BLi are precharged to Vcc by setting the precharge signals .phi.P and /.phi.P to "H" and "L", respectively.
After that, select gates SG1 and SG2, control gate CG1
A voltage is output from the row decoder 5 to CG8. For example, if CG2 is selected, SG1, SG2, CG1
, CG3 to CG8 are Vcc, and CG2 is 0V. When the data in the memory cell is "0", the bit line BLi is at "L" level, and when the data is "1", it remains at "H" level.

After the selection gate and the control gate are reset to 0V, the signal φRP becomes "H" and φRN becomes "L", the signal φF becomes "H", and the potential of the bit line BLi becomes CMOS flip-flop. The potential of the bit line BLi is sensed by being applied to the output line of FF, and φRP is “L”, φRN
Becomes "H" and the sensed data is latched. The latched read data is output to the input / output lines I / O and / I / O when the column selection signal CSLi becomes "H".

FIG. 7 shows the operation at the time of write / write verify. Write data is input / output line I / O, / I / O
After being latched by the CMOS flip-flop FF from
The precharge signal φP becomes "H" and / φP becomes "L", and the bit line BLi is precharged to Vcc. Further, the voltage VMB changes from Vcc to the intermediate potential VM (-10 V). After that, the signal φF becomes VM, and the bit line BLi becomes 0V or VM depending on the latched data. It is 0V when "1" is written, and VM when "0" is written.
At this time, when the selection gate SG1 is VM, SG2 is 0V, and the control gate is CG2, CG1 is VM, C
G2 is high voltage Vpp (~ 20V), CG3 ~ CG8 is VM
Is.

Select gates SG1 and CG2, control gate S
When G1 to CG8 are reset to 0V, the signal .phi.F becomes "L" and the reset signal .phi.R becomes "H", and the bit line BLi is reset to 0V. Then, the verify read operation is performed.

In the verify read operation, like the normal read operation, first, the precharge signal φP becomes "H" and / φP becomes "L", and the bit line BLi is precharged to Vcc. Thereafter, the row decoder 5 drives the selection gate and the control gate. After the selection gates SG1 and SG2 and the control gates CG1 to CG8 are reset, the signal φRN
Becomes Vcc → Vss, then φF becomes Vss → Vcc, and becomes “0”.
Since Qp5 is turned on only in the CMOS flip-flop connected to the written bit line, Vcc is output only to the node N1 connected to the "0" written bit line BLi. At this time, the bit line BLi to which "0" is written is changed from "L" level to (Vcc-Vfhn).
(Vfhn is the threshold voltage of Qn21) and then the bit line potential is sensed.

After the bit line potential is sensed, the signal φRN
Becomes "H" and the rewrite data is latched. At this time, the relationship among the write data, the memory cell data, and the rewrite data is as shown in (Table 1) below.

[0032]

[Table 1] The write / write verify operation, for example, is repeated about 100 times and completed. The potentials of the bit line BLi, the select gates SG1 and SG2, and the control gates CG1 to CG8 at the time of erasing, writing, reading, and verify reading in this embodiment are
The results are shown in (Table 2) below. Here, the case where CG2 is selected is shown.

[0033]

[Table 2] FIG. 8 shows an embodiment different from FIG. 6 of the operation timing at the time of reading when the circuit of FIG. 5 is used as the bit line control circuit 2 of FIG. Initially, φSP and / φRP are “L”
Since the levels, φSN and φRN are at “H” level, CMO
The two clock signal synchronous inverters forming the S flip-flop FF are both in the active state, and the nodes N1 and N2 are latched so as to be "L" and "H" or "H" and "L", respectively. ing. Subsequently, when φRP becomes “H” and φRN becomes “L”, Qp5, Qp6, Qn19,
The clock signal synchronous inverter composed of Qn20 becomes inactive and the latched state is released.

Next, when φR becomes "H", the bit line B
Li is set to "L" level and φF is "H".
Since it is at the level, the node N1 is fixed at the "L" level. In this case, since .phi.SP is "L" and .phi.SN is "H", the clock signal synchronous inverter composed of Qp3, Qp4, Qn17 and Qn18 is inactive, so that the node N2 is "H". Fixed to the level. Then φ
When SP becomes "L" and φSN becomes "H", Qp5, Qp6, Qn1
The clock signal synchronous inverter composed of 9 and Qn20 is activated, the node N1 is "L", the node N2 is
Is latched so that it becomes "H".

Subsequently, φF becomes "L", and the bit line BL
i and CMOS flip-flop FF are separated, CM
The operation of resetting the latched state of the OS flip-flop FF ((A) in FIG. 8) ends.

Then, the precharge signals φp and φp are set to "H" and "L", respectively, so that the bit line BLi is set to V.
Precharged to cc. After this, select gates SG1,
A voltage is output from the row decoder 5 to SG2 and control gates CG1 to CG8. For example, when CG2 is selected, SG1, SG2, CG1, CG3 to CG8 are Vcc,
CG2 becomes 0V. When the data in the memory cell is "0", the bit line BLi is at "L" level, and when the data is "1", it remains at "H" level.

After the selection gate and the control gate are reset to 0V, the signal φRN becomes "L". At this time, since the nodes N1 and N2 are at "L" and "H", respectively, the node N1 is in a floating state. Then, the signal φ
F becomes "H" and the potential of the bit line BLi changes to the node N1.
And the bit line potential is sensed by the clock signal synchronous inverter composed of Qp3, Qp4, Qn17 and Qn18. Then, φRN becomes “H” and the sensed data is latched. For the read data that has been latched, the column selection signal CSLi becomes "H" and the input / output line
Output to I / O and / I / O.

When the operation timing shown in FIG. 6 is used as the normal read method, the φRP timing is different from the verify read operation timing shown in FIG.
Different signal φ between normal read operation and verify read operation
Although RP must be given, when the operation of FIG. 8 is used as a normal read method, the operation timing of the portion (a) in FIG. 8 is exactly the same as the verify read operation timing in FIG. The timing (a) in the read operation can be used also in the verify read, and the design can be simplified.

When data is read out according to the operation timing of FIG. 6, the potential of the node N1 immediately before transferring the bit line potential BLi to the node N1 via Qn21 is "H" and "L". Since there are both cases, when the capacitance of the node N1 is relatively large, the potential of the node N1 after the transfer of the bit line potential BLi to the node N1 is different between "H" and "L". Therefore, there is a risk of erroneous reading. However, when the timing of FIG. 8 is used, the potential of the node N1 immediately before the transfer of the bit line potential BLi to the node N1 is always "L", and therefore the risk of erroneous reading described above can be avoided.

FIG. 9 shows another embodiment of the normal read operation timing of the present invention, and FIG. 10 shows the read / read operation of the present invention.
Another embodiment of the operation timing at the time of write verify read will be described.

First, the operation timing of FIG. 9 will be described.
The signal .phi.F becomes "L", and the bit line BLi and the CMOS flip-flop FF are disconnected. Then, φSN becomes “L”, φRP becomes “H”, and / I / O becomes “L”,
I / O becomes "H". Next, when CDLi goes to "H", the node N1 is set to "L" and the node N2 is set to "H", which is latched. In this case, .phi.SH is set to "L" and .phi.RP is set to "H" before CSLi is set to "H" because the node N1 is "H" and the node N2 is "L".
This is to prevent a through current from flowing through the two clock signal synchronous inverters when CSLi is set to "H" and the node N1 is set to "L" and the node N2 is set to "H" for the S flip-flop. In this case, since Qp4 and Qn19 are conductive, the node N1 is latched at "L" and the node N2 is latched at "H". Subsequently, after φSH goes to "H" and φRP goes to "L", CSLi goes to "L", and then I / O, /
Both I / Os are set to a potential between 0 V and Vcc. At this point, the operation of resetting the latched state of the CMOS flip-flop FF ((C) in FIG. 9) ends.

Then, the precharge signals φp and / φp become "H" and "L", respectively, so that the bit line BLi
Is precharged to Vcc. After this, the selection gate SG
A voltage is output from the row decoder 5 to 1, SG2 and control gates CG1 to CG8. For example, when CG2 is selected, SG1, SG2, CG1, CG3 to CG8 are Vc.
c and CG2 become 0V. Memory cell data is "0"
In this case, the bit line BLi is at "L" level, and when the data is "1", it remains at "H" level.

After the selection gate and the control gate are reset to 0V, the signal φSP becomes "H" and φRH becomes "L". At this time, the nodes N1 and N2 are "L" and "H", respectively.
Therefore, the nodes N1 and N2 are both in a floating state. Then, when .phi.F becomes "H", the potential of the bit line BLi is transmitted to the node N1. When the potential of the node N1 is higher than the threshold voltage of Qn18, Qn18 is turned on, so that the node N2 becomes "L". Then Q
Since p6 turns on, the node N1 and Vcc become conductive, and BLi
And node N1 is charged. Further, when the potential of the node N1 after φF becomes "H" is lower than the threshold voltage of Qn18, Qn18 does not turn on, so the potential of the node N2 remains "H", and therefore Qp6. Is in the off state, and the potential of the node N1 does not change. Then, φSP becomes “L” and φRN becomes “H”, and the sensed data is latched. Then, φRN becomes “H” and the sensed data is latched. For the read data latched, the column selection signal CSLi becomes "H", and the input / output line I / O,
It is output to / I / O.

Next, the operation timing of FIG. 10 will be described. Write data from I / O line I / O, / I / O to CMOS
After being latched by the flip-flop FF, the precharge signal .phi.p becomes "H" and /.phi.p becomes "L", and the bit line BLi is precharged to Vcc. Further, the voltage VMB changes from Vcc to the intermediate potential VM (-10 V). After that, the signal φF becomes VM, and the bit line BLi becomes 0V or VM depending on the latched data. 0 when writing "1"
In the case of writing V, "0", it is VM. At this time, the selection gate SG1 is VM, SG2 is 0V, and the control gate is CG2.
Is selected, CG1 is VM, CG2 is high voltage Vpp (~ 20V), and CG3 to CG8 are VM.

Select gates SG1 and SG2, control gate C
When G1 to CG8 are reset to 0V, the signal .phi.F becomes "L" and the reset signal .phi.R becomes "H", and the bit line BLi is reset to 0V. Then, the verify read operation is performed.

In the verify read operation, as in the case of FIG. 9D, first, the precharge signal φp is "H", / φ.
p becomes "L" and precharged to the bit line BLi. Thereafter, the row decoder 5 drives the selection gate and the control gate. After the selection gates SG1 and SG2 and the control gates CG1 to CG8 are reset, the signal .phi.SP becomes "H", .phi.RN becomes "L", and then .phi.F becomes "H". At this time, since Qp5 is turned on only in the CMOS flip-flop connected to the "0" written bit line, Vcc is output only to the node N1 connected to the "0" written bit line BLi. . At this time, the "0" written bit line BLi is charged from "L" level to (Vcc to Vfhn) (Vfhn is the threshold voltage of Qn21), and the bit line potential is subsequently sensed. After the bit line potential is sensed, the signal φSP becomes “L” and φRN becomes “H”, and the rewrite data is latched. At this time, the relationship among the write data, the memory cell data, and the rewrite data is as described above (Table 1).

FIG. 11 shows the configuration of the bit line control circuit 2 according to another embodiment of the present invention. The circuit configuration shown in FIG. 11 is obtained when the circuit shown in FIG. 5 has an open bit line structure.
Similarly to the BLi side, a memory cell, a charging Tr, (corresponding to Qp7 and QD1 on the BLi side), a discharging Tr, (corresponding to Qn24 on the BLi side) are connected to the bit line BLj side. However, it is omitted in FIG. The operation timing when BLi is selected as the selected bit line will be described below with reference to FIGS.
Even when Lj is selected, similar operations such as reading and writing can be performed only by inverting the voltage of the data lines of I / O and / I / O as compared with the case of selecting BLi.

FIG. 12 shows the timing of the normal read operation when the circuit of FIG. 11 is used as the bit line control circuit 2.
FIG. 13 shows the operation timing at the time of write / write verify read.

First, the operation timing of FIG. 12 will be described. The portion (A) in FIG. 12 has the same operation timing as the portion (A) in FIG. 8, and the dummy bit line BLj is set to the “H” level voltage (Vcc-Vthn) at the time when (E) ends. ing. In (f), first, the precharge signals .phi.p and .phi.p become "H" and "L", respectively, so that the bit line BLi is precharged to Vcc. After this, select gates SG1 and SG2, control gates CG1 to C
A voltage is output from the row decoder 5 to G8. For example,
If CG2 is selected, SG1, SG2, CG1, C
G3 to CG8 are Vcc and CG2 is 0V. When the data in the memory cell is "0", the bit line BLi is at "L" level, and when the data is "1", it remains at "H" level.

After the selection gate and the control gate are reset to 0V, the signal φSP becomes "H" and φRN becomes "L". At this time, the nodes N1 and N2 are "L" and "H", respectively.
Therefore, the nodes N1 and N2 are both in a floating state. Then, when .phi.F becomes "H", the potential of the bit line BLi is transmitted to the node N1. When the potential of the node N1 is higher than the threshold voltage of Qn18, Qn18 is turned on, so that the node N2 becomes "L". Then Q
Since p6 turns on, the node N1 and Vcc become conductive, and BLi
And node N1 is charged. When the potential of the node N1 after .phi.F becomes "H" is lower than the threshold voltage of Qn18, Qn18 does not turn on, and the potential of the node N2 remains "H" in the floating state. In this case, since .phi.F2 is "H", the nodes N2 and BLj are in the conductive state. Therefore, even if the node N2 is in the floating state, it is conductive with the large load capacitance BLj. 9 is not conducted, the potential of the node N2 is erroneously changed from "H" to "L" without passing through Qn17 and Qn18, as compared with the case shown in FIG.
For example, the risk of accidentally changing the potential of the node N2 due to noise or the like is reduced, and more reliable data reading can be performed. At this time, the bit line BLj changes according to the potential change of the node N2. continue,
φSP becomes “L” and φRN becomes “H”, and the sensed data is latched. For the read data that has been latched, the column selection signal CSLi becomes "H" and the input / output lines I / O, / I /
Output to O.

Next, the operation timing of FIG. 13 will be described. Write data from I / O line I / O, / I / O to CMOS
After being latched by the flip-flop FF, the precharge signal φp becomes “H” and / φp becomes “L”, and the bit line B
Li is precharged to Vcc. Also, φF2 is “L”
Therefore, the node N2 and the bit line BLj are not connected.
Then, the voltage VMB changes from Vcc to the intermediate potential VM (-10V).
Becomes After that, the signal φF becomes VM and the bit line BLi becomes 0V or VM depending on the latched data (at this time, since φF2 is "L", the potential of the bit line BLj does not change). 0V, "0" when writing "1"
In the case of writing, it is VM. At this time, when the select gate SG1 is VM, SG2 is 0V, and the control gate is CG2, CG1 is VM and CG2 is high voltage Vpp (up to 20).
In V), CG3 to CG8 are VM.

Select gates SG1 and SG2, control gate C
When G1 to CG8 are reset to 0V, the signal φF becomes "L" and the reset signal φR becomes "H", and the bit line B
Li is reset to 0V. Then, .phi.F2 becomes "H", the bit line BLj and the node N2 are connected, and then the verify read operation is started.

In the verify read operation, the precharge signal .phi.p is "H", /.phi.p as in the portion (f) of FIG.
Becomes "L" and the bit line BLi is precharged to Vcc. After that, the row decoder 5 selects the selection gate,
The control gate is driven. Select gates SG1, SG2,
After the control gates CG1 to CG8 are reset, the signal φ
SP becomes "H", φRN becomes "L", and then φF becomes "H".
Becomes At this time, only in the CMOS flip-flop connected to the bit line for which "0" is written, Qp5
Is on, so the bit line BL for which "0" was written
Vcc is output only to the node N1 connected to i. At this time, the bit line BLi in which "0" is written is charged from "L" level to (Vcc-Vthn) (Vthn is the threshold voltage of Qn21), Then, the bit line potential is sensed. At this time, since the node N2 at the time of verify read is connected to the bit line BLj, as in the case of (f) in FIG. 12, a more reliable read is performed as compared with the case where the bit line BLj is not connected. It can be performed. After the bit line potential is sensed, the signal φSP becomes “L” and φRN becomes “H”, and the rewrite data is latched. At this time, the relationship among the write data, the memory cell data, and the rewrite data is as described above (Table 1).

Although the embodiment in which the present invention is applied to the NAND type EEPROM has been described above, as can be understood from the above description, the bit line BLi potential sensing method using the CMOS flip-flop circuit has two methods. There are two methods. In the embodiment of FIGS. 6-8, Qp3, Qp4, Qn17, Qn1
In contrast to the circuit threshold voltage of the clock signal synchronous inverter composed of 8 as a reference, "H" and "L" are determined, while in the embodiments of FIGS. "H" and "L" are determined as the reference. The former has the advantage that the node N2 does not enter the floating state regardless of the data latch state.
There are also disadvantages that a through current flows when sensing the bit line potential and the variation in the circuit threshold voltage is relatively large. The latter has the drawback that the node N2 is in the floating state when the node N1 is in the "L" latched state, but a through current does not flow when the bit line potential is sensed. It has the advantage that the variation in the threshold voltage is relatively small.

The present invention is a NOR type flash EEPRO.
It can also be applied to M. An example will be described below.

FIG. 14 shows a memory cell array of a flash type EEPROM. When lowering the threshold value of a memory cell (data is set to "1"), a voltage of about -12V is applied to the control gate of the memory cell and V is applied to the drain.
Apply cc. At this time, 0V is applied to the drains of the memory cells which do not want to change the threshold voltage, sharing the control gate with the selected memory cell.

A bit line control circuit including data latch and sense up shown in FIG. 15 is provided at one end of the bit line to latch the data as to whether or not the threshold value of the memory cell is changed. .

In this embodiment, after the threshold value of a memory cell is lowered, a predetermined verify voltage is applied to the control gate of the memory cell to evaluate the threshold value of the memory cell. Then, if there is a memory cell that has not reached the desired threshold value, the operation of lowering the threshold value is performed again only for that memory cell. By repeating this operation, it is confirmed that the threshold value of the memory cell is within the desired allowable range, and the verify operation is ended.

FIG. 15 shows the configuration of a bit line control circuit including a CMOS flip-flop FF which serves as a data latch and sense amplifier connected to the bit line BLi. The basic configuration is the same as that of the previous embodiment shown in FIG.

The write operation (operation of lowering the threshold value of the memory cell) and the write verify read operation of this embodiment will be described below with reference to the timing chart of FIG. First, the memory cell is erased for each word line prior to data writing. This data erase is performed by applying a high voltage Vpp (~) to the word line WLj commonly connecting the control gates of the memory cells
20V) and 0V to the bit line. As a result, electrons are injected into the floating gate of the memory cell, and the threshold value becomes Vcc or higher.

Data writing is carried out for one page at a time. First, write data is input / output lines I / O, / I / O to C
After being latched by the MOS flip-flop FF, the bit line reset signal φR becomes “L” level and the bit line B
Li becomes floating. Next, the word line WLi becomes about -12V. Then, φF is VH potential (VH is Qn2
1 is a gate voltage at which a voltage of about Vcc can be transferred, and generally VH ≥Vcc. When writing "1" (emits electrons from the floating gate), the bit line BLi is about Vcc and "0". The bit line BLi becomes 0V at the time of writing (the electrons in the floating gate are not emitted). Then, the word line is reset and the writing is completed.

Next, the verify read operation is performed. First, after the precharge signal .phi.p is "H" and /.phi.p is "L" to precharge the bit line BLi to Vcc, .phi.p is "L" and .phi.p is "H" level, and BLi
Is in a floating state. Then, the word line is set to a verify voltage of about 3.5V (however, 3.5V ≦ Vcc, generally 3.5V <Vcc), and reading is performed.
When "0" is written in the memory cell, bit line B
Li remains at "H" level. When "1" is written in the memory cell and its threshold voltage is 3.5 V or less, the potential of the bit line BLi drops to "L" level. Then, the word line becomes 0V and φRP
Becomes "H". Then, when φF becomes “H”,
Since Qn20 is turned on only in the CMOS flip-flop connected to the bit line where "0" is written,
Vss is output only to the node N1 connected to the "0" written bit line BLi. At this time, the "0" written bit line BLi is also charged from the "H" level to Vss, and then the bit line potential is changed. To be sensed. Then, φRP
Becomes "L" and the sensed data is latched.

FIG. 17 shows a bit line control circuit shown in FIG.
NOR flash EEPROM when using the above circuit
Another embodiment of the write / write verify read operation in FIG. 16 differs from the operation of FIG. 16 in that the write verify read changes φRP from 0V → Vcc → 0V in FIG. 16 and φSN is fixed to Vcc, whereas in FIG. 17, φRP is changed at the same timing as in FIG. 0V → Vcc →
When changing to 0V, φSN is changed from Vcc to 0V to Vcc at the same time.
It is about to change. In the operation timing of FIG. 17, when sensing the bit line potential, Qn17, Qn
Since p6 is in the off state, (Vcc-Vthp) potential (Vth
p is the threshold voltage of Qp3) which becomes the reference voltage for judging the "H" and "L" levels of the potential of the bit line BLi. On the other hand, in the case of the operation timing of FIG. 16, Qp3, Qp4, Qn1
The circuit threshold voltage of the clock signal synchronous inverter composed of 7 and Qn18 is "H" or "L" of the bit line potential.
This is the reference voltage for level judgment, and in this respect,
Although it is different from the operation timing of No. 7, the other points are the same. The operation timing of FIG. 16 has the same concept as that of FIG. 7 and the operation timing of FIG. 17 has the same concept as that of FIG. 10, and the on / off timings of the p channel and n channel are interchanged.

FIG. 18 shows still another embodiment of the write / write verify read operation in the NOR type flash EEPROM when the circuit of FIG. 15 is used as the bit line control circuit. The write operation in FIG. 18 is the same as in FIGS.
Since the operation timing is exactly the same as the write operation in the middle, the description thereof is omitted here, and only the write verify read operation in FIG. 18 will be described. The precharge signal φp becomes "H" and / φp becomes "L", and the bit line BLi becomes V.
After being precharged to cc, .phi.p becomes "L" and /.phi.p becomes "H" level, and BLi becomes a floating state. Then, .phi.F becomes "H" level, and the node N1 and the bit line BLi are connected. At this time, the CMOS flip-flop FF is in the data latch state, and the node N1 connected to the bit line for writing "0" is "L".
Since it is in the level state, the bit line for writing "0" drops to "L" level. On the other hand, since the node N1 connected to the bit line for writing "1" is at the "H" level, the bit line for writing "1" is kept at the "H" level. Then, .phi.F becomes "L" level to bring the bit line BLi into a floating state, and then the verify voltage of the word line becomes about 3.5 V and reading is performed. When the memory cell to which "1" is written is not sufficiently written and this memory cell is in the state of "0" data, the bit line BLi remains at "H" level. "1"
When the data is written and the threshold voltage is 3.5 V or less, the potential of the bit line BLi drops to "L". Then, the word line becomes 0 V, φRP becomes “H” and φRN becomes “L”, and then φF becomes “H”, and the bit line potential is sensed. Then, .phi.RP and .phi.RN become "L" and "H", respectively, and the sensed data is latched.

Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made. For example, NOR flash EEP
The present invention can be applied to the case where the open bit line system as shown in FIGS. 11 to 13 is used in the ROM. Also, N
In both the AND type and the NOR type, not only the method of judging the "H" level and the "L" level based on the circuit threshold voltage and the threshold voltage of the transistor as in the above embodiment, In such an open bit line structure, the voltage of the selected bit line and the other bit line (dummy bit line)
The present invention is effective even when a method of reading the data of the memory cell by comparing the voltages of the above is used.

Further, in the read operation or the verify read operation, the node N1 in FIG. 5 may be in a floating state (for example, the (*) part in FIGS. 6 and 7), so the node N1 is affected by noise. The reliability of the read data can be improved by using a method of shielding the node N1 by some method so as not to prevent it. In the read operation or verify read operation,
In order to improve the reliability of read data, the node N1 in FIG.
Φ: Vss → Vcc, φ during read operation for the purpose of shortening or eliminating the time when
RN: Vcc → Vss timing and φF: Vss → Vcc timing, φRN: Vcc → V during verify read operation
The present invention is effective even when the timing of ss and the timing of φ F: Vss → Vcc are almost the same.

The present invention is also effective when the portions surrounded by broken lines in the circuits of FIGS. 5, 11, and 15 are changed to the circuit configuration of FIG. However, FIG. 19 (a) cannot be used in the embodiments of FIGS.

Further, as described above, in the read operation or the verify read operation, the node N in FIG.
1 may be floating. In the floating state, there is a risk that the data may be inverted due to the fluctuation of the power supply voltage.
A circuit such as No. 1 can be used instead of the circuit surrounded by the broken line in FIGS. 5, 11, and 15.

FIG. 20A shows that the "H" level potential VMB of the CMOS flip-flop is between Vccmin and Vcc during reading.
When fluctuations in the range of max are allowed, a depletion type n-channel transistor having a threshold voltage of -Vccmin or more is connected between VMB and the p-channel transistor, and the gate voltage is set to 0V to obtain Vcc. Is Vcc
Even if the voltage fluctuates between min and Vccmax, the voltage transmitted to the source of the p-channel transistor on the VMB side does not fluctuate, so that more reliable reading can be performed.

FIG. 20B shows that when the node N2 is at the "H" level, the amount of the node N is the same as the fluctuation of the power supply voltage.
Change the voltage of 2. When the node N1 is in a floating state, the node N1 is in the "L" state and the node N2 is in the "H" state in the NAND type embodiment.
As shown in (b), connect a capacitor between node N2 and Vcc,
By connecting a capacitor between the node N1 and Vss, the voltage on the "H" level side can be changed by the same amount as the fluctuation amount of the power supply voltage. Furthermore, node N1 and node N2
Since the load capacitance is increased by connecting the capacitor to, the effect of reducing the risk of data inversion in the floating state can be added, and more reliable reading can be performed.

Similarly, in the NOR type embodiment, as shown in FIG.
By using (a), highly reliable reading can be performed. Also, as shown in FIG. 21B, the node N1,
If both Vcc and Vss are connected together with N2, the capacitance will be V
By adjusting the ratio between the capacitance on the cc side and the capacitance on the Vss side, changes in the nodes N1 and N2 with respect to power supply voltage fluctuations can be adjusted, and by adjusting the ratio to the optimum, more reliable reading can be performed. It will be possible. Further, as the VMB, Vcc is used during the read operation and the verify read operation in the above-mentioned embodiment, but instead, a voltage which is always kept constant without depending on Vcc is used. , 15 can be used as it is, it is possible to perform more reliable reading that prevents erroneous reading due to fluctuations in the power supply voltage.

[0072]

As described above, according to the present invention, it is possible to perform write verify control that does not perform unnecessary additional writing without increasing the circuit area, and to finally write the memory cell. It is possible to obtain an EEPROM capable of setting the threshold distribution within a small range.

[Brief description of drawings]

FIG. 1 is a NAND cell type EEPROM of an embodiment of the present invention.
The block diagram which shows the structure of M.

FIG. 2 is a plan view and an equivalent circuit diagram showing the NAND cell configuration.

FIG. 3 is a sectional view taken along line AA ′ and BB ′ of FIG.

FIG. 4 is an equivalent circuit diagram of the memory cell array.

FIG. 5 is a diagram showing a configuration of a bit line control circuit unit in the same manner.

FIG. 6 is a timing chart showing the first embodiment of the data read operation.

FIG. 7 is a first data write and verify read operation.
FIG.

FIG. 8 is a timing chart showing an embodiment of a modification of the first embodiment of the data read operation.

FIG. 9 is a timing chart showing a second embodiment of the data read operation.

FIG. 10 is a timing chart showing a second embodiment of the data read and verify read operations.

FIG. 11 is a timing diagram showing another configuration of the bit line control circuit unit.

FIG. 12 is a timing chart showing a third embodiment of the data read operation.

FIG. 13 is a timing chart showing a third embodiment of the data read and verify read operations.

FIG. 14 is a diagram showing a cell array configuration of a NOR type EEPROM.

FIG. 15 is a diagram showing a configuration of a bit line control circuit portion of a memory cell.

FIG. 16 is a timing chart showing a fourth embodiment of the data read and verify read operations.

FIG. 17 is a timing chart showing a fifth embodiment of the data read and verify read operations.

FIG. 18 is a timing chart showing a sixth embodiment of the data read and verify read operations.

FIG. 19 is a view showing a modified example of a portion surrounded by a broken line in FIGS. 5, 11 and 15.

FIG. 20 is a diagram showing another modification of the portion surrounded by the broken line in FIGS. 5, 11 and 15.

FIG. 21 is a diagram showing another modification of the portion surrounded by the broken line in FIGS. 5, 11 and 15.

FIG. 22 is a diagram showing a configuration of a conventional bit line control circuit unit.

FIG. 23 is a timing chart showing a conventional data read operation.

FIG. 24 is a timing chart showing conventional data write and verify read operations.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Bit line control circuit, 3 ... Column decoder, 4 ... Address buffer, 5 ... Row decoder, 6 ... Data input / output buffer, 7 ... Substrate buffer circuit, FF ... CMOS flip-flop (data latch and sense) up).

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical indication location H01L 29/792 H01L 29/78 371 (72) Inventor Hideko Ohira Toshiba Komukai Toshiba, Kawasaki City, Kanagawa Prefecture Town No. 1 Toshiba Corporation Research Institute

Claims (3)

[Claims] 1. A memory cell array in which a charge storage layer and a control gate are laminated on a semiconductor substrate, and a memory cell is formed in which memory cells are electrically rewritten by transfer of charges between the charge storage layer and the substrate. A data latch / sense amplifier which is provided at one end of the cell array in the bit line direction and performs a sensing operation and a write data latch operation, and a unit write time is set in a predetermined range of memory cells of the memory cell array to simultaneously write data. After that, verify control means for reading the memory cell data and rewriting if there is a memory cell that has not been sufficiently written, and the data of the read memory cell and the data latch Takes the logic of the write data latched in the sense amplifier and bit by bit according to the write state. Means for automatically setting rewrite data of the data latch / sense amplifier, wherein the data latch / sense amplifier has a first clock signal synchronous inverter having an output terminal connected to a bit line of a memory cell array, and an input The terminal and the output terminal are respectively composed of the second inverter or the second clock signal synchronous inverter connected to the output terminal and the input terminal of the first clock signal synchronous inverter, and the bit line during the write verify read operation. At least one of the transistors between the output terminal of the first clock-synchronous inverter and the ground potential is deactivated when detecting the logic level of A transistor characterized by activating at least one of the transistors between the potentials. Volatile semiconductor memory device. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cell array has a NAND cell structure in which a plurality of MOS transistors are connected in series. 3. A first clock signal synchronous inverter,
First and second n-channel MOS transistors connected in series between the bit line and a ground terminal, and first and second p-channel MOS transistors connected between the bit line and a power supply terminal The gates of the second n-channel MOS transistor and the second p-channel MOS transistor are commonly connected to the input terminal, and the first n-channel MOS transistor and the first p-channel MOS transistor are connected.
2. The nonvolatile semiconductor memory device according to claim 1, wherein the gates of the transistors are clock input terminals.