JP3448045B2 - Nonvolatile semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM), and more particularly to an EEP having a memory cell array of NAND cell structure.
Regarding ROM.

[0002]

2. Description of the Related Art A NAND cell type EEPROM capable of high integration is known as one of EEPROMs. This is to connect a plurality of memory cells in series such that their sources and drains are shared by adjacent ones and connect them to a bit line as a unit. The memory cell usually has a FETMOS structure in which a charge storage layer and a control gate are stacked. The memory cell array is integrally formed in a p-type well formed on a p-type substrate or an n-type substrate. NAN
The drain side of the D cell is connected to the bit line via the selection gate, and the source side is also connected to the source line (reference potential wiring) via the selection gate. The control gates of the memory cells are continuously arranged in the row direction to form word lines.

The operation of this NAND cell type EEPROM is as follows. The data write operation is performed in order from the memory cell farthest from the bit line. A high voltage Vpp (about 20 V) is applied to the control gate of the selected memory cell, and an intermediate potential VppM (= 1) is applied to the control gate and the select gate of the memory cell on the bit line side.
0V) is applied, and 0V is applied to the bit line according to the data.
Alternatively, an intermediate potential is applied. When 0V is applied to the bit line, the potential is transmitted to the drain of the selected memory cell, and electrons are injected from the drain to the floating gate. This shifts the threshold value of the selected memory cell in the positive direction. This state is, for example, "1". When an intermediate potential is applied to the bit line, electron injection does not occur,
Therefore, the threshold value does not change and remains negative. This state is "0".

Data erasing is performed simultaneously on all memory cells in the NAND cell. That is, all control gates and select gates are set to 0V, the bit lines and the source lines are set in a floating state, and a high voltage of 20V is applied to the p-type well and the n-type substrate. As a result, in all memory cells, electrons in the floating gate are emitted to the p-type well, and the threshold value shifts in the negative direction.

In the data read operation, the control gate of the selected memory cell is set to 0V, the control gates and the selection gates of the other memory cells are set to the power supply potential Vcc (= 5V), and whether or not a current flows in the selected memory cell. It is performed by detecting whether or not. As is clear from the above description of the operation, in the NAND cell type EEPROM, the non-selected memory cell acts as a transfer gate during the write and read operations. From this point of view, the threshold voltage of the programmed memory cell is limited. For example, the preferable range of the threshold value of a memory cell programmed with "1" is:
It becomes about 0.5 to 3.5V. Considering changes with time after data writing, variations in manufacturing parameters of memory cells, and variations in power supply potential, the threshold distribution after data writing is required to be in a smaller range.

However, it is difficult to keep the threshold value range after "1" writing within the permissible range in the conventional method in which the write potential and the write time are fixed and data is written in all the memory cells under the same condition. . For example, the characteristics of memory cells vary due to variations in the manufacturing process. Therefore, looking at the write characteristics, there are memory cells that are easy to write and memory cells that are hard to write.
In contrast to this, conventionally, it is generally performed that all memory cells are written under the same condition with an allowance in writing time so that writing is sufficiently performed in a memory cell that is difficult to write. In this case, the memory cells that are easy to write are written more than necessary, and the threshold voltage exceeds the allowable range and becomes high.

[0007]

As described above, the conventional N
In the AND cell type EEPROM, there is a problem that it is difficult to keep the memory cell within the allowable threshold range which is limited because the memory cell acts as a transfer gate when writing data.

An object of the present invention is to provide a NAND cell type EEPROM capable of reducing the threshold distribution of a memory cell in a written state.

[0009]

In order to solve the above problems and achieve the object, the present invention uses the following means.

A memory cell array composed of a large number of memory cells each having a transistor having a charge storage portion;
A first or a first memory cell connected to the memory cell array and defining (i) a control write voltage applied to each of the memory cells.
Other stores data of a second logic level to the data storage unit, the control write voltage is applied to each of said memory cells in accordance with the data stored in the data storage unit (ii), (iii) the The actual write state of the memory cell is detected, and (iv) it is detected that writing has not been completed sufficiently.
Stored in the storage unit corresponding to the stored memory cell.
Setting the data to the first logic level to facilitate writing,
Corresponds to the memory cells that are detected to have been sufficiently written.
The data stored in the storage unit according to the second logical level
Many programming systems that are set to
And control circuitry, connected to said number of programming the control circuit, and a data output control signal generator for generating a data output control signal supplied to the plurality of programming the control circuit in order to detect the data separately, the number is connected to the programming control circuit, all the data the previous
When in the serial second logic level, comprising a data detector for generating a verification end signal, the data output control signal data detection timing of the data detector is generated from the data output control signal generator and Non-volatile semiconductor memory device synchronized.

Further, a memory cell array composed of a large number of memory cells each having a transistor having a charge storage portion, and a memory cell connected to the memory cell array, for selecting the memory cell and applying a write voltage to the selected memory cell. A plurality of programming control circuits for controlling the memory cell array, combined with the plurality of programming control circuits, and (i) defining a write control voltage applied to each of the memory cells selected by the programming control circuits. Write control data of the first and second logic levels to be stored, (ii) applying the write control voltage to each of the memory cells, (iii) detecting an actual write state of the memory cell, and (iv) ) Writing that is stored in a data circuit corresponding to a memory cell in which data has been sufficiently written The logic level of the control data first
The logic level is modified from the logic level to the second logic level, and (v) the logic level of the write control data stored in the data circuit corresponding to the memory cell in which the data is not sufficiently written remains the first logic level. Keep (vi)
A plurality of data circuits that maintain the write control data stored in the data circuit that stores the second logic level at the second logic level and a plurality of data circuits that are connected to the plurality of data circuits to selectively write the write control data. An address signal generator for generating an address signal supplied to the plurality of data circuits for detection, and whether all the write control data are connected to the plurality of data circuits and are at the second logic level. And it is detected that all the write control data are at the second logic level,
A non-volatile semiconductor memory device, comprising: a data detector that generates a verify end signal, wherein the data detection timing of the data detector is synchronized with the address signal generated from the address signal generator.

According to the present invention, the write verify control is performed to shorten the data write time once,
NAND cell type EE in which reliability is improved by reducing the threshold distribution of the finally written memory cell
A PROM can be provided.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a nonvolatile semiconductor memory device according to the present invention will be described below with reference to the drawings.

First Embodiment FIG. 1 shows a NAND cell type EEPROM according to one embodiment.
Shows the configuration of. In the figure, an address buffer for address selection, row and column address decoders, and the like are omitted, and a configuration of a portion related to a write verify operation is shown. A data latch circuit 5 and a sense amplifier circuit 1 are provided for writing and reading data to and from the memory cell array 2. The sense amplifier circuit 1 and the data latch circuit 5 are connected to the data input / output buffer 4. The control gate control circuit 6 outputs a predetermined control signal to the control gate line of the memory cell array 2 in response to data write, erase, read and verify operations. During the write verify operation, the data latch circuit 5 and the sense amplifier circuit 2 perform the sensing operation and the latch of the data to be rewritten according to the column address output from the column address generating circuit 7. The data comparison circuit 3 also has a function of comparing and detecting, for each column address, a match between the write data latched by the data latch circuit 5 and the data read by the sense amplifier circuit 1 during the verify operation, and latching the result. Have. The output of the comparison circuit 3 is guided to the verification end detection circuit 9 via the output buffer 8. When the write verify operation is performed by the control circuit 6 after the write operation is performed according to the data to be written latched in the data latch circuit 5 and all the write data are within the desired threshold distribution. The verify end detection circuit 9 obtains a data write end signal. When the data write end signal is not output, the data write operation is performed again and the verify operation is repeated.

2A and 2B are a plan view and an equivalent circuit diagram of one NAND cell portion of the memory cell array, and FIGS. 3A and 3B are respectively FIG. 2A. A-
It is A'and BB 'sectional drawing. Element isolation oxide film 12
P-type silicon substrate (or p-type well) 11 surrounded by
A memory cell array composed of a plurality of NAND cells is formed in. In the description of this embodiment, focusing on one NAND cell, eight memory cells M _{1 to} M ₈ are connected in series to form one NAND cell. In each memory cell, a floating gate 14 (14 ₁ , 14 ₂ , ..., 14 ₈ ) is formed on a substrate 11 via a gate insulating film 13, and a control gate 16 is formed on the floating gate 14 via an interlayer insulating film 15.
(16 ₁ , 16 ₂ , ..., 16 ₈ ) are formed and configured. The n-type diffusion layers 19 which are the source and drain of these memory cells are connected in series so that adjacent n-type diffusion layers 19 are shared by both. The drain side of the NAND cell, respectively to the source side, the floating gate of the memory cell, the control gate selection formed simultaneously with the gate 14 _9, 16 ₉
And 14 ₁₀ and 16 ₁₀ are provided. The substrate on which the elements are formed is covered with the CVD oxide film 17, and the bit line 18 is provided on the substrate. Bit line 18 is NA
The drain side diffusion layer 19 at one end of the ND cell is contacted. Control gates 1 of NAND cells arranged in the row direction
4 are commonly arranged as control gate lines CG ₁ , CG ₂ , ..., CG ₈ . These control gate lines become word lines. Select gates 14 ₉ , 16 ₉ and 14 ₁₀ , 16
₁₀ also sequentially select gate lines SG ₁ , SG ₁ in the row direction,
It is arranged as SG ₂ .

FIG. 4 shows an equivalent circuit of a memory cell array in which such NAND cells are arranged in a matrix.

FIG. 5 shows the sense amplifier circuit 1 in FIG.
A specific configuration of the data latch circuit 5, the data comparison circuit 3, and the output buffer 8 is shown. In the data latch circuit 5, the data of the address selected by the logic of the latch signal LATCH and the address a _i is latched in the latch circuit body LA. The sense amplifier circuit 1 has a sense control signal SE
Bit line data at an address selected by the logic of NSE and address a _i is sensed and output. The output of the sense amplifier circuit 1 is compared with the corresponding data of the data latch circuit 5 by the comparison circuit 3, and the result is latched by the latch signal LATCHV and the inverted latch signal / LATCHV /.

FIG. 6 is a control gate control circuit in FIG.
The specific configuration of the portion 6 is shown. This control circuit
High potential supply that applies high potential Vpp to the select gate during writing
Circuit 21, also intermediate to non-selected control gate during writing
Intermediate potential supply circuit 22 for applying potential VppM, write verify
Verify potential V during phi operation_VERGiving verifi
Signal supply circuit 23 and erase / read control circuit 2
It is composed of four. Such a circuit is used for each control gate
It is provided for each line. The high potential supply circuit 21 is a write signal.
NAND gate G that takes the logic of WRITE and address ai₁
Type, n-channel switching controlled by
MOS transistor Q_E1And E type, p-channel scan
Itching MOS transistor Q_P1, And the output bag
E-type p-channel MOS transistor Q
_P2It is mainly composed of. MOS transistor
Q_E1And Q_P1During, MOS transistor Q_P1And high voltage
A switching MOS transistor is connected between the Vpp terminals.
N-channel MOS for protecting the transistor from high potential
Transistor Q_D1, Q_D2Is provided. these
MOS transistor Q_D1, Q_D2Is D type, n
It is a channel. Buffer stage MOS transistor Q_P1of
Similarly for upper and lower, D type, n channel MOS transistor
Star Q_D3, Q_D4Is provided. Like this in the output stage
P channel MOS transistor and D type, n channel
The high-potential Vpp is
This is because the voltage is supplied to the control gate line without a threshold drop.
Especially MOS transistor Q_D4Controlled from other circuits
When a positive potential is supplied to the gate line, the p-channel MOS transistor
Langista Q_P2Prevents the drain junction of the
It works to stop. The intermediate potential supply circuit 22 also supplies high potential.
Similarly to the power supply circuit 21, the NAND gate G_Two, By this
Controlled E-type, n-channel switching MOS
Transistor Q_E2And E type, p channel switch
MOS transistor Q_P3, The output buffer E
Type, p-channel MOS transistor Q _P4,and
D type, n channel MOS transistor Q_D5~ Q
_D8It is composed by.

The erase / read control circuit 24 uses a read signal.
NAND gates G ₃ and G ₅ that take the logic of READ and address a _i , inverted address / a _i /, inverter gate I ₂ that takes in the erase signal ERASE, and these inverter gates I ₂ and N
NOR gate G ₆ for taking the sum of AND gates G ₅ , E type for switching, n-channel MO controlled by NOR gate G ₆ and NAND gate G ₃ , respectively
S transistor Q _E3 and E type, p channel MOS transistor Q _P5 , D type for protection provided between these switching MOS transistors and control gate lines, n channel MOS transistors Q _D10 , Q _D9
It is composed by.

The verify control circuit 23 has a NAND gate G that takes the logic of the verify signal VERIFY and the address a _i.
4 and an inverter gate I ₁ for inverting its output, and a verify potential V ₁ controlled by the inverter gate I _1.
An E-type switching n-channel MOS transistor Q _E4 for supplying _VER to the control line, and a D-type n-channel MOS transistor Q _D11 for protection provided between the MOS transistor Q _E4 and the control gate line. It is composed by.

FIG. 7 shows an example of the structure of the generation circuit of the verify potential V _VER applied to the verify control circuit 23. The verify potential V _VER is the verify signal VERIFY.
When the voltage goes in, an intermediate potential set between the power supply potential Vcc and the ground potential is output and supplied to the control gate line selected by the verify potential supply circuit 23 in FIG. , E-type, n-channel MOS transistor Q _E6 connected in series between Vcc and ground potential
And _QE7 . These MOS
A voltage divider circuit of resistors R _{1 to} R ₃ is provided to apply a predetermined bias to the gates of the transistors. In principle, the power supply potential Vcc may be applied to the terminal A of these voltage dividing circuits, but this causes a through current to flow. In order to prevent this, in this embodiment, the E type, n-channel MOS transistors Q _E8 and Q _{E 9} and the E type,
A switching circuit including p-channel MOS transistors Q _P6 and Q _P7 and an inverter I ₃ is provided. That is, when the verify signal VERIFY becomes "H" level, the MO
The S transistor Q _E8 is turned on, _{QP 7} is turned on, Q _E9 is turned off, and the power supply potential Vcc is supplied to the terminal A of the voltage dividing circuit. Accordingly, M set by the voltage division ratio of the voltage dividing circuit
A verify potential V _VER of an intermediate potential corresponding to the conduction state of the OS transistors Q _E6 and Q _E7 is obtained. When the verify signal VERIFY is at “L” level, the MOS transistor Q _E9 is turned on, the terminal A of the voltage dividing circuit becomes the ground potential, and the terminal of the verify potential V _VER becomes floating. At this time, no current flows in the switching circuit because the MOS transistor Q _P7 is off.

FIG. 8 shows an example of the structure of the verify end detection circuit, which is composed of a flip-flop, a NAND gate and an inverter.

Next, the operation of the EEPROM thus configured will be described.

First, data is erased from all memory cells prior to data writing. At the time of erasing data, 0V is applied to all control lines (word lines) CG. That is, FIG.
In the control circuit shown in (1), the erase signal ERASE is input to the erase / read control circuit 24, whereby the MOS transistor Q _E3 is turned on and the control gate line CG _i is set to 0V. At this time, the select gate lines SG ₁ and SG ₂ are also set to 0V. Then, with the bit line and the source line in a floating state, a high voltage Vpp is applied to the p-type substrate (or p-type well and n-type substrate) in which the memory cell array is formed. By keeping this bias state for, for example, 10 msec, electrons are emitted from the floating gates in all the memory cells, and the threshold value becomes a negative "0" state.

In data writing, one word of data is latched by the data latch circuit 5, and the bit line potential is controlled by the data to write "0" or "1". At this time, the high potential Vpp is applied to the selected control gate line, and the intermediate potential VppM is applied to the non-selected control gate line on the bit line side. In the control circuit of FIG. 6, the write signal WRI
TE is input. That is, write signal WRITE and address a
_i , the high-potential supply circuit 21 or the intermediate-potential supply circuit 22 is turned on by the logic of the inverted address / a _i /, and Vpp is applied to the selected control gate line and Vpp is applied to the non-selected control gate line.
ppM is applied. The bit line BL is supplied with 0 V when writing data “1” and with an intermediate potential when writing data “0”. The time for holding the bias condition for data writing is sufficiently shorter than that of the conventional writing method, for example, about 1/100 of that of the conventional method, specifically about 10 μsec. In the memory cell in which "1" is written, the threshold value shifts in the positive direction, and in the memory cell in which "0" is written, the threshold value remains negative.

Next, the write verify operation is started. In this embodiment, it is checked whether the threshold value of the memory cell in which the data "1" is written has reached the desired value. This desired threshold value is determined in consideration of the data retention characteristic of the memory cell, and is, for example, about 2.5V. Such a verify operation is performed on the memory cell of one word line to which the writing has been performed. FIG. 9 is a timing chart of the verify operation. First, the sense signal SENS
E becomes "H" level, and the sense amplifier circuit 2 is enabled. At this time, the column address generation circuit 7 inputs the column address a _i , the data is output to the data output line, and the data of the data latch circuit 5 is output to the latch output line. In the cycle of this write verify operation, the verify signal VERIFY and the read signal READ are sent to the control circuit of FIG.
Enter at the same time. These and address a _i , inverted address /
A verify potential V _VER = 2.5V, which is set between the Vcc and the ground potential by the verify control circuit 23, is applied to the selected control gate line according to the logic of a _i /.
Is supplied. The output of the NAND gate G ₃ of the erase / read control circuit 24 is “L” for the other control gate lines.
The level becomes Vcc and is supplied to the control gate line. At this time, the selection gate lines SG1 and SG2 are both Vcc and the bit line B
L also becomes Vcc and the source line is set to 0V. As a result, if the selected memory cell has been subjected to "1" programming and its threshold value exceeds 2.5V,
The selected memory cell becomes non-conductive, and data "1" is read. When "1" is written but the threshold value does not reach 2.5V, the selected memory cell becomes conductive and is read as data "0".
Then, the write data and the data read by the verify operation are compared by the data comparison circuit 3, and the comparison result is latched when the latch signal LATCHV changes from the “L” level to the “H” level. That is, if the read data is "1", it is inverted by the inverter 31 in the comparison circuit 3 and enters the NAND gate 32 together with the write data "1" from the data latch circuit 4, and the inverter 33 writes the write data. Is "1", it becomes "0" and is latched by the latch circuit 34. When the write data is "1" but the write is insufficient and "0" is read, the latch circuit 34 latches the data as "1". When the write data is "0", it is latched by the latch circuit 34 in the comparison circuit 3 as "0" regardless of the read data. Table 1 collectively shows the state of the latch data in the above data comparison circuit 3.

[0027]

[Table 1]

Even one output of the data comparison circuit 3 is "1".
In this case, the verification end detection circuit 9 does not output the verification end signal. That is, in FIG. 8, when "1" appears in the output of the data comparison circuit 3 after the flip-flop is initialized by the write verify signal W-VERIFY, the output of the flip-flop is set to "0".
Until the data comparison is completed, the data comparison signal is "0",
Therefore, the verify end signal is "0" output, indicating that the verify is not completed. When the data comparison of all bit lines is completed, the data comparison end signal becomes "1". However, if the verification is not completed, the signal D _OUT V becomes "H" level, so that the data of the data comparison circuit 3 becomes data again. The new data is latched by the data latch circuit 5 via the buffer 8 and the data input line. As is clear from the above table, the "1" data is latched again only for the address for which the writing was insufficient, so that the "1" data write operation is repeated again. Then, the verify operation is performed again, and when there is no memory cell in which "1" is insufficiently written, no "1" appears in the data comparison circuit 3, and the flip-flop remains set to "0". When the data comparison end signal becomes “1”, the verification end detection circuit 9
Outputs an end signal to complete the data write operation.

Table 2 shows a summary of the potential relationship of each part in each of the above operation modes. Here, the case where the control gate line CG ₂ is selected at the time of programming and programming verification is shown.

[0030]

[Table 2]

The data read operation is the same as the conventional one.

As described above, according to this embodiment, at the time of data writing, the operation of shortening one writing time and rewriting to a memory cell in which writing is insufficient is repeated. As a result, excessive writing due to variations in the manufacturing process or the like, that is, 1 ", when writing" 1 "data surely in one writing operation as in the past,
Data thresholds are prevented from being unnecessarily high,
It is possible to reduce variations in threshold values of all memory cells in which "1" data is written. As a result,
The reliability of the NAND cell type EEPROM in which the non-selected memory cell functions as a transfer gate is improved.

FIG. 10 shows a NAND according to another embodiment of the present invention.
It is a main part configuration of a cell type EEPROM. The memory cell array 31 has the same configuration as the memory cell array 1 of the embodiment of FIG. For this memory cell array 31,
Address buffer 32 and row decoder 3 as in the conventional case
3, column decoder 34, data input / output buffer 35,
A substrate potential control circuit 36 and the like are provided. The control gate control circuit 37 outputs a predetermined control signal to the control gate line according to each operation of data writing, erasing and verifying, and its configuration is the same as that of the control gate control circuit 6 of FIG.

The difference from the previous embodiment is that a first bit line control circuit 38 and a second bit line control circuit 39 each including a sense amplifier and a data latch are provided above and below the memory cell array 31, that is, at both ends in the bit line direction. It is provided. At the time of write verify, the first bit line control circuit 38 performs a sensing operation for all bit lines and latches data to be rewritten regardless of the column address. Similarly, the second bit line control circuit 39 also performs a sensing operation and latches data to be rewritten to all bit lines regardless of the column address at the time of write verify. The relationship between these two bit line control circuits 38 and 39 during the verify operation is as follows. After data is written in the memory cell array 31 by the data latched by the first bit line control circuit 38, the second bit line control circuit 39 operates as a sense amplifier and the sensed data is directly used as the rewrite data. To latch as. Next, the data latched by the second bit line control circuit 39 is used to write to the memory cell array 31. Then, this time, the first bit line control circuit 38 operates as a sense amplifier to latch the sensed data as it is as rewriting data. Such a verify write operation is repeated.

First and second bit line control circuits 38 and 39
A specific configuration of the part is shown in FIG. First bit line system
The control circuit 38 functions as a sense amplifier and a data latch, and
Type, p-channel MOS transistor Q_P8, Q
_P9And E-type, n-channel MOS transistor
Q_E15, Q_E16CMOS flip configured by
Have a flop. This CMOS flip-flop
The source has a D-tie with its source and drain commonly grounded.
N-channel MOS transistor Q_D12, Q
_D13Are provided as capacitors. These keys
The capacitor transfers the data on the bit line
It is for storing in form. E type, n channel M
OS transistor Q_E10, Q_E11By address
ON / OFF depending on the column selection signal CSLi selected
Between the I / O line and this sense amplifier and data latch
Is for controlling the transfer of data. E Thailand
N-channel MOS transistor Q_E12, Q
_E13, Q_E14Is a CMOS flip-flop reset
The source is connected to (1/2) Vcc in common.
MOS transistor Q_E12, Q_E13Pretended by
Reset the flip-flop node to (1/2) Vcc
Have a function. E type, n channel MOS transistor
Star Q_E17Is the node of the CMOS flip-flop
With a transfer gate that turns the bit line connection on and off
is there. E-type, n-channel MOS transistor Q
_E18, Q_E19Is the CMO during the write verify operation.
Depending on the data contents of the S flip-flop, the bit line is charged.
It constitutes a circuit for supplying loads. D type, n channel
MOS transistor Q_D14And E type, p channel
MOS transistor Q_P10When reading data
This is a circuit that precharges the bit line.
Transistor Q_D14Is applied to the bit line when writing data
High potential VppM (~ 10V) obtained is MOS transistor
Q_P10It is provided so as not to be applied to. E-ta
Ip, n-channel MOS transistor Q_E20And D
Ip, n-channel MOS transistor Q_D15Is the de
High potential Vpp (up to 20) applied to the bit line when erasing data
V) is transferred to the first bit line control circuit 38.
It works to prevent it. These MOS transistors Q
_E20And Q_D15Connecting in series increases the withstand voltage
This is because

The configuration of the second bit line control circuit 39 is also basic.
Is similar to the first control circuit 38, and Q_E30, Q
_E31Is Q_E12, Q_E13To Q_E29Is Q
_E14To Q_{P 11}, Q_P12Is Q_P8, Q_P9To Q
_E27, Q_E28Is Q_E15, Q_E16To Q_D17，
Q_D18Is Q_D12, Q_D13To Q_E26Is Q_E17
To Q _E24Is Q_E18To Q_E22Is Q_E20And Q
_D16Is Q_D15, Respectively. Q_E23
Is an E type, n channel for resetting the bit line
It is a MOS transistor.

These first and second bit line control circuits 3
The memory cell array 31 is arranged between the memory cells 8 and 39 as shown in FIG.
L is, E type in the middle of the memory cell array, the n-channel MOS transistors _{QE 21,} BL1 and BL2
Is divided into The ratio of the lengths of the bit lines BL1 and BL2 divided here is, for example, BL1: BL2 = 3: 2. This division ratio determines the bit line precharge potential at the time of reading. When Vcc = 5V, the precharge potential becomes 3V.

Next, the operation of the EEPROM thus configured will be described.

First, data is erased from all memory cells prior to data writing. At the time of erasing data, 0V is applied to all control lines (word lines) CG. That is, FIG.
In the control circuit shown in (1), the erase / read control circuit 24 receives the erase signal ERASE, whereby the MOS transistor Q _E3 is turned on and the control gate line CGi is set to 0V. At this time, the select gate lines SG ₁ and SG ₂ are also set to 0V. Then, with the bit line and the source line in a floating state, a high voltage Vpp is applied to the p-type substrate (or p-type well and n-type substrate) in which the memory cell array is formed. At this time, since the bit line is floating and the high potential Vpp is applied, the inversion control signal / E shown in FIG.
RPH / becomes 0V, and the high potential Vpp is prevented from being transferred to the first and second bit line control circuits 38 and 39. By keeping this bias state for, for example, 10 msec, electrons are emitted from the floating gates in all the memory cells, and the threshold value becomes a negative "0" state.

In data writing, first, one word of data is latched by the sense amplifier / data latch in the first bit line control circuit 38. That is, the input data is transferred from the data input / output buffer to the input / output line, the column selection signal CSLi is selected by the address and becomes "H" level, and is latched by the CMOS flip-flop in the first bit line control circuit 38. It In FIG. 11, the signals φPD and φWD are Vcc until the data is latched. After that, φPD, φWD, FFSD, / ERPH / (inversion signal),
By setting φBE to the high potential VppM, 0 V is applied to the bit line when the data is "1" and VppM is applied when the data is "0".

At this time, a high potential V is applied to the selected control gate line.
pp, middle to non-selected control gate line on the bit line side
The inter-potential VppM is applied. Write in the control circuit of FIG.
The signal WRITE is input. That is, write signal WRITE and add
Reply a_i, Reverse address / a _iHigh potential by the logic of /
The supply circuit 21 or the intermediate potential supply circuit 22 is turned on.
To the selected control gate line, Vpp, unselected control gate
VppM is applied to the line. Bias for writing this data
The time to hold the condition is sufficient compared to the conventional writing method.
Short, for example, about 1/100 of the conventional one, specifically 1
It is about 0 μsec. In the memory cell where "1" is written
Memory where the threshold value shifts in the positive direction and "0" is written
The threshold remains negative in the cell.

Next, the write verify operation is started. In this embodiment, it is checked whether the threshold value of the memory cell in which the data "1" is written has reached the desired value. This desired threshold value is determined in consideration of the data retention characteristic of the memory cell, and is, for example, about 2.5V. Such a verify operation is performed on the memory cell of one word line to which the writing has been performed.

FIG. 12 specifically shows the timing of the write and verify operations in this embodiment. The operation will be described in more detail using this. First, data is sent from the input / output buffer to the data input / output line I / O and the inverted data output line / I / O /. I / O is "H" level for "1" data and I / O for "0" data
O is at "L" level. When the column selection signal CSLi selected by the address becomes "H" level, the data is latched in the CMOS flip-flop of the first bit line control circuit 38. When the data for one word is latched, RESET goes to "L" level and the bit line becomes floating. Then, when the signal PVD goes to "H" level, the bit line is Vcc-V only when the data is "0".
Precharged to th. After that, FFSD is set to the “H” level, and when the data is “0”, the bit line is set to Vcc-Vth,
In the case of "1" data, the bit line is set to 0V. afterwards,
“0” with φWD, φPD, FFSD, φBE as VppM
The bit line is set to VppM-Vth for data, and the bit line is set to 0V for "1" data. The word line is set to the desired value as described above, and the writing is completed.

When writing is completed, signals φWD, φPD, φ
BE becomes Vcc and FFSD becomes 0V. In addition, reset signal RESET
Becomes "H" level, and the bit line is reset to 0V.

Then, the verify operation is started. First, the signal .phi.BE becomes "L" level and the bit line BL2 becomes floating. And the signal PRE goes to "H" level,
Bit line BL1 is charged to Vcc. Then the signals PRE and RE
SET goes to "L" level, .phi.BE goes to "H" level, and bit lines BL1 and BL2 are (3/5) Vcc (.about.3).
V) becomes floating. At the same time that the signals PRE and RESET are set to the “L” level, the signals φnu and φpu are changed to (1 /
2) When Vcc is set and then the signal φEU is set to "H" level, the potentials of the nodes N3 and N4 of the CMOS flip-flop in the second bit line control circuit 39 become (1/2) Vcc. Then, the signal φEU is set to the “L” level and FFSU is set to the “H” level. At this time, the word line becomes the desired potential as described above, the selected control gate becomes V _VER , and if the threshold voltage of the memory cell is lower than this, the potential of the bit line decreases. That is, if the threshold value of the memory cell is lower than V _VER after writing “1” data, in other words, if the writing is insufficient, the potential of the bit line falls below (½) Vcc, and "1" is written by the rewriting operation. Also, after writing "0" data, the potential of the bit line naturally drops. In this case, since "1" is written by mistake at the time of rewriting, the signal PVD is set to "H" level after the word line is set to 0V.
The bit line is recharged only when "0" data is latched by the second bit line control circuit 39. The bit line at this time is ( _1/1) only when the threshold value of the memory cell is lower than V _VER after writing “1” data.
2) It is designed to be lower than Vcc. At this time, it is determined whether the node N3 is higher or lower than (1/2) Vcc, and the node N4 is (1/2) Vcc. And signal PV
D is set to "L" level and signal FFSU is set to "L" level. This brings the nodes N3 and N4 into a floating state. In this state, if the signal φnu is set to 0 V and the signal φpu is set to Vcc, the magnitude of the potential difference between the nodes N3 and N4 is sensed and the data is latched as it is. The latched data becomes rewrite data.

Since the first bit line control circuit 38 and the second bit line control circuit 39 are basically similar circuits, they operate similarly. That is, the rewriting is performed by the second bit line control circuit 39, and the verify reading is performed by the first bit line control circuit 38. The above operation is repeated, for example, 128 times, and the verify operation ends.

FIG. 13 is a timing chart of the data read operation. When an address is input, the signal .phi.BE first becomes "L" level, and the bit line BL2 on the second bit line control circuit 39 side becomes floating. Then, the signal PRE becomes "H" level and the bit line BL1 is precharged to Vcc. And the signals PRE and RESET are "L" level,
φPD and φnD become (1/2) Vcc, and then the signal φBE becomes "H" level, and the bit lines BL1 and BL2 are set to (3
/ 5) Precharged to Vcc. Further, the signal .phi.ED goes to "H" level, and the nodes N1 and N2 on the side of the first bit line control circuit 28 become (1/2) Vcc. continue,
The signal φED goes to "L" level. When the signal FFSD becomes "H" level and the word line is set to the potential for reading as described above, the potential of the bit line is lowered when the cell data is "0", and the potential is set when the cell data is "1". The bit line potential does not change. This bit line potential is at node N1
, The signal FFSD is "L" level, φPD is Vcc, φ
When nD becomes 0V, the first bit line control circuit 3
Sensed by 8 CMOS flip-flops. Then, the signal RESET becomes "H" level and the bit line is reset. Then, the column selection signal CSLi selected by the address becomes "H" level, the data is transferred to the data input / output line I / O and the inverted data input / output line / I / O /, and is output from the input / output buffer 35. .

Table 3 shows a summary of the potential relationship of each part in each of the above operation modes. Here, the case where the control gate line CG ₂ is selected at the time of programming and programming verification is shown.

[0049]

[Table 3]

In the embodiment, the threshold evaluation criterion in the verify operation is 2.5V, but this can be set to another appropriate value in relation to the allowable threshold distribution. The same applies to the write time for one time. For example, in order to make the final threshold distribution smaller,
It suffices to shorten the write time once and repeat the write / verify operation in small steps. Further, in the embodiment, a NAND cell type EEPR using tunnel injection is used.
Although the OM has been described, the NAND cell type E can be used even if another method such as hot electron injection is used.
The present invention is effective if it is an EPROM.

Others The present invention can be variously modified and implemented without departing from the spirit thereof.

[0052]

According to the present invention, after writing data, the write verify control circuit applies a predetermined verify potential (for example, set between the power supply potential and the ground potential) to the control gate of the memory cell to make the memory. Evaluate the threshold voltage of the cell. Then, if there is a memory cell that has not reached the desired threshold value, a write operation is added. After that, the threshold value is evaluated again. This operation is repeated, and when it is confirmed that the threshold values of all the memory cells are within the desired allowable range, the write operation is ended.

As described above, according to the present invention, the data write time for one time is shortened and the data write is repeated in small steps while checking the progress of the data write.
The threshold distribution of the memory cell array in which the data writing is finally completed can be made small.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an EEPROM according to an embodiment of the present invention.

FIG. 2A is one NAN of the memory cell array.
A plan view of the D cell, (b) is an equivalent circuit diagram of one NAND cell in the memory cell array.

3A is a sectional view taken along the line AA ′ of FIG. 2A, and FIG.
2B is a sectional view taken along the line BB ′ of FIG.

FIG. 4 is an equivalent circuit diagram of a memory cell array.

FIG. 5 is a diagram specifically showing a configuration of a main part of FIG.

FIG. 6 is a diagram specifically showing a configuration of a main part of FIG.

FIG. 7 is a diagram showing a verify potential generation circuit.

FIG. 8 is a diagram showing a configuration example of a verify end detection circuit.

FIG. 9 is a timing chart for explaining a verify operation.

FIG. 10 is a NAND cell type EEPROM according to another embodiment.
The figure which shows the principal part structure of.

FIG. 11 is a diagram showing a specific configuration example of a bit line control circuit according to another embodiment.

FIG. 12 is a timing chart for explaining write and verify operations.

FIG. 13 is a timing chart for explaining a read operation.

[Explanation of symbols]

1 ... Sense amplifier circuit 2 ... Memory cell array 3 ... Data comparison circuit 4 ... I / O buffer 5 ... Data latch circuit 6 ... Control gate control circuit 7. Column address generation circuit 8 ... Verify end detection circuit 31 ... Memory cell array 32 ... Address buffer 33 ... Row decoder 34 ... Column decoder 35 ... Data input / output buffer 36 ... Substrate potential control circuit 37 ... Control gate control circuit 38 ... First bit line control circuit 39 ... Second bit line control circuit

─────────────────────────────────────────────────── --- Continuation of the front page (72) Inventor Neo Ito 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Toshiba Research Institute Co., Ltd. (72) Inventor Masaki Tomomi Komukai-shiba, Kawasaki-shi, Kanagawa No. 1 in Toshiba Research Institute Co., Ltd. (72) Inventor Fujio Masuoka Komukai Toshiba-cho, Komukai-ku, Kawasaki-shi, Kanagawa No. 1 within Toshiba Research Institute Co., Ltd. (56) Reference JP-A-3-286497 (JP, A) Kaihei 4-82091 (JP, A) JP 2-308500 (JP, A) JP 1-144297 (JP, A) JP 1-263997 (JP, A) JP 61-294565 ( JP, A) TOMOHARU TANAKA, A 4-Mbit NAND-EEPROM M with Tight Progmmed Vt Distributio. , Dig Tech Pap 1990 Symp VLSI circu its, IEEE, 1990 years, 105-106 (58) investigated the field (Int.Cl. ^7, DB name) G11C 16/06

Claims (8)

(57) [Claims] 1. A memory cell array comprising a plurality of memory cells each having a transistor having a charge storage portion, and (i) defining a control write voltage applied to each of the memory cells. First to do
Other stores data of a second logic level to the data storage unit, the control write voltage is applied to each of said memory cells in accordance with the data stored in the data storage unit (ii), (iii) the The actual write state of the memory cell is detected, and (iv) it is detected that writing has not been completed sufficiently.
Stored in the storage unit corresponding to the stored memory cell.
Setting the data to the first logic level to facilitate writing,
Corresponds to the memory cells that are detected to have been sufficiently written.
The data stored in the storage unit according to the second logical level
Many programming systems that are set to
And control circuitry, coupled to the plurality of programming the control circuit, for generating a data output control signal supplied to the plurality of programming the control circuit in order to detect the data individually de
And over data output control signal generator, coupled to said plurality of programming the control circuit, the total
If the data of Te is in the second logic level, comprising a data detector for generating a verification end signal, the data detection timing of the data detector is the data
A non-volatile semiconductor memory device synchronized with the data output control signal generated from an output control signal generator. 2. The memory cell of the control write voltage
The voltage applied to each and the actual write state of the memory cell
The nonvolatile semiconductor memory device according to claim 1 , wherein the detection is performed until the data detector generates the verify end signal. 3. The data stored in the data storage unit is set to the initial data at the initial stage, and the initial data stored in the data storage unit is the actual data of the memory cell.
The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is modified according to the write state of the memory. 4. The nonvolatile semiconductor memory device according to claim 3, wherein the initial data is supplied through at least one input line. 5. A memory cell array composed of a large number of memory cells each having a transistor having a charge storage section, selected memory cells connected to the memory cell array, and applying a write voltage to the selected memory cells. A plurality of programming control circuits for controlling the memory cell array, combined with the plurality of programming control circuits, and (i) defining a write control voltage applied to each of the memory cells selected by the programming control circuits. Write control data of the first and second logic levels to be stored, (ii) applying the write control voltage to each of the memory cells, (iii) detecting an actual write state of the memory cell, and (iv) ) A write control is stored in a data circuit corresponding to a memory cell in which data has been sufficiently written. The logic level of the data is modified from the first logic level to the second logic level, and (v) the logic level of the write control data stored in the data circuit corresponding to the memory cell in which the data is not sufficiently written. And (vi) a number of data circuits that maintain write control data stored in a data circuit that stores the second logic level at the second logic level, and An address signal generator connected to a data circuit for generating an address signal supplied to the plurality of data circuits for selectively detecting the write control data; It is determined whether the write control data is at the second logic level, and it is detected that all the write control data are at the second logic level. A non-volatile semiconductor memory device comprising a data detector that generates a verify end signal when issued, and the data detection timing of the data detector is synchronized with the address signal generated from the address signal generator. 6. The write control to each of the memory cells.
Control voltage and the actual write state of the memory cell
Corresponds to sensing and memory cells that have been fully written with data.
The stored write control data in the data circuit
From the first logic level to the second logic level
The nonvolatile semiconductor memory device according to claim 5, wherein the correction to the level is performed until the data detector generates the verify end signal. 7. The nonvolatile semiconductor memory device according to claim 5, wherein the write control data stored in said data circuit is set to initial data at the initial stage. 8. The nonvolatile semiconductor memory device according to claim 7, wherein the initial data is supplied through at least one input line.