JP2002367380A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory in which the number of times of verifying is less, a time of a write-in cycle including verifying or an erasure cycle is short, and power consumption is less. SOLUTION: In a memory cell array MCA, a plurality of dielectric films comprising a discrete level for storing information as quantity of captured electric charges have a plurality of memory cells laminated between a semiconductor in which a channel is formed and a control electrode. A column control circuit CC accesses to a memory cell of which the number is less than the number of memory cells in a write-in unit (e.g. memory cell connected to one word line) with which write-in is performed simultaneously, verification and read-out are performed, depending on the result, it is decided whether write-in (or erasure) is performed correctly in a corresponding write-in unit or not. A memory cell performing this verification/read-out may be provided separately, or a memory cell of one part of the memory cell array MCA can be used.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device having discrete levels in a plurality of dielectric films as means for storing information as a trapped charge amount.
Specifically, the present invention relates to a nonvolatile semiconductor memory device in which the number of times of verification reading after writing or erasing is reduced.

[0002]

2. Description of the Related Art As a typical element structure of a nonvolatile memory (flash EEPROM) which can be electrically programmed and erased at once, a dielectric film between a semiconductor substrate on which a channel is formed and a control gate electrode is formed. There is an FG type in which a single conductive layer is embedded so as to be in an electrically floating state.

FIG. 11 is a sectional view showing a basic structure of an FG type memory transistor. A bottom dielectric film BTM made of silicon dioxide is formed on a p-type semiconductor on which a channel is formed, for example, a p-type semiconductor substrate SUB, and a floating gate FG made of polycrystalline silicon is formed thereon. ONO on the floating gate FG
(Oxide-Nitride-Oxide) Inter-gate dielectric film I
NT is formed, and a control gate CG made of polycrystalline silicon is formed thereon. Source / drain regions S / D made of an n-type semiconductor are formed on the surface of the semiconductor substrate SUB on both sides of these laminated films.

In the FG type flash memory, charges are injected into the floating gate FG from the entire surface of the channel or from the source / drain impurity regions S / D on both sides of the channel by using FN tunneling, and conversely, charges in the floating gate FG are charged. The basic operation is to pull out to the substrate side. The threshold voltage of the memory transistor changes depending on the presence or absence of the charge and the difference in the charge amount. For example, when writing is performed by electron injection, the threshold voltage of the n-channel memory transistor rises from the erased state “1” and changes to the written state “0” by the electron injection. At the time of erasing, the threshold voltage is lowered by extracting electrons from the floating gate FG, and the writing state is returned from “0” to the erasing state “1”. At the time of reading, by turning on or off the memory transistor according to the difference in the threshold voltage, the stored data is converted to a bit line potential difference and output to the outside.

In each write or erase operation cycle of the FG type flash memory, a write verify or erase verify is performed as a read step for checking whether or not the threshold voltage has changed within a desired range.

[0006] These verifications are usually performed for all bits that have been written or erased. Hereinafter, a write verify operation will be described with reference to FIG. FIG. 1 shows a 4M bit in which a memory cell of 2048 bits is connected to one word line and about 2 k word lines exist.
The memory cell array MCA and a part of its peripheral circuits are shown. This peripheral circuit is configured on the assumption that the number of I / O pins is eight. That is, the memory cell array M
Using (256 × 2k) bits of CA as one unit, a column decoder C-DEC, one sense amplifier SA, and a 256-bit data holding circuit (data latch) not shown are attached. In FIG. 1, the memory cell array M
(256 × 2k) bits of CA are transferred to I / O0, I / O
1, I / O2, I / O3, I / O4, I / O5, I / O
6, I / O7.

The write operation is performed collectively on 2048-bit memory cells connected to one word line. Specifically, first, write data is stored in a data latch connected to each bit line. At this time, as many data as the number of bits to be written are stored. That is, here, about 2 kbits of data is stored in the data latch. Next, the bit line potential is determined based on the data stored in the data latch. For example, 4V is applied to a bit line connected to a cell into which "1" is to be written,
0V is applied to the bit line connected to the cell where "0" is to be written. Further, the row decoder R-DEC selects a word line and raises the potential to a writing potential. As a result, data "1" or "0" is written to each memory cell.

[0008] A write verify for confirming whether or not the write has been properly performed is executed. Specifically, the column decoder C-DEC selects one of the 256 bit lines, sets the voltage between the source and the drain to 1.5 V for the memory cell connected to the bit line, and sets the gate ( (Word line) voltage is 2V. As a result, the data stored in the memory cell is converted into a potential difference between the bit lines and read, and based on the result, it is determined whether or not the writing to the memory cell has been properly performed. If it is determined that the proper writing has been completed based on the result of this verification,
The verification result is stored in the data latch connected to the read bit line.

[0009]

In this conventional nonvolatile memory device, write verification (and data storage) is repeated while changing the bit line selected from among the 256 bit lines by the column decoder C-DEC. In other words, in order to execute the write verify for all about 2 k bits connected to one page, the verify and data storage operations are repeated at least 256 times.

Here, if it is determined that the proper writing has not been completed for all the verified bits, a voltage is again applied to the bit line in accordance with the information of the data latch, and writing is performed. Verify is performed, and when writing is determined to be appropriate, data is stored in a data latch. Therefore, assuming that the number of write operations performed on one page is N, the number of verify operations is 256N per page.

As described above, in the above-described conventional nonvolatile memory device, the number of times of verification is large. 25 per write
The reason why the verification is required six times is that the convergence of the threshold voltage of the FG type memory cell is poor. In the FG type memory cell, it is difficult to keep all cells within an appropriate threshold voltage range by one writing. So, for example,
It is necessary to finely set the application time of the program pulse applied to the word line, and make the number of times of application of the program pulse different between cells while verifying each writing.

For each verification, it is necessary to change the word line voltage and the bit line voltage from the voltage at the time of writing to the voltage at the time of verification. This causes a longer write cycle time including verification of the FG type nonvolatile memory device and an increase in power consumption.

An object of the present invention is to provide a nonvolatile semiconductor memory device in which the number of times of verification is small, the time of a write cycle or erase cycle including verification is short, and power consumption is low.

[0014]

In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention comprises a plurality of dielectric films each including a discrete level for storing information as a trapped charge amount. Access and verify reading by accessing a memory cell array having a plurality of memory cells stacked between a semiconductor in which a channel is formed and a control electrode, and a memory cell less than the number of memory cells in a writing unit for writing at a time. And a circuit for determining whether or not the writing (or erasing) has been correctly performed in the corresponding writing unit based on the result. Specifically, for example,
In addition to the memory cell array, the memory circuit includes a reference memory cell array which is a set of reference memory cells provided in a predetermined number for each write unit, and the circuit accesses the reference memory cells in the reference memory cell array and performs verification reading. . Alternatively, the circuit selects a predetermined number of representative memory cells for each write unit in the memory cell array according to a determined rule, accesses the selected representative memory cells, and performs verification reading.

In the nonvolatile semiconductor memory device having such a configuration, since the means for storing information as the amount of trapped charges is a discrete level, the convergence of the threshold voltage is extremely high as compared with the FG type. Therefore, as described above, the reference memory cell in the reference memory cell array provided separately from the memory cell array, or the representative memory cell in the memory cell array, is smaller than the number of memory cells in the write unit in which writing is performed at a time in the memory cell array. The number of times of verification reading (verification) is performed. Therefore, the number of times of verification is smaller than that of the conventional FG type nonvolatile semiconductor memory device.

[0016]

FIG. 1 is a block diagram showing a main configuration of a nonvolatile memory device according to an embodiment of the present invention. This non-volatile memory device includes a 4-Mbit memory cell array MCA, a row control circuit including a row decoder R-DEC, a column control circuit CC, an address control circuit including a logic controller LC, a power supply circuit (not shown), and the like.

In the memory cell array MCA, 2048-bit memory cells are connected to one word line, there are about 2 k word lines, and the memory capacity is 4 Mbit. Each memory cell is composed of, for example, one memory transistor. There are various types of connection methods such as bit lines and word lines between memory transistors.
It is classified into ND type and the like. A configuration example of the memory cell will be described later.

The row decoder R-DEC receives an X address, selects and activates one or more 2k word lines based on the X address.

The column control circuit CC has eight I / O pins.
It is configured assuming the case of a book. That is, using (256 × 2 k) bits of the memory cell array MCA as one unit, a column decoder C-DEC, one sense amplifier SA, and a data holding circuit (data latch) for 256 bits (not shown) are attached. In response, FIG.
Then, (256 × 2k) bi of the memory cell array MCA
t from the left, I / O0, I / O1, I / O2,
I / O3, I / O4, I / O5, I / O6, and I / O7. Each column decoder C-DEC inputs a Y address, selects one of about 256 bit lines based on the Y address, and applies a predetermined voltage. This voltage at the time of writing is determined according to the write data stored in a data latch (not shown) in the column control circuit CC. At the time of erasing and reading, a predetermined voltage is predetermined. The sense amplifier S / A is 256b
It is provided for each column decoder C-DEC
Are appropriately connected to the selected bit line, and amplify the bit line potential difference with respect to the selected memory cell. The amplified data is
The data is stored in the data latch, and is output as read data via the data buffer D-BUF.

The nonvolatile memory device according to the present embodiment
The aforementioned 4-Mbit memory cell array MC shown in FIG.
In addition to A, a reference memory cell array RMCA is provided. FIG. 2 shows this reference memory cell array RMCA as a (256 × 2k) bit portion I / Ox of the memory cell array MCA.
It is a block diagram shown with. Memory cell array MC
There is no limitation on the connection method of A, but here, an isolated source line NOR type is adopted. That is, among the memory transistors constituting the memory cells MC arranged in a matrix, the sources of the memory transistors in the same column are connected to the source line S.
, And the drains of the memory transistors in the same column are connected to the bit lines BL1, BL2,. The gates of the memory transistors in the same row are connected to word lines WL1, WL2,.

On the other hand, the reference memory cell array R
The MCA includes one reference memory cell RMC in one row. Each reference memory cell RMC is connected to a reference bit line RBL and a reference source line RSL. Each gate of the reference memory cell RMC is connected to the memory cell M
Are connected to any of the common word lines WL1, WL2,.

The reference memory cell RMC and the memory cell M
C has the same element structure and is formed simultaneously. The reference memory cell RMC is preferably formed in a region continuous with the corresponding memory cell array portion I / Ox in order to minimize the difference in threshold voltage depending on the position in the chip.

The reference memory cell RMC and the memory cell M
FIG. 3 is a schematic sectional view showing the basic structure of the MONOS type memory transistor constituting C. A bottom dielectric film BTM is formed on a p-type semiconductor on which a channel is formed, for example, a p-type semiconductor substrate, a p-type well or a p-type SOI (Silicon On Insulator) layer (hereinafter simply referred to as a substrate SUB). . The bottom dielectric film BTM is made of, for example, silicon dioxide, silicon oxynitride, silicon nitride with few traps, or a laminate thereof. The charge storage film CHS is formed on the bottom dielectric film BTM. Charge storage film CHS
Is made of a dielectric material having more charge trapping levels (charge traps) than the bottom dielectric film BTM, for example, a nitride such as silicon nitride. On the charge storage film CHS, a top dielectric film TOP made of, for example, silicon dioxide is formed.
When the charge storage film CHS is made of silicon nitride or silicon oxynitride and the top dielectric film TOP is made of silicon dioxide, a deep charge trap mainly responsible for charge storage is formed near the interface between the two. These three layers constitute the gate dielectric film GD. A gate electrode G made of polycrystalline silicon and functioning as a word line is formed on the gate dielectric film GD.
E is formed.

The semiconductor substrates SUB on both sides of these laminated films
On the surface, a source / drain region S made of an n-type semiconductor
/ D is formed. The source / drain region S / D itself may be used as a source line or a bit line. Or,
The source line and the bit line may have a layered structure with the source / drain region S / D and an upper wiring layer.

Such a MONOS type memory transistor has extremely good convergence of the threshold voltage distribution.
FIG. 4 is a graph showing the relationship between programming time and threshold voltage change in a MONOS type nonvolatile memory device. This graph is obtained by plotting the average value of the threshold voltage for every memory cell MC in the 4-Mbit memory cell array MCA for each programming time. FIGS. 5A to 7C show threshold voltage distributions at each program time. In these figures, the horizontal axis represents the threshold voltage Vth, and the vertical axis represents the number of bits in the 4-Mbit memory cell array MCA. From these figures, it can be seen that the average value of the variance σ of the threshold voltage Vthw in the written state is as extremely small as about 0.038 V.
This is because the charge storage means is composed of discrete levels,
This is a major feature of the MONOS type. This feature is MNOS
It is considered the same for types.

The average value of the variance σ of the threshold voltage Vthe in the erased state was examined in the same manner. Further, the variance of the threshold voltage distribution of the FG type memory transistor described in the literature was picked up. These results are summarized in the table of FIG. As can be seen from FIG. 8, the variance σ of the threshold voltage of the MONOS type memory transistor is less than の of that of the FG type, and it was possible to demonstrate the good convergence of the threshold voltage of the MONOS type memory transistor.

In the present invention, the number of times of verification is reduced by utilizing the features of the MONOS type memory transistor.
That is, write verify or erase verify is performed on the reference memory cell RMC, and if it is determined from the result that write or erase is sufficient, the corresponding 256b
It is presumed that writing or erasing is sufficient in all the memory cells MC of the it. This is possible only with a non-volatile memory device having a discrete charge trapping level, such as a MONOS type having a uniform threshold voltage distribution, as described above, but not with a conventional FG type.

FIG. 9B is a flowchart showing a program procedure according to this embodiment. FIG. 9A is a flowchart showing a program procedure in a conventional FG type nonvolatile memory device as a comparative example. In the conventional program, after erasing before writing as necessary, first, a page program (ST0) is performed, and write verification of N bits (8 bits in the present embodiment) is repeated 256 times (ST11). ＳＴST1E).

On the other hand, in the present embodiment, the write verification is performed on the reference memory cell RMC, and the number of times is only one. Hereinafter, the program procedure shown in FIG. 9B will be described in more detail. After performing pre-write erasure as necessary, first, in step ST0,
Perform the page program. The page program is performed by a 2048-bit memory cell MC connected to one word line.
Group and a reference memory cell RMC connected to the same word line.
Are executed collectively. Specifically, each bit line B
Data latch D-LAT connected to L1, BL2,.
To store the write data. At this time, as many data as the number of bits to be written are stored. That is,
Here, data of about 2 kbits is stored in the data latch DL.
Stored in the AT. Next, the data latch D-LA
The bit line potential is determined based on the data stored in T. For example, 4 V is applied to the bit line BL and the source line SL connected to the cell to which "1" is written, and the bit line BL and the source line SL to the cell to which "0" is written.
To 0 V. At this time, “0” write data is prepared for the reference memory cell so that the threshold voltage always changes. That is, 0 V is applied to the reference bit line RBL and the reference source line RSL. Further, the row decoder R-DEC selects one of the word lines WL1, WL2,... And raises its potential to the write potential. As a result, electrons are injected from, for example, the entire surface of the memory cell MC into which the “0” data is written and the reference memory cell RMC, and their threshold voltages rise. In the memory cell MC to which "1" data is written, the threshold voltage does not rise and the erased state is maintained. As a result, data “1” or “0” is written in all the memory cells MC in the selected row, and data “0” is written in the reference memory cell RMC.

In step ST2, a write verify for confirming whether or not the write has been properly performed is executed. This write verify is performed on the reference memory cell array. Specifically, the memory cell array MC
A (256 × 2k) bit I / Ox (x = 0 to 0)
7) corresponds to I /
It is disconnected from Ox and is instead connected to the reference bit line RBL in the reference memory cell array RMCA. The switching of the bit lines is achieved by the operation of the selector STR shown in FIG.

Next, the reference bit line RBL is charged to 1.5V. This charging is performed by a bit line charging circuit in the column control circuit CC connected to the reference bit line RBL. Next, the reference bit line RBL is disconnected from the bit line charging circuit to be in a floating state. At this time, the reference bit line RBL is not discharged. That is, the reference bit line RBL is held at 1.5V. The reference source line RSL is connected to the ground simultaneously with the charging of the reference bit line RBL. Thus, the potential difference between the floating reference bit line RBL and the reference source line RSL is kept at 1.5V. Next, 2 V is applied to the word line of the selected row. Thereby, this reference memory cell RM
The stored data of C is converted into a potential difference of the reference bit line RBL and read. That is, when writing to the reference memory cell RMC is insufficient, the threshold voltage of the reference memory cell RMC is low, so that the reference memory cell is turned on by the voltage applied to the word line of the selected row, and the reference bit line RBL Are connected to the reference source line RSL, and the charge of the reference bit line RBL is discharged to the reference source line RSL through the reference memory cell RMC. As a result, the potential of the reference bit line RBL drops from 1.5V. On the other hand, when writing to the reference memory cell RMC is sufficient,
Since the threshold voltage of the reference memory cell RMC is high, the reference memory cell is not turned on by the voltage applied to the word line of the selected row, and the reference bit line RBL is not connected to the reference source line RSL but is connected to the reference bit line RSL. The potential of RBL is 1.
5V will be maintained. Thus, the storage state of reference memory cell RMC is converted to the potential of reference bit line RBL.

The potential of reference bit line RBL is amplified by a sense amplifier. For example, the differential amplifier shown in FIG. 10 is used as the sense amplifier. This differential amplifier has two pMOS transistors PI, PR and three N
It comprises MOS transistors NI, NR and NE. The reference bit line is connected to the input SAI of the sense amplifier S / A, 1 V is applied to the reference voltage input SAR, and 3.3 V is input to the sense amplifier enable input SAE. In this state, the voltage of the input SAI of the sense amplifier to which the reference bit line RBL is connected and the voltage input to the reference voltage input SAR are compared by the sense amplifier. The result of the comparison is output as the voltage of the output SAO of the sense amplifier. That is, when the voltage of the input SAI of the sense amplifier is lower than the voltage 1 V input to the reference voltage input SAR, the voltage of the output SAO of the sense amplifier increases,
When the voltage of the input SAI of the sense amplifier approaches 3.3V and is higher than the voltage 1V input to the reference voltage input SAR, the voltage of the output SAO of the sense amplifier decreases and approaches 0V. Thus, the result of the verification is reflected on the output of the sense amplifier. Then, the verification result of the reference memory cell is stored in the latch.

If all the verification results of the reference memory cells RMC for each I / O indicate that the writing has been completed, it is determined that the writing for the page has been completed. That is, as a result of the verification, if the output of the latch becomes high (Hi) when the writing is not completed, if all the outputs of the latches storing the verification results, which are the outputs of the respective sense amplifiers, are ORed ( O
R), and if the result is low (Lo),
It is determined that the writing has been completed.

Conversely, all the outputs of the latches storing the verification results, which are the outputs of the respective sense amplifiers, are ORed. If the result is Hi, the writing has not been completed. Reflect the stored latch information to the bit lines connected to each memory cell,
Write again. Thereafter, verification is performed, and when the writing is determined to be appropriate, the data is stored in the data latch. FIG. 9 shows a case where the number of times of writing is one for simplification of the drawing.

In the present embodiment, such a write procedure can reduce the write cycle time, for example, from several μs to several tens μs. In addition, the power consumption for verification can be reduced by several orders of magnitude.

In erasing, verification can be performed by using the reference memory cell RMC in the same manner as in writing. That is, when erasing is performed on a specific block, the erasing is performed on the reference memory cells in the reference memory cell array simultaneously with the erasing. The result of the erasure is converted to a bit line voltage in the same manner as the verification at the time of writing, the bit line voltage is compared with a reference voltage by a sense amplifier, and the result is stored in a latch. When the erasing of the reference memory cell RMC is insufficient, the threshold voltage of the reference memory cell RMC is high, and thus the reference memory cell is not turned on by the voltage applied to the word line of the selected row, and the reference bit line RBL is turned off. Not connected to the reference source line RSL. As a result, the voltage of the reference bit line RBL holds 1.5V. On the other hand, if the erasure of the reference memory cell RMC is sufficient,
, The reference memory cell is turned on by the voltage applied to the word line of the selected row, and the charge of the reference bit line RBL is discharged to the reference source line RSL through the reference memory cell RMC. As a result, the potential of the reference bit line RBL drops from 1.5V. Such a storage state of the reference memory cell RMC is converted to the potential of the reference bit line RBL.

The potential of the reference bit line RBL is amplified by a sense amplifier as in the case of writing, and stored in a latch connected to the output of the sense amplifier. Each I /
If all the verification results of the reference memory cell RMC for O indicate that the erasure has been completed, it is determined that the erasure for that block has been completed. That is,
As a result of the verification, if the output of the latch becomes Lo when the erasure is not completed, the logical product (AND) of all the outputs of the latches storing the verification result, which is the output of each sense amplifier, is taken. If the result is Hi, it is determined that the erasure has been completed. Conversely, all the ANDs of the outputs of the latches storing the verification results, which are the outputs of the respective sense amplifiers, are taken. If the result is Lo, the erasure has not been completed, so that To erase.

In the erase verify, as in the case of the write verify, the application of the present invention makes it possible to reduce the erase time and the power consumption during the erase.

In this embodiment, various changes can be made. First, in the present invention, the reference memory cell array RMC
A and the selector STR are not always necessary. That is, verification is performed on behalf of a predetermined number of memory cells in the memory cell array, and when it is determined that writing or erasing is sufficient in the representative memory cell, it is determined that writing or erasing of other memory cells is also sufficient. Estimation methods can be adopted. For example, in this case, it is possible to detect the end "0" write cell in the I / Ox and make it the representative memory cell.

The present invention is also applicable to a non-volatile memory device in which a sense amplifier is provided for each bit line of the memory cell array and the verify operation is performed collectively. In this case, the advantage of reducing the number of times of verification cannot be obtained. However, in the present invention, only the reference memory cell or the representative memory cell is subjected to the verify operation. At this time, the number of bit lines to be charged / discharged for verification is small. This has the advantage of requiring less.

The memory transistor is not limited to the MONOS type, but may be an MNOS type or the like. The writing and erasing methods are not limited to FN tunneling injection over the entire channel, but various writing / erasing methods such as direct tunneling injection, channel hot charge injection, source side hot charge injection, and hot charge injection caused by band-to-band tunneling. Can be applied. Since the charge storage means is discretized, binary data can be stored independently on both sides of the distribution area. It is also possible to multi-value by dividing the distribution width of the threshold voltage into three or more values. In particular, in a non-volatile memory device using discrete levels such as a MONOS type, the threshold voltage distribution width is narrow, so that there is no verification, or multi-valued operation by reducing the number of times of verification is easier than that of the FG type, and the bit cost can be easily reduced. It is.

[0042]

According to the nonvolatile semiconductor memory device of the present invention, as compared with the conventional FG type, the time of the write cycle or the erase cycle including the verify operation is shorter because the verify read operation is less. Further, the power consumed at the time of writing or erasing is reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main configuration of a nonvolatile memory device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a reference memory cell array according to the embodiment of the present invention, together with a (256 × 2k) bit portion of the memory cell array.

FIG. 3 is a schematic sectional view showing a basic structure of a MONOS type memory transistor according to an embodiment of the present invention.

FIG. 4 is a MON of 4 Mbit according to the embodiment of the present invention.
5 is a graph showing a relationship between programming time and threshold voltage change in an OS type memory cell array.

FIGS. 5A and 5B are diagrams showing threshold voltage distributions at a program time of 0 s and 2 μs in a 4 Mbit MONOS memory cell array according to an embodiment of the present invention;

FIGS. 6A, 6B and 6C show a program time of 10 μs and 100 μs, respectively, in a 4 Mbit MONOS type memory cell array according to an embodiment of the present invention;
FIG. 7 is a diagram showing threshold voltage distributions at μs and 1 ms.

FIGS. 7A, 7B, and 7C show program times of 10 ms and 100 ms, respectively, in a 4 Mbit MONOS memory cell array according to an embodiment of the present invention;
It is a figure which shows the threshold voltage distribution in ms and 1s.

FIG. 8 shows a 4 Mbit MON according to the embodiment of the present invention.
9 is a table comparing the variance of the threshold voltage between the write state and the erase state in the OS memory cell array with that of the FG memory transistor described in the literature.

FIG. 9B is a flowchart showing a program procedure according to the embodiment of the present invention. (A) is a flowchart showing a programming procedure in a conventional FG type nonvolatile memory device as a comparative example.

FIG. 10 is a circuit diagram of a differential amplifier constituting a sense amplifier.

FIG. 11 is a schematic sectional view showing a basic structure of a conventional FG type memory transistor.

[Explanation of symbols]

SUB: Substrate (semiconductor on which channel is formed), BTM
... Bottom dielectric film, CHS ... Charge storage film, TOP ... Top dielectric film, GE ... Gate electrode (control electrode), S / D ... Source / drain region, MCA ... Memory cell array, MC
... memory cell, RMCA ... reference memory cell array, RM
C: Reference memory cell, BL1, etc .... Bit line, SL1, etc.
Source line, RBL: Reference bit line, RSL: Reference source line, WL1, etc .: Word line, CC: Column control circuit (circuit for performing verification reading and determination), SA: Sense amplifier.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/792 F-term (Reference) 5B025 AA03 AA07 AB01 AB03 AC01 AD06 AD07 AE05 AE06 5F083 EP18 EP23 EP44 EP77 ER03 ER06 ER09 ER14 ER19 ER23 GA05 HA02 JA04 JA32 KA06 KA12 LA03 ZA20 ZA28 5F101 BA46 BB05 BC02 BC11 BD02 BE02 BE05 BE07 BG07 BH26

Claims (8)

[Claims] 1. A semiconductor device comprising: a plurality of dielectric films each including a discrete level for storing information as a trapped charge amount; and a plurality of memory cells stacked between a semiconductor in which a channel is formed and a control electrode. Verification read is performed by accessing the memory cell array that has been written and the memory cells less than the number of memory cells in the write unit to be written at one time, and based on the result, it is determined whether or not the write was correctly performed in the corresponding write unit Nonvolatile semiconductor memory device having a circuit that performs A reference memory cell array which is a set of reference memory cells provided in a predetermined number for each write unit, separately from the memory cell array; and wherein the circuit accesses the reference memory cells in the reference memory cell array. 2. The non-volatile semiconductor memory device according to claim 1, wherein verification reading is performed. 3. The circuit according to claim 1, wherein a predetermined number of representative memory cells are selected for each write unit in the memory cell array according to a predetermined rule, the selected representative memory cells are accessed, and verification reading is performed. Nonvolatile semiconductor memory device. 4. A sense amplifier is connected to each of N columns (N: a natural number of 2 or more) of the memory cell array, and the circuit selects one representative memory cell for every N columns in the write unit. 4. The non-volatile semiconductor memory device according to claim 3, wherein the verification read is performed by accessing the representative memory cell. 5. A memory cell comprising a plurality of dielectric films, each including a discrete level for storing information as a trapped charge amount, laminated between a semiconductor in which a channel is formed and a control electrode. Read and access the memory cell array that has been written and the number of memory cells less than the number of memory cells in the write unit to be written at a time, and verify whether or not erasure has been performed correctly in the corresponding write unit based on the result. And a non-volatile semiconductor memory device having a circuit. 6. A reference memory cell array, which is a set of reference memory cells provided in a predetermined number for each writing unit, separately from the memory cell array, wherein the circuit accesses the reference memory cells in the reference memory cell array. 6. The nonvolatile semiconductor memory device according to claim 5, wherein verification reading is performed. 7. The circuit according to claim 5, wherein a predetermined number of representative memory cells are selected for each write unit in the memory cell array according to a predetermined rule, and the selected representative memory cells are accessed to perform a verification read. Nonvolatile semiconductor memory device. 8. A sense amplifier is connected to each of N columns (N: a natural number of 2 or more) of the memory cell array, and the circuit selects one representative memory cell for every N columns in the write unit. The nonvolatile semiconductor memory device according to claim 7, wherein the representative memory cell is accessed to perform verification reading.