JPH1011990A - Non-volatile storage device having verify function - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a small-size non-volatile storage device having a verify function by altering a sensing ratio between an output of a verify cell and an output of a reference cell in a sense amplifier. SOLUTION: Non-volatile memory transistors and verify transistors having a memory cell array 11 and a verify cell column 13, in addition to associated circuit elements, are formed on a single semiconductor substrate. A reference cell 16 is also formed simultaneously, so that the same writing/erasing times are achieved with application of the same voltages for writing/erasing information. That is, a change in a threshold value appearing in the memory cell array 11 can be detected by being represented with a change in a threshold value appearing in the verify cell column 13. Accordingly, upon switching to a verify mode, a verify control circuit 18 operates in accordance wit a control signal from a control circuit 20, and an output from the reference cell 16 is amplified by a sensing ratio control circuit 17a to a predetermined level to be then input to a sense amplifier 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile memory device, and more particularly to a verifying method using a verify cell formed separately from a memory cell as a representative of a memory cell and a reference cell to which the output of the verify cell is referred. The present invention relates to a nonvolatile storage device having a function.

[0002]

2. Description of the Related Art In a nonvolatile storage device such as an EEPROM or a flash memory, an operation of writing or erasing information is performed for a certain period of time, and an operation of confirming that the writing or erasing operation has been completed is performed. The writing or erasing operation and the confirming operation are performed as a set for a certain period of time, and the confirming operation is terminated when the writing or erasing operation is completed correctly. This confirmation operation is called verification. Conventionally, this verify reads sequentially the stored contents of each memory cell in an array cell constituting a nonvolatile storage device when writing or erasing information,
This is done by comparing the result with the contents of the reference memory cell. Specifically, verification is performed by comparing the threshold value of each memory cell in the array cell with the threshold value of the reference memory cell.

However, since the number of memory cells has become enormous with the recent high integration of memories, it takes a lot of trouble and time to inspect the threshold value of each cell.

[0004] For example, US Patent No. N0.5,142,49
No. 6 discloses a technique in which a reference column is provided at an end of a cell matrix, and outputs of a reference cell and an array cell sharing a word line are verified by adjusting a sense ratio in a sense circuit. Here, since one reference cell is connected to each word line, the characteristics of the array cells sharing the word line can be inspected by verifying each reference cell.

[0005]

This U.S. Pat.
In the invention of Japanese Patent No. 5,142,496, the sense cell compares the array cell sharing the word line with the reference cell. However, the array cell selected at the time of writing must be selected again at the time of verification and compared with the reference cell. Must. For this reason, even if writing is performed in the page mode, for example, at least comparison between the selected array cell and the reference cell is necessary, and it takes time to select a specific cell, and it takes time to perform verification.

Further, since the reference cells are different for each word line, variations in the manufacture of the reference cells appear as variations in the characteristics of the reference cells, and the verification standard differs for each word line.

As described above, in the conventional nonvolatile memory device,
Verification must be performed on all selected memory cells to confirm that information has been correctly written or erased in the memory cells in the array, which requires a great deal of labor and time.

Accordingly, the present invention provides a non-volatile memory device having a verify function which can perform a write operation or an erase operation of information simply, quickly and accurately by performing a verify operation promptly and accurately. The purpose is to provide.

[0009]

A nonvolatile memory device having a verify function according to the present invention comprises a plurality of word lines arranged in a row direction and a plurality of bit lines arranged in a column direction intersecting the word lines. A plurality of non-volatile memory cells, each of which is disposed at an intersection of a line, the word line and the bit line, and a plurality of non-volatile memory cells which are commonly connected to the plurality of non-volatile memory cells at each of the word lines. At least one verify cell having substantially the same write / erase characteristics, a reference cell for generating a reference signal, an output of a verify cell connected to a word line selected at the time of write / erase, and a reference signal from the reference cell. Are detected with different predetermined sense sensitivities.

With the above configuration, the verification of the plurality of nonvolatile memory cells connected to each of the word lines is performed by verifying the write / erase characteristics which are commonly connected to these nonvolatile memory cells and which are substantially the same as the plurality of nonvolatile memory cells. Can be performed for each word line by using the verify cell having the threshold voltage and the reference cell, so that high-speed verify can be realized. This is a technical idea that can be called page mode verify. In addition, according to the above configuration, such a high-speed verification can be performed by electrically controlling the sense sensitivity of the sensing means and adjusting the threshold value of the cell. And can be performed accurately. In manufacturing, the sensing means has a simple circuit configuration, and the verify cell can be formed simultaneously with a plurality of nonvolatile memory cells. Therefore, the manufacturing process can be performed almost as it is, the chip area can be reduced, and the manufacturing cost can be reduced. Can be reduced.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block circuit diagram showing the first embodiment. A memory cell array 11 includes a plurality of nonvolatile memory cell transistors M1i, M1 (i + 1),
, M2i, M2 (i + 1), ..., M3i, M3 (i +
1) are arranged in a matrix in the row and column directions. Nonvolatile memory cell transistors M1i, M
The control gates of the non-volatile memory cell transistors M2i, M2 (i + 1),... Are commonly connected to the word line WLi + 1, and the control gates of the non-volatile memory cell transistors M2i, M2 (i + 1),. The control gates of M3i, M3 (i + 1),... Are commonly connected to word line WLi + 2. These word lines WLi, WLi +
1 and WLi + 2 are connected to and driven by a word line driver, that is, the output terminal of the X decoder 10.

The nonvolatile memory cell transistors M1i,
The drains of M2i, M3i,.
i, and connected to the nonvolatile memory cell transistor M1
The drains of (i + 1), M2 (i + 1), M3 (i + 1),... Are commonly connected to the bit line BLi + 1. Each of these bit lines BLi, BLi + 1... Is turned on by a Y decoder 13 which is a bit line selection circuit.
Connected to a write circuit 6 including a sense amplifier via transistors 8ni and 8n (i + 1) that are turned off,
Furthermore, it is connected to a power supply (not shown). The sources of the nonvolatile memory cell transistors M1i, M2i, M3i... Are commonly connected to a source line SLi, and the nonvolatile memory cell transistors M1 (i + 1), M2 (i + 1),
The sources of M3 (i + 1)... Are commonly the source line SLi
Connected to +1. These source lines SLi, SL
i + 1 is commonly grounded.

The memory cell array 1 constructed as described above
1 and a redundant cell array 1 composed of redundant cells.
3 is added. Since the redundant cell array 13 is used for verifying the cell array 11 as described in detail below, it is referred to as a verify cell column 13 in the following description. The verify cell column 13 is composed of redundant cells, one for each word line WLi, WLi + 1, WLi + 2,..., That is, verify cell transistors Mv1, Mv2, Mv3,. These verify cell transistors Mv1 and Mv
, Mv3... Are respectively connected to word lines WLi, WLi + 1, WLi + 2,. Is done. Furthermore, it is connected to one input terminal of the sense amplifier 14 via the transistor 8v. Verify cell transistors Mv1, Mv
, Mv3... Are commonly grounded.

An output from the reference cell 16 is supplied to the other input terminal of the sense amplifier 14 via a level adjusting circuit 17. The level adjusting circuit 17 operates with a signal from a verify control circuit 18 in a verify mode, which will be described later, and adjusts the level of the output from the reference cell 16 to an appropriate value for comparison with the signal from the bay cell column 13. And supplies the data to the sense amplifier 14.

In this embodiment, the nonvolatile memory cell transistors M1i,... M3 (i + 1) and the verify cell transistors Mv1, Mv2, Mv constituting the memory cell array 11 and the verify cell column 13 are described.
Are formed on one semiconductor substrate together with the attached circuit elements. In particular, the nonvolatile memory cell transistors M1i,... M3 (i + 1) and the verify cell transistors Mv1, Mv2, Mv3,... Which constitute the memory cell array 11 and the verify cell column 13 have the same configuration and dimensions. Formed at the same time. Further, a reference cell 16 is formed at the same time. Therefore, the characteristics of the memory cell are the same, and if the voltage applied at the time of writing and erasing information is the same, the time required for writing and erasing becomes almost the same. From another viewpoint, a change in the threshold value appearing in the memory cell array 11 at the time of writing or erasing information can be detected by representing the change in the threshold value appearing in the verify cell column 13. In this way, the verification of writing and erasing of information in the memory cell transistor connected to each word line can be performed by one verification cell as a representative. In this embodiment, verification is performed by paying attention to this point, and details will be described below.

FIG. 2 shows that the writing of information into the nonvolatile memory cell transistors M1i,... M3 (i + 1) and verifying cell transistors Mv1, Mv2, Mv3. The graph shows a write characteristic distribution and an erase characteristic distribution (threshold distribution) when the word line voltage, the drain voltage, and the source voltage are kept constant in the case of performing N-electron injection.

In FIG. 2, a curve A shows a threshold distribution of the array cell 11 after electron injection for a predetermined time.
The threshold distribution of the verify cell is shown by a curve B located substantially at the center of the curve A. At this stage, the mode is switched to the verify mode, and the level of the output of the reference cell 16 with respect to the output of the verify cell column 13 is increased by the level adjusting circuit 17 and supplied to the sense amplifier 14 so that the sense ratio becomes larger than 1. The threshold distribution of the verify cells in the column 13 is moved from a position substantially at the center of the curve A to a position of a curve B ′ shown below the curve A. As a result, the apparent threshold distribution B ′ of the verify cell is lower than the threshold distribution A of the array cell 11. Therefore, if the output of the reference cell 16 is adjusted by the level adjusting circuit 17 so that the threshold distribution B 'can be detected, when the threshold distribution B' of the verify cell in the column 13 is detected, the output of the array cell 11 is determined. The threshold should have reached the position indicated by A. Therefore, verifying only one verify cell for each word line has verified the writing of all the array cells sharing the word line. That is, this means that the verification is performed at high speed in the page mode.

In FIG. 2, a curve C shows a threshold distribution of the array cell 11 after electron extraction for a predetermined time, and a threshold distribution of a verify cell in the column 13 is shown by a curve D located substantially at the center of the curve C. . At this stage, the mode is switched to the verify mode, and the level of the output of the reference cell 16 with respect to the output of the verify cell column 13 is reduced by the level adjusting circuit 17 and supplied to the sense amplifier 14 so that the sense ratio becomes smaller than 1. Column 13
The threshold distribution of the verify cell is shifted from the substantially center position of the curve C to the position of the curve D 'shown above the curve C. As a result, the apparent threshold distribution D 'of the verify cell is higher than the threshold distribution C of the array cell 11. Therefore, the output of the reference cell 16 is adjusted by the level adjusting circuit 17 so that the threshold distribution D 'can be detected.
If the threshold value distribution D 'of the verify cell in the column 13 is detected, the threshold value of the array cell 11 should have reached the position indicated by C. Therefore, erasure of all the array cells sharing the word line can be verified only by verifying one verify cell for each word line.

In the embodiment shown in FIG. 1, a case where one verify cell column 13 is formed for one cell array 11 has been described as an example, but a memory cell array coupled to one word line has been described. However, even when a very large number of memory cells are connected as in the case where the memory cell is composed of a plurality of sectors, it is needless to say that verification can be performed by one verify cell as a representative.

FIG. 3 is a block diagram showing a more specific embodiment of the embodiment shown in FIG. Here, parts corresponding to those in FIG. 1 are denoted by the same or similar reference numerals, and only different parts will be described. 3 differs from the circuit of FIG. 1 in that the write circuit 6 of FIG. 1 is shown as an input / output buffer 22 and a data latch circuit 23, and a sense ratio control circuit 17a is used as a level adjustment circuit 17. Point, the point at which the output of the sense amplifier 14 is supplied to another input / output buffer 21,
2 and the verify control circuit 18 operates under the control of the control circuit 20.

In FIG. 3, in the write mode, the information latched by the data latch circuit 23 from the input / output buffer 22 is decoded by the Y decoder 12a to select the bit lines BLi,... BLi + n, and the word lines scanned by the X decoder 10. Writing is performed on the selected memory cell every time.

When the mode is switched to the verify mode after a predetermined time, the verify control circuit 18 operates according to a control signal from the control circuit 20 such as a CPU, and the output of the reference cell 16 is amplified to a predetermined level by the sense ratio control circuit 17a. And supplied to one input terminal of the sense amplifier 14. The other input terminal of the sense amplifier 14 has Y
The output of the verify cell column 13 is supplied via the decoder 12a and the data latch circuit 23, and the two are compared. As described with reference to FIG. 2, when the output of the verify cell column 13 is detected at the position of the distribution curve B ′,
It can be seen that the threshold value of the cell array 11 is at the position of the distribution curve A, indicating that the verification has been performed. The case of information erasure has been described with reference to FIGS. 1 and 2 and is omitted here.

The embodiment of FIG. 4 is an improvement of the embodiment of FIG. 3, and the circuit configuration is further simplified by omitting the sense ratio control circuit 17a in FIG. In the embodiment of FIG.
The output of the verify circuit 18 supplies a control signal to the gate of the reference cell transistor 16 to directly adjust the output level of the reference cell transistor 16. Other configurations and operations are the same as those of the embodiment of FIG. 3, and the description is omitted.

In each of the above embodiments, the verification of the array cells sharing the word line can be performed only by the verification of the verification cells, so that the verification time can be greatly reduced. Further, as the verify cell column 13, a part of the redundant cell array formed and provided simultaneously in preparation for a failure of the memory cell array can be used as it is, so that it can be realized by the normal manufacturing process of the nonvolatile memory cell. Therefore, the circuit configuration can be simplified, so that the manufacturing cost and the chip size can be reduced.

In each of the embodiments described above, the configuration of the memory cell, the verify cell and the reference cell are the same, and the threshold characteristics thereof are the same. Further, the threshold characteristics of the memory cell and the verify cell are the same. The present invention can also be applied to cases where In this case, verification can be performed by changing the sense ratio of the sense amplifier according to the threshold value or by fixing the sense ratio to one. For example, in the embodiment shown in FIG. 1, the memory cells M1i to M1 (i + 1) and the verify cells Mv1 to Mv3 are formed in the EEPROM structure as shown in FIGS. 5 and 6, the memory cell M1i and the verify cell Mv are representatively shown.
1, the other cells have the same configuration. Since these memory cell M1i and verify cell Mv1 have almost the same configuration as each other, the same portions are denoted by the same reference numerals and will be described at once.

A drain region 31 and a source region 32 are formed on a p-type silicon substrate 30 as high-concentration impurity diffusion regions (n + 1) by doping n-type impurity ions. A tunnel oxide film 33 is formed on silicon substrate 30 including drain region 31 and source region 32. A floating gate 34 made of polysilicon is formed on the channel region between the drain region 31 and the source region 32 and on the tunnel oxide film 33. On the tunnel oxide film 33 other than the floating gate 34, a field oxide film 35 made of a silicon oxide film is formed.

A cap 36 made of polysilicon is formed to cover the exposed surface of the floating gate 34 and to cover the surface of the field oxide film 35 up to above the drain region 31 and the source region 32. This cap 3
On the field oxide film 6 and the field oxide film 35, an ONO film 37 as an insulating layer having a structure in which silicon oxide / silicon nitride is laminated on the surface of the field oxide film 35 including the cap 36 is formed. The ONO film 37
A control gate 38 made of polysilicon is formed thereon.

The dimensions of the cap 36 are different between the memory cell M1i and the verify cell Mv1 in FIGS. In the memory cell M1i shown in FIG. 5, the cap 36 has a length Lx1 along the direction in which the drain region 31 and the source region 32 are arranged and a length Ly1 along a direction orthogonal to the direction in which the drain region 31 and the source region 32 are arranged. And a cap area S1 represented by Lx1 × Ly1. On the other hand, in the verify cell Mv1 shown in FIG. 6, the length Lx2 along the direction in which the drain region 31 and the source region 32 are arranged, and the length along the direction orthogonal to the direction in which the drain region 31 and the source region 32 are arranged. And a cap area S2 represented by Lx2 × Ly2. Therefore, FIG.
The relationship S1> S2 exists between the areas S1 and S2 of the caps 36 of the memory cell M1i and the verify cell Mv1 in FIG.

The memory cell M having the structure as described above
1i and verify cell Mv1, verify cell M
The gate couple ratio of v1 is set smaller than the gate couple ratio of the memory cell M1i. The gate couple ratio increases as the capacitance between the channel region and the floating gate 34 and the capacitance between the floating gate 34 and the control gate 38 increase.

The memory cell M1i shown in FIGS. 5 and 6
In the verify cell Mv1, the area where the channel region and the floating gate 34 face each other is the same, so that the capacitance between the channel region and the floating gate 34 is equal. On the other hand, in the memory cell M1i and the verify cell Mv1, the areas S1 and S2 where the floating gate 34 and the control gate 38 face each other are different, and the memory cell M1i is different from the verify cell Mv1 in the floating gate 34. And the area S1 facing the control gate 38 is large. Therefore, the memory cell M1i is larger than the floating gate 3 in comparison with the verify eye cell Mv1.
4 and the control gate 38 have a large capacitance. The gate couple ratio of the memory cell M1i is larger than the gate couple ratio of the verify cell Mv1. As described above, the memory cell M1i is different from the memory cell M1i of the word line WLi to which the verify cell Mv1 is connected simply by incorporating the verify cell Mv1 having a different gate couple ratio into the semiconductor device and verifying the verify cell Mv1. M1 (i +
1) can be verified.

The other word lines WLi + 1, WLi + 2
The same applies to. It is simplest to simply form cells having different couple ratios by adjusting the area of the tunnel oxide film portion of the cell and the surface area of the floating gate.

That is, in the structure shown in FIGS. 5 and 6, if the polysilicon cap 36 indicated by oblique lines is made shorter by the verify mask on the photomask than by the array cell, the couple ratio of the verify cell is higher than that of the array cell. It is clear that the cell can be small.

As described above, writing or erasing to a memory cell is performed by Fowler-Nordheim tunnel current (hereinafter, FN current) or hot electron injection (hereinafter, HE injection). Array memory cell M
1i, a verify cell Mv1 having a smaller gate couple ratio is prepared, and characteristics of electron injection into each floating gate 34, characteristics of extracting electrons from the floating gate 34, and characteristics of electron injection of hot electrons into the floating gate 34 are measured. When examined, FIG. 7 (a),
(B) and (c).

As is apparent from FIGS. 7A, 7B and 7C, the threshold value Vth of the array cell having a higher couple ratio changes more rapidly and the predetermined time elapses regardless of the FN current or the HE injection. Later, it can be seen that the thresholds are different. By utilizing this property, each word line WLi, WLi + can be written only by verifying the writing of information into the verify cell Mv1 and the erasure from the verify cell Mv1.
1, the memory cells connected to WLi + 2,... Can be verified.

First, the program verify will be described. First, a write operation is performed. That is, the word line WLi is selected by the X decoder 10 in FIG. 1, a write selection voltage is applied to the word line WLi, and the bit lines BLi, B of the memory cell to be written are written.
Li + 1... And the selection transistor 8 connected to one of the verify cells Mv1 and the bit line BLvi
v, 8n, 8n (i + 1) are selected by the Y decoder 12, and a write voltage is applied to any one of the bit lines BLi, BLi + 1... and the bit line BLvi.

In this manner, data, for example, data "" is stored in the memory cell to be written and the verify cell Mv1.
In this write operation, a select voltage and a write voltage are applied for a predetermined time, and a threshold value in a predetermined range is given to each of the memory cell and the verify cell Mv1.

After this write operation, a verify operation is started. In the verify operation, the verify cell Mv1 of the word line WLi to which the programmed memory cell is connected is selected by the X decoder 10, and a verify voltage is applied. This verify voltage corresponds to the threshold voltage of the verify cell Mv1 programmed as described later.

Thereafter, the selection transistor 8v connected to the bit line BLvi is selected by the Y decoder 12. Therefore, the output from the programmed verify cell Mv1 is supplied to the sense amplifier 14. At the time of this verify operation, since the reference cell 16 is also turned on, the reference output from the reference cell 16 is supplied to the sense amplifier 14. In the sense amplifier 14, the reference output and the output from the verify cell 4n are compared with a sense ratio of 1.

Here, when the verify cell Mv1 is correctly programmed, for example, the level of the output from the verify cell Mv1 is higher than the level of the reference output, and the sense amplifier 14 informs that the program has been correctly performed. The output "1" meaning is output. If the verify cell Mv1 is not programmed correctly, for example, the level of the output from the verify cell Mv1 is lower than the level of the reference output, and the sense amplifier 1
4 outputs an output "0" which means that the program is not correctly performed.

As described above, the program operation and the verify operation are repeated, and when the output "1" indicating that the program has been correctly performed is output from the sense amplifier 14, the program operation ends.

The erase verify is executed as described below in substantially the same manner as the write verify. Here, the erasing operation is performed for each common source and common well. That is, an erase gate voltage is applied to the word lines WLi, WLi + 1,... And an erase well voltage or an erase voltage is applied to a common well or a common source, or an erase well voltage and an erase well voltage are applied to a common well and a common source, respectively. An erase voltage is applied.

In this manner, data in the memory cells and the verify cells are erased. In this erasing operation, a selection voltage and an erasing voltage are applied for a predetermined time, and a threshold value in a predetermined range is given to each of the memory cell and the verify cell. After this erase operation, a verify operation is started.
In the verify operation, the verify cells connected to the word lines to which the memory cells from which data has been erased are connected are sequentially selected by the X decoder 10, and a verify voltage is applied.

This verify voltage corresponds to the threshold voltage of the verify cell at the time of erasing, as described later.
When the selection transistor 8v connected to the bit line BLvi is selected by the Y decoder 12, the output from the erased verify cell is supplied to the sense amplifier 14. At the time of this verify operation, the reference output from the ON reference cell 16 is compared with the output from the verify cell by the sense amplifier 14 set to the sense ratio 1.

Here, when the verify cell has been correctly erased, for example, it means that the level of the output from the verify cell is lower than the level of the reference output, and that the sense amplifier 14 has correctly erased the data. Output
When the verify cell is not erased, for example, the level of the output from the verify cell is higher than the level of the reference output, and it is not correctly erased from the sense amplifier 14. Is output.

Thus, it is verified whether or not all the verify cells have been erased. As described above, by verifying the verify cell, the program or erase of the memory cell sharing the word line WLi with the verify cell is verified.

This is based on the following reasons. FIG. 8A shows the distribution of threshold values of a large number of cells. The horizontal axis shows the cell count corresponding to the number of cells, and the vertical axis shows the threshold voltage Vth. Graph A1
And B1 are a memory cell M1i and a verify cell M1 at a certain point when electrons are injected into the floating gate 34.
3 shows a distribution of threshold values of v1.

Graphs A2 and B2 show the distribution of the threshold values of the memory cell M1i and the verify cell Mv1 at a certain point when electrons are extracted from the floating gate 34. As is clear from the graphs A1 and B1 in FIGS. 7A and 8A, when electrons are injected into the floating gate 34, if the threshold value of the verify cell Mv1 rises to a certain value, the couple ratio is verified. In the memory cell M1i larger than the cell, the threshold change has reached a higher threshold level because the threshold change is faster than the verify cell Mv1.

Therefore, if it is determined whether or not the verify cell Mv1 conducts at the threshold value, all the other memory cells coupled to the word line will set a predetermined threshold value having a threshold value larger than the threshold value of the verify cell Mv1. This means that it is not necessary to check whether the memory cell corresponding to the verify cell Mv1 conducts at the threshold.

Also, as is apparent from the graphs A2 and B2 in FIGS. 7B and 8A, when electrons are extracted from the opening gate 34, the threshold value of the verify cell drops to a certain value. For example, in an array cell in which the couple ratio is larger than the verify cell, the threshold change has reached a lower threshold level because the threshold change is faster than in the verify cell. Therefore, if it is checked whether or not the verify cell conducts at the threshold, the other memory cells have a predetermined threshold having a threshold smaller than the threshold of the verify cell,
It is not necessary to check whether the memory cell corresponding to the verify cell conducts at the threshold.

From such a principle, the word line WLn
Is verified only by examining one verify cell for a plurality of memory cells sharing the same. Even when hot electrons are injected into the floating gate 34, the distribution is similar to that shown in the graphs A1 and B1 of FIG. 8A. Alternatively, even when erasing, many memory cells can be verified simply by verifying the verify cells.

Here, the reference cell 16 is formed as a cell of the same type as the array memory cell,
When the couple ratio of the array memory cell is made equal to the couple ratio of the array memory cell, the sense ratio adjustment of the sense amplifier 14 for adjusting the offset with the verify cell is checked by the TEG process, and the method described with reference to FIGS. Can be verified. If the reference cell 16 is also a cell of the same type as the verify cell, the adjustment becomes easy.

From the above, the following applications are possible.

(1) A bit line composed of a verify cell having a larger couple ratio than the array cell is added. This verify cell can be used for over-erasing (over-erasing) and over-program checking. That is,
As shown in FIG. 8B, the threshold distribution of the verify cell and the array cell is different from that of FIG.

That is, the relationship between the threshold value of the memory cell and the threshold value of the verify cell at a certain time when electrons are injected into the floating gate 34 is such that the threshold value of the memory cell rises to a certain value as is clear from the graphs C1 and D1.
In a verify cell having a couple ratio larger than that of a memory cell, the threshold change has reached a higher threshold level because the threshold change is faster than that of the memory cell. When the electrons are extracted from the floating gate 34, the relationship between the threshold values of the memory cell and the verify cell at a certain point in time is, as is clear from the graphs C2 and D2, when the threshold value of the memory cell falls to a certain value. In a verify cell larger than a memory cell, the threshold change has reached a lower threshold level because the threshold change is faster than that of the memory cell.

By utilizing this property to make the verify cell shown in FIG. 1 larger in couple ratio than the array cell, the verify cell can be used for over-race and over-programming of the memory cell.

(2) In the circuit shown in FIG. 1, the memory cells are classified into first and second memory cells having different threshold values, and the first and second memory cells have a smaller couple ratio than each of the first and second memory cells. By adding two or more bit lines composed of the second verify cells, it is possible to deal with a multilevel memory. When making a multi-level memory by changing the voltage applied to the word line, the first level is set to the first level.
The verify is performed by the verify cell, and the second level is verified by the second verify cell. At this time, the couple ratio of the first verify cell and the second verify cell does not necessarily need to be the same.

[0058]

As described in detail above, according to the present invention,
To provide a non-volatile memory device having a verify function, particularly a page mode verify function, by which a verify or write operation can be performed easily, quickly and accurately by performing verify quickly and accurately. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the embodiment of FIG. 1;

FIG. 3 is a block diagram of another embodiment of the present invention.

FIG. 4 is a block diagram of still another embodiment of the present invention.

FIG. 5 is a sectional view showing a configuration of a memory cell included in still another embodiment of the present invention.

FIG. 6 is a sectional view showing a configuration of a verify cell included in still another embodiment of the present invention.

FIG. 7 is a diagram for explaining the operation of the embodiment having the cells shown in FIGS. 5 and 6;

FIG. 8 is a diagram for explaining the operation of the embodiment having the cells shown in FIGS. 5 and 6;

[Explanation of symbols]

WLi, WLi + 1, WLi + 2, WLi + n Word line BLi, BLi + 1, BLi + n, BLv1 Bit line M1i to M3 (i + 1) Memory cell Mv1 to Mv3, Mvi to Mvi + n Verify cell 8n (i + 1) ... switch transistor 10 ... X decoder 11 ... memory cell array 12, 12a ... Y decoder 13 ... verify cell column 14 ... sense amplifier 16 ... reference cell 17 ... level adjustment circuit 17a ... sense ratio control circuit 18 ... verify control circuit Reference Signs List 20 control circuit 21, 22 input / output buffer 23 data latch circuit 30 semiconductor substrate 36 cap

Claims (5)

[Claims] 1. A plurality of word lines arranged in a row direction, a plurality of bit lines arranged in a column direction intersecting with the word lines, and a plurality of bit lines arranged at intersections of the word lines and the bit lines. And at least one verify cell connected to each of the word lines in common with the plurality of nonvolatile memory cells and having substantially the same write / erase characteristics as the plurality of nonvolatile memory cells. A reference cell for generating a signal; and sense means for detecting an output of a verify cell connected to a word line selected at the time of writing / erasing and a reference signal from the reference cell with different predetermined sense sensitivities. A nonvolatile storage device having a verify function. 2. The verifying function according to claim 1, wherein the verifying cell is a part of a redundant cell array formed simultaneously with the non-volatile memory cell in preparation for a failure of the non-volatile memory cell. Nonvolatile storage device having the same. 3. The sensing means includes: a first supply means for directly supplying an output from the verify cell to the sensing means at the time of verification; and a supply means for adjusting the level of a reference signal from the reference cell and supplying the output to the sensing means. Second
2. The nonvolatile memory device having a verify function according to claim 1, further comprising a supply unit. 4. The sensing means comprises: a first supply means for directly supplying an output from the verify cell to the sense means at the time of verification; and a control signal supplied to an output control terminal of the reference cell for output. 2. The nonvolatile memory device having a verify function according to claim 1, further comprising: a second supply unit that adjusts a level of a reference signal and supplies the reference signal to the sense unit. 5. Each of said word line, bit line, memory cell, verify cell, reference cell, and sense means is formed on a single semiconductor chip, and said reference cell is formed of said memory cell pattern and sense means pattern. 2. The nonvolatile memory device having a verify function according to claim 1, wherein the nonvolatile memory device is arranged between the nonvolatile memory devices.