JP2010056518A - Nonvolatile semiconductor memory element and nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To actualize a nonvolatile memory in a standard logic CMOS process, while making the area of a memory cell minimum, to actualize an OTP and an MTP. <P>SOLUTION: A transistor formation portion 3 is arranged in an up and down direction, a metal wiring 12 is arranged in the left side of the transistor formation portion 3, and is connected to a drain. Moreover, a metal wiring 13 connected to a source is arranged in a right and left direction. Furthermore, an n-type well 2 is arranged in the left side of the transistor formation portion 3, a floating gate 9 is arranged in the right and left direction so as to face opposedly to the surface of this n-type well 2 and a gate region portion (region shown by the reference numeral 4) of the transistor, and a control gate wiring 19 which gives an electric potential to the floating gate 9 is also arranged in the right and left direction. By controlling a signal applied to a drain D, a control gate CG, and a source S, this memory cell is operated as the OTP or the MTP. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device, and in particular, a floating gate type nonvolatile semiconductor memory element (memory cell) configured by a standard CMOS process on a semiconductor substrate, and a nonvolatile semiconductor including the nonvolatile semiconductor memory element The present invention relates to a memory device (memory cell array).

  Nonvolatile memories represented by EPROM (Electrically Programmable Read Only Memory) have been used for many purposes because information does not disappear even when the power is turned off. For example, a typical use of EPROM is used as a replacement for a mask ROM in a medium capacity mask ROM microcomputer. EPROM is erasable with ultraviolet light and can be rewritten multiple times. However, since a package using transparent glass is expensive, it is sealed in an inexpensive plastic package and cannot be erased, but as an inexpensive non-volatile memory, OTP (One Time Programmable ROM) has become popular. Furthermore, in recent years, an embedded type so-called logic embedded memory (Embedded Memory) in which a nonvolatile memory is incorporated in a part of a system LSI or logic IC has become necessary. Furthermore, a small-sized non-volatile memory of about several hundred bits to several K bits is also required as an adjustment switch that is incorporated in an analog circuit and performs tuning of a highly accurate analog circuit.

  However, a non-volatile memory generally has a cell structure using two-layer polysilicon or three-layer polysilicon, and the manufacturing process is more complicated and requires more manufacturing processes than a standard CMOS logic process. Attempting to embed them at the same time, there were many manufacturing processes, yields were reduced, and the price (cost) of the product increased.

  As one means for solving this problem, an EEPROM (Electrically Erasable Programmable Read Only Memory) using one-layer polysilicon has been proposed (see, for example, Patent Document 1). If this one-layer polysilicon EEPROM is used, the number of manufacturing steps can be reduced as compared with the conventional two-layer polysilicon process. In addition to the floating gate type, an OTP of an antifuse type standard CMOS process in which a high voltage is applied to the oxide film of a capacitor to cause a gate breakdown to be stored has begun to appear.

  However, in the single-layer polysilicon EEPROM, since the second-layer polysilicon used as the control gate is omitted, it is necessary to embed a control gate composed of a diffusion layer under the floating gate, which is a standard CMOS used in logic. The manufacturing process is more complicated than the process. Furthermore, if the diffusion layer embedded at a high concentration is oxidized, an oxide film of poor quality is formed, and the probability of occurrence of a defect is high, and reliability is also a problem.

  In addition, since the antifuse type OTP causes 100% gate destruction, it cannot be restored once it has been destroyed. Therefore, it cannot be tested at the time of shipment and cannot be guaranteed, so there is a problem in reliability.

JP-A-10-289959

As described above, in the conventional EEPROM using one-layer polysilicon, since the second-layer polysilicon used as the control gate is omitted, it is necessary to embed a control gate made of a diffusion layer under the floating gate. In other words, the manufacturing process is more complicated than the standard CMOS process used in logic. Furthermore, if the diffusion layer embedded at a high concentration is oxidized, an oxide film of poor quality is formed, and the probability of occurrence of a defect is high, and reliability is also a problem.
In addition, since the antifuse type OTP causes 100% gate destruction, it cannot be restored once it has been destroyed. Therefore, it cannot be tested at the time of shipment and cannot be guaranteed, so there is a problem in reliability.

  The present invention has been made in view of such circumstances, and an object of the present invention is to realize a non-volatile memory by a standard logic CMOS process and to use an OTP, MTP (Multi Time Programmable ROM) using one-layer polysilicon. ) Can be provided, and a nonvolatile semiconductor memory device.

  In addition, in the nonvolatile semiconductor memory element, a nonvolatile semiconductor memory element capable of minimizing the area by compactly arranging a capacitor having a large area (a capacitor formed on the surface of the floating gate and the semiconductor substrate), and A non-volatile semiconductor memory device is provided.

  The present invention has been made to solve the above problems, and the nonvolatile semiconductor memory device of the present invention is a floating gate type single-layer polysilicon nonvolatile memory device configured by a standard CMOS process on a semiconductor substrate. When the first direction on the semiconductor substrate is represented in the up-down direction and the second direction orthogonal to the first direction is represented in the left-right direction, the first direction serving as the drain of the transistor in the up-down direction. A rectangular transistor forming portion in which a first n-type diffusion layer, a gate region portion forming a channel of a transistor, and a second n-type diffusion layer serving as a source of the transistor are sequentially disposed; On the left or right side of the transistor, parallel to the transistor formation portion and spaced from the surface of the semiconductor substrate by a predetermined distance. A first metal wiring connected to the in through a contact, and a rectangular n-type well formed on the left side of the transistor formation portion in the left-right direction with a predetermined width and depth on the semiconductor substrate. The semiconductor substrate is disposed in the left-right direction so as to face the semiconductor substrate surface, and a region on the left end side thereof faces the surface of the n-type well, and a region on the right end side faces the gate region portion. Adjacent to the left side of the region of the n-type well facing the floating gate, the rectangular floating gate is formed with a predetermined width and depth in the left-right direction and connected to the control gate wiring. A p-type diffusion layer serving as a connection terminal is disposed in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the floating gate. And a control gate line connected to the p-type diffusion layer by a semiconductor device and a left-right direction at a predetermined distance from the semiconductor substrate surface so as to face the second n-type diffusion layer, and And a second metal wiring connected to the second n-type diffusion layer by a contact.

  The nonvolatile semiconductor memory device of the present invention is a floating gate type single-layer polysilicon nonvolatile memory device configured by a standard CMOS process on a semiconductor substrate, and the first direction on the semiconductor substrate is vertically changed. The first n-type diffusion layer serving as the drain of the transistor and the channel of the transistor are formed in the vertical direction when the second direction expressed by the direction and the second direction perpendicular to the first direction is expressed by the horizontal direction. A rectangular transistor forming portion in which a gate region portion and a second n-type diffusion layer serving as a source of the transistor are sequentially arranged, on the left side or the right side of the transistor forming portion, in parallel with the transistor forming portion and A first metal disposed at a predetermined distance from the surface of the semiconductor substrate and connected to the drain of the transistor by a contact A line-shaped D-type (depletion-type) channel implanter having a predetermined width and depth on the left side of the transistor forming portion on the semiconductor substrate; A rectangular shape that is disposed in the left-right direction so as to face the substrate surface, and that the region on the left end side faces the surface of the channel implanter and the region on the right end side faces the gate region portion. A floating gate, a third n-type diffusion layer adjacent to the left side of the channel implanter, having a predetermined width and depth and formed in the left-right direction, and serving as a connection terminal to the control gate wiring; The third n-type diffusion layer and the third n-type diffusion layer are disposed in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the floating gate. A control gate line connected by contact and a second n-type diffusion layer which is a source of the transistor, and is arranged in a lateral direction at a predetermined distance from the surface of the semiconductor substrate. And a second metal wiring connected to the n-type diffusion layer by a contact.

  According to another aspect of the present invention, the nonvolatile semiconductor memory element is configured as an OTP (One Time Programmable ROM), and a first voltage is applied to the control gate of the transistor during charge accumulation in the floating gate. , A second voltage is applied to the drain, a voltage of “0” V is applied to the source, hot electrons are generated near the drain of the transistor, and the hot electrons are injected into the floating gate. It is characterized by being comprised.

  In the nonvolatile semiconductor memory device of the present invention, the nonvolatile semiconductor memory device is configured as an MTP (Multi Time Programmable ROM), and when the charge stored in the floating gate is stored, the first control gate of the transistor is connected to the first control gate of the transistor. Is applied, a second voltage is applied to the drain, a voltage of "0" V is applied to the source, hot electrons are generated near the drain of the transistor, and the hot electrons are injected into the floating gate. At the same time, when erasing the electric charge to the floating gate, as a first erasing means, a voltage of “0” V is applied to the control gate of the transistor, a third voltage is applied to the drain, and the source is turned on. Open or apply 4th voltage (3rd voltage> 4th voltage) Applying a high electric field between the floating gate and the floating gate to release the charge of the floating gate by an FN current (Fowler-Nordheim tunneling current), and a second operation performed after execution of the first erasing means As an erasing means, “0” V or a fifth voltage is applied to the control gate of the transistor, the third voltage is applied to the drain, and “0” V is applied to the source (third voltage). > Fifth voltage), means for generating hot electrons near the drain of the transistor and injecting the hot electrons into the floating gate for a predetermined time.

  In addition, the nonvolatile semiconductor memory device of the present invention includes a memory cell which is a floating gate type single layer polysilicon nonvolatile memory element formed by a standard CMOS process on a semiconductor substrate, and crosses a word line and a data line. A non-volatile semiconductor memory device having a memory cell array arranged in a matrix form, wherein the memory cell is an OTP (One Time Programmable ROM), and controls the transistor during charge accumulation in the floating gate. A first voltage is applied to the gate, a second voltage is applied to the drain, a voltage of “0” V is applied to the source, hot electrons are generated near the drain of the transistor, and the hot electrons are The nonvolatile semiconductor memory is configured to be injected into a floating gate. Based on the number of input / output I / O bits of column address n bits (n ≧ 1) and io bits (io ≧ 1), the memory device moves the memory cell array in the column direction in units of the column address n bits. A plurality of memory cell blocks configured to be divided into the number of I / O bits are arranged, and a plurality of bit lines in which the drains of the transistors of each memory cell are commonly connected along the row direction are provided for each row. A word line for commonly connecting the control gates of the transistors of the memory cells along the column direction; a source line for commonly connecting the sources of the transistors of the memory cells; and a row decoder provided for each row A row decoder that receives an address signal and generates a row selection signal for selecting the memory cell; and a row selection signal output from each of the row decoders. A first level shift circuit for converting the first signal voltage Vp1 applied to the word line to a signal, and a column decoder provided corresponding to the number n of bits in the column direction in the memory cell block, N column decoders for outputting a column selection signal for selecting one memory cell from the memory cell block, and a second level for converting the column selection signal output from the column decoder into a signal of the second signal voltage Vp2. A column selection transistor in n-bit units provided for each of the shift circuit and the memory cell block, the second signal voltage Vp2 output from the second level shift circuit as a gate input, and each memory A column selection transistor for selecting a bit line of one memory cell from a cell block and selecting a memory cell having the number of I / O bits; A data input / output line having the number of I / O bits connected to the bit line having the number of I / O bits selected by the selection transistor via the column selection transistor, and write data having the number of I / O bits A write control circuit that outputs a third voltage signal Vp3 applied to the drain of the transistor through the data input / output line when data is written and erased in response to the input signal, and read to the data input / output line. And a sense amplifier circuit that amplifies the data of the output memory cell and outputs the amplified data to the outside.

  In addition, the nonvolatile semiconductor memory device of the present invention includes a memory cell which is a floating gate type single layer polysilicon nonvolatile memory element formed by a standard CMOS process on a semiconductor substrate, and crosses a word line and a data line. A non-volatile semiconductor memory device having a memory cell array arranged in a matrix form, wherein the memory cell is an OTP (One Time Programmable ROM), and controls the transistor during charge accumulation in the floating gate. A first voltage is applied to the gate, a second voltage is applied to the drain, a voltage of “0” V is applied to the source, hot electrons are generated near the drain of the transistor, and the hot electrons are The nonvolatile semiconductor memory is configured to be injected into a floating gate. The memory device includes a plurality of memory cell blocks configured by dividing the memory cell array in the column direction in units of the number of input / output I / O bits of io bits (io ≧ 1). A plurality of bit lines in which the drains of the transistors are commonly connected in the row direction, and word lines provided for each row, the word lines commonly connecting the control gates of the transistors of the memory cells in the column direction; A source line to which the sources of the transistors of the memory cells are connected in common; a row decoder provided for each row; a row decoder that receives the address signal and generates a row selection signal for selecting the memory cell; A first level shift circuit that converts a row selection signal output from each row decoder into a signal of a first signal voltage Vp1 applied to the word line. A column decoder for receiving an address signal and selecting the memory cell in the column direction in units of the number of I / O bits; and a second signal voltage Vp2 for selecting the selection signal output from the column decoder. And a second signal voltage output from the second level shift circuit, the second level shift circuit for converting to a column select transistor provided for each memory cell block in units of the number of I / O bits. A column selection transistor for selecting a bit line of the memory cell having the number of I / O bits from the selected memory cell block with Vp2 as a gate input, and a bit line having the number of I / O bits selected by the column selection transistor The data input / output line having the number of I / O bits and the write data having the number of I / O bits connected to each other via the column selection transistor A write control circuit for outputting a third voltage signal Vp3 applied to the drain of the first transistor through the data input / output line when data is written and erased in response to the input signal; and the data input / output line And a sense amplifier circuit that amplifies the data read from the memory cell and outputs it to the outside.

  In addition, the nonvolatile semiconductor memory device of the present invention includes a memory cell which is a floating gate type single layer polysilicon nonvolatile memory element formed by a standard CMOS process on a semiconductor substrate, and crosses a word line and a data line. A non-volatile semiconductor memory device having a memory cell array arranged in a matrix, wherein the memory cell is configured as an MTP (Multi Time Programmable ROM), and a MOS transistor is used when electric charges are accumulated in the floating gate. A hot electron is generated in the vicinity of the drain of the first electrode and injected into the floating gate, and at the time of erasing the electric charge to the floating gate, an FN current (Fowler-Nordheim tunneling current) causes the floating gate to Note charge And a second step of generating hot electrons near the drain of the transistor and injecting the hot electrons into the floating gate for a predetermined time after execution of the first step. It was configured as described above.

  In addition, the nonvolatile semiconductor memory device of the present invention includes a memory cell which is a floating gate type single layer polysilicon nonvolatile memory element formed by a standard CMOS process on a semiconductor substrate, and crosses a word line and a data line. A non-volatile semiconductor memory device having a memory cell array arranged in a matrix, wherein the memory cell is configured as an MTP (Multi Time Programmable ROM), and a MOS transistor is used when electric charges are accumulated in the floating gate. Hot electrons are generated in the vicinity of the drain of the semiconductor, and the hot electrons are injected into the floating gate. At the time of erasing the charge to the floating gate, an electric charge is injected into the floating gate by an FN current (Fowler-Nordheim tunnel current). After The non-volatile semiconductor memory device is configured to generate hot electrons near the drain of the transistor and inject the hot electrons into the floating gate for a predetermined time. Based on the number of input / output I / O bits of io bits (io ≧ 1), a plurality of memory cell arrays are divided into the number of I / O bits in the column address in units of n bits in the column direction. A memory cell block is arranged, and a plurality of bit lines in which drains of transistors of each memory cell are commonly connected in a row direction, and word lines provided for each row, the control gate of the transistor of the memory cell A word line commonly connected in the column direction and a source line provided for each row, wherein the memory cell A source line commonly connecting the sources of the transistors in the column direction, and a switch provided for each of the source lines, for selecting whether the source line is grounded or opened to GND (“0” V) And a row decoder provided for each row, which receives an address signal, generates a row selection signal for selecting the memory cell, selects a voltage level of the row selection signal, and applies it to the word line And a row decoder for outputting a signal for controlling on / off of the switching transistor, and a column decoder provided corresponding to the number of bits n in the column direction in the memory cell block, each including 1 from each memory cell block. N column decoders for outputting a column selection signal for selecting one memory cell, and a column selection signal output from the column decoder as a second signal. A second level shift circuit for converting the signal to the signal Vp2 and a column selection transistor in n-bit units provided for each of the memory cell blocks, the column being output from the second level shift circuit A selection signal Vp2 is used as a gate input, a bit line of one memory cell is selected from each memory cell block, and a memory cell having the number of I / O bits is selected, and the column selection transistor selected by the column selection transistor The I / O bit number data input / output line connected to the I / O bit number bit line via the column selection transistor and the I / O bit number write data input signal are received. When writing and erasing data, a third voltage signal V applied to the drain of the transistor through the data input / output line. A write control circuit for outputting a 3, characterized in that it comprises a sense amplifier circuit for outputting to the outside amplifies data of the memory cell read to the data input and output lines.

  In the nonvolatile semiconductor memory device of the present invention, the row decoder receives 2-bit write control signals E1 and E2 as control inputs, and writes data to memory cells according to the values of the control signals E1 and E2. A write mode in which the first signal voltage Vp1 is output to the word line and the switch transistor is turned on; and "0" V is output to the word line when erasing data in the memory cell; and the switch transistor A first erasing mode for outputting a signal for turning off, and a second erasing for outputting a signal for turning on the switching transistor by outputting "0" V of the word line at the time of erasing data of the memory cell A mode.

  In addition, the nonvolatile semiconductor memory device of the present invention includes a memory cell which is a floating gate type single layer polysilicon nonvolatile memory element formed by a standard CMOS process on a semiconductor substrate, and crosses a word line and a data line. A non-volatile semiconductor memory device having a memory cell array arranged in a matrix, wherein the memory cell is configured as an MTP (Multi Time Programmable ROM), and a MOS transistor is used when electric charges are accumulated in the floating gate. Hot electrons are generated in the vicinity of the drain of the semiconductor, and the hot electrons are injected into the floating gate. At the time of erasing the charge to the floating gate, an electric charge is injected into the floating gate by an FN current (Fowler-Nordheim tunnel current). After The non-volatile semiconductor memory device is configured to generate hot electrons in the vicinity of the drain of the transistor and inject the hot electrons into the floating gate for a predetermined time, and the non-volatile semiconductor memory device has an io bit (io ≧ 1) input / output. A plurality of memory cell blocks configured by dividing the memory cell array in the column direction by using the number of I / O bits as a unit are arranged, and a plurality of drains of the transistors of the memory cells are commonly connected along the row direction. A bit line, a word line provided for each row, a word line commonly connecting the control gates of the transistors of the memory cell along a column direction, and a source line provided for each row, the memory cell A source line commonly connecting the sources of the transistors along the column direction, and each of the source lines A switching transistor for selecting whether the source line is grounded or opened to GND (“0” V), and a row decoder provided for each row, which receives the address signal and A row decoder for generating a row selection signal for selecting a memory cell, selecting a voltage level of the row selection signal and applying it to the word line, and outputting a signal for controlling on / off of the switch transistor; and an address A column decoder that receives the signal and outputs a column selection signal for selecting the memory cells in the column direction in units of the number of I / O bits, and a column selection signal output from the column decoder as the second signal voltage Vp2. A second level shift circuit for conversion; and a column selection transistor for each I / O bit number provided for each memory cell block, A column selection transistor that selects the bit line of the memory cell having the number of I / O bits from the selected memory cell block by using the second signal voltage Vp2 output from the level shift circuit as a gate input, and the column selection transistor A data input / output line having the number of I / O bits connected to the selected bit line having the number of I / O bits via the column selection transistor, and an input signal of the write data having the number of I / O bits. When a data write and data erase are received, a write control circuit that outputs a fourth voltage signal Vp3 applied to the drain of the transistor of the memory cell through the data input / output line, and a read to the data input / output line And a sense amplifier circuit that amplifies the data of the output memory cell and outputs the amplified data to the outside.

  In the nonvolatile semiconductor memory device of the present invention, the row decoder receives 2-bit write control signals E1 and E2 as control inputs, and writes data to memory cells according to the values of the control signals E1 and E2. A write mode in which the first signal voltage Vp1 is output to the word line and the switch transistor is turned on; and "0" V is output to the word line when erasing data in the memory cell; and the switch transistor A first erasing mode for outputting a signal for turning off, and a second erasing for outputting a signal for turning on the switching transistor by outputting "0" V of the word line at the time of erasing data of the memory cell A mode.

  In addition, the nonvolatile semiconductor memory device of the present invention includes a memory cell which is a floating gate type single layer polysilicon nonvolatile memory element formed by a standard CMOS process on a semiconductor substrate, and crosses a word line and a data line. A non-volatile semiconductor memory device having a memory cell array arranged in a matrix, wherein the memory cell is configured as an MTP (Multi Time Programmable ROM), and a MOS transistor is used when electric charges are accumulated in the floating gate. Hot electrons are generated in the vicinity of the drain of the semiconductor, and the hot electrons are injected into the floating gate. At the time of erasing the charge to the floating gate, an electric charge is injected into the floating gate by an FN current (Fowler-Nordheim tunnel current). After The non-volatile semiconductor memory device is configured to generate hot electrons near the drain of the transistor and inject the hot electrons into the floating gate for a predetermined time. Based on the number of input / output I / O bits of io bits (io ≧ 1), a plurality of memory cell arrays are divided into the number of I / O bits in the column address in units of n bits in the column direction. A memory cell block is arranged, and a plurality of bit lines in which drains of transistors of each memory cell are commonly connected in a row direction, and word lines provided for each row, the control gate of the transistor of the memory cell A word line for commonly connecting CGs along the column direction and a source line provided for every two rows in a pair. A source line commonly connecting the transistors of the memory cells in the two rows along the column direction, and two switching transistors provided for each of the source lines, the two row decoders of the pair A first switching transistor that selects whether the source line is grounded or opened to GND (“0” V) by a signal from one side, and the source by a signal from the other of the two paired row decoders A second switch transistor for selecting whether the line is grounded or opened to GND (“0” V), and a row decoder provided for each row, the row selecting the memory cell in response to an address signal A selection signal is generated, a voltage level of the row selection signal is selected and applied to a word line, and a pair is formed by two, and the first switch is started from one A row decoder that outputs a control signal for turning on and off the transistor for the transistor and a control signal for turning on and off the second switch transistor from the other, and corresponds to the number of bits n in the column direction in the memory cell block N column decoders for outputting a column selection signal for selecting one memory cell from each of the memory cell blocks, and a column selection signal output from the column decoder as a second signal. A second level shift circuit for converting the signal into a signal of voltage Vp2, and a column selection transistor in units of n bits provided for each of the memory cell blocks, the second level shift circuit being output from the second level shift circuit The signal voltage Vp2 of the memory cell is used as a gate input, and a bit line of one memory cell is selected from each memory cell block, and the I / O bit is selected. And a data input / output line having the number of I / O bits connected to the bit line having the number of I / O bits selected by the column selection transistor via the column selection transistor. And a third voltage signal Vp3 to be applied to the drain of the transistor through the data input / output line when receiving the input signal of the write data having the number of I / O bits and performing data writing and data erasing. And a sense amplifier circuit that amplifies the data of the memory cell read to the data input / output line and outputs the amplified data to the outside.

  The nonvolatile semiconductor memory device of the present invention outputs the first signal voltage Vp1 to the word line when the row decoder is a selected row decoder when writing data to the memory cell, and In the write mode in which the switch transistor corresponding to the row decoder is turned on, and when erasing data of the memory cell, when the selected row decoder is selected, “0” V is output to the word line, and the row decoder Outputs a signal for turning off the corresponding switching transistor, and outputs a predetermined voltage signal to the word line when the row decoder is a non-selected row decoder, and turns off the switching transistor corresponding to the row decoder. The first erasing mode for outputting a signal to be used when the row decoder is selected at the time of erasing data of the memory cell. "0" V is output to the line, a signal for turning on the switching transistor corresponding to the row decoder is output, and "0" is output to the word line when the row decoder is not selected. And a second erase mode for outputting a signal for turning off the switching transistor corresponding to the row decoder.

  In addition, the nonvolatile semiconductor memory device of the present invention includes a memory cell which is a floating gate type single layer polysilicon nonvolatile memory element formed by a standard CMOS process on a semiconductor substrate, and crosses a word line and a data line. A non-volatile semiconductor memory device having a memory cell array arranged in a matrix, wherein the memory cell is configured as an MTP (Multi Time Programmable ROM), and a MOS transistor is used when electric charges are accumulated in the floating gate. Hot electrons are generated in the vicinity of the drain of the semiconductor, and the hot electrons are injected into the floating gate. At the time of erasing the charge to the floating gate, an electric charge is injected into the floating gate by an FN current (Fowler-Nordheim tunnel current). After The non-volatile semiconductor memory device is configured to generate hot electrons in the vicinity of the drain of the transistor and inject the hot electrons into the floating gate for a predetermined time, and the non-volatile semiconductor memory device has an io bit (io ≧ 1) input / output. A plurality of memory cell blocks configured by dividing the memory cell array in the column direction in units of the number of I / O bits are arranged, and a plurality of transistors in which the drains of the transistors of the memory cells are commonly connected in the row direction A bit line, a word line provided for each row, a word line commonly connecting the control gates CG of the transistors of the memory cell along the column direction, and a source line provided for each pair of two rows A source for commonly connecting the sources of the transistors of the memory cells in the two rows along the column direction. And two switching transistors provided for each source line, and the source line is grounded or opened to GND (“0” V) by a signal from one of the paired two row decoders. A first switching transistor that selects the second switching transistor, and a second switching signal that selects whether the source line is grounded or opened to GND (“0” V) according to a signal from the other of the two paired row decoders. A switching transistor and a row decoder provided for each row, receiving an address signal, generating a row selection signal for selecting the memory cell, selecting a voltage level of the row selection signal, and applying it to the word line In addition, a control signal for turning on / off the first switch transistor is output from one, and the second switch transistor is output from the other. A row decoder that outputs a control signal for turning on and off the register; a column decoder that receives an address signal and outputs a column selection signal for selecting the memory cell in the column direction in units of the number of I / O bits; and the column A second level shift circuit for converting a selection signal output from the decoder into a second signal voltage Vp2, and a column selection transistor in units of the number of I / O bits provided for each of the memory cell blocks, A column selection transistor for selecting the bit line of the memory cell having the number of I / O bits from the selected memory cell block, using the second signal voltage Vp2 output from the level shift circuit of 2 as a gate input; Data of the number of I / O bits connected via the column selection transistor to the bit line of the number of I / O bits selected by the transistor A fourth voltage applied to the drain of the first transistor through the data input / output line when receiving an input signal of the write data having the number of I / O bits and performing data writing and data erasing. A write control circuit that outputs a signal Vp3 and a sense amplifier circuit that amplifies the data of the memory cell read to the data input / output line and outputs the data to the outside.

  The nonvolatile semiconductor memory device of the present invention outputs the first signal voltage Vp1 to the word line when the row decoder is a selected row decoder when writing data to the memory cell, and In the write mode in which the switch transistor corresponding to the row decoder is turned on, and when erasing data of the memory cell, when the selected row decoder is selected, “0” V is output to the word line, and the row decoder Outputs a signal for turning off the corresponding switching transistor, and outputs a predetermined voltage signal to the word line when the row decoder is a non-selected row decoder, and turns off the switching transistor corresponding to the row decoder. The first erasing mode for outputting a signal to be used when the row decoder is selected at the time of erasing data of the memory cell. "0" V is output to the line, a signal for turning on the switching transistor corresponding to the row decoder is output, and "0" is output to the word line when the row decoder is not selected. And a second erase mode for outputting a signal for turning off the switching transistor corresponding to the row decoder.

  In addition, the nonvolatile semiconductor memory device of the present invention includes a memory cell which is a floating gate type single layer polysilicon nonvolatile memory element formed by a standard CMOS process on a semiconductor substrate, and crosses a word line and a data line. A non-volatile semiconductor memory device arranged in a matrix form, wherein the memory cell represents a layout of its constituent parts in a first direction on the semiconductor substrate in a vertical direction, and the first direction When the second direction orthogonal to the vertical direction is expressed in the left-right direction, the first n-type diffusion layer serving as the drain of the transistor, the gate region forming the channel of the transistor, the source of the transistor in the vertical direction, A square-shaped transistor forming portion in which second n-type diffusion layers are sequentially arranged, and on the left side of the transistor forming portion. On the right side, on the semiconductor substrate, a first metal wiring that is arranged in parallel to the transistor formation portion and at a predetermined distance from the surface of the semiconductor substrate and connected to the drain of the transistor by a contact, On the left side of the transistor formation portion, a rectangular n-type well formed in the left-right direction with a predetermined width and depth, and disposed in the left-right direction facing the semiconductor substrate surface, the left end side thereof A rectangular floating gate arranged so that the region of the n-type well faces the surface of the n-type well and the region on the right end side faces the gate region, and the floating gate of the n-type well faces the floating gate Adjacent to the left side of the region, a p-type diffusion layer formed in the left-right direction with a predetermined width and depth and serving as a connection terminal to the control gate wiring; A control gate line that is arranged in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the floating gate, and that is connected to the p-type diffusion layer by a contact and serves as a source of the transistor A second metal disposed in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the second n-type diffusion layer, and connected to the second n-type diffusion layer by a contact Wiring, and in the arrangement of each of the memory cells, the two n memory cells are arranged symmetrically on the left and right with the n-type well in common, and the two memory cells arranged symmetrically on the left and right On the other hand, a total of four memory cells including two memory cells arranged symmetrically in the downward direction with the second metal wiring in common with each other are arranged. As the main unit, four memory cells, which are basic units of the above configuration, are arranged in parallel in the left-right direction and arranged in parallel in the up-down direction.

  In addition, the nonvolatile semiconductor memory device of the present invention includes a memory cell which is a floating gate type single layer polysilicon nonvolatile memory element formed by a standard CMOS process on a semiconductor substrate, and crosses a word line and a data line. A non-volatile semiconductor memory device arranged in a matrix form, wherein the memory cell represents a layout of its constituent parts in a first direction on the semiconductor substrate in a vertical direction, and the first direction When the second direction orthogonal to the vertical direction is expressed in the left-right direction, the first n-type diffusion layer serving as the drain of the transistor, the gate region forming the channel of the transistor, the source of the transistor in the vertical direction, A square-shaped transistor forming portion in which second n-type diffusion layers are sequentially arranged, and on the left side of the transistor forming portion. On the right side, on the semiconductor substrate, a first metal wiring that is arranged in parallel to the transistor formation portion and at a predetermined distance from the surface of the semiconductor substrate and connected to the drain of the transistor by a contact, On the left side of the transistor formation portion, a square-shaped D-type (depletion-type) channel implant formed in the left-right direction with a predetermined width and depth, and disposed in the left-right direction facing the semiconductor substrate surface And a rectangular floating gate arranged such that a region on the left end side faces the surface of the channel implanter and a region on the right end side faces the gate region portion of the transistor, and the channel Adjacent to the left side of the implant, and formed in the left-right direction with a predetermined width and depth, the control gauge A third n-type diffusion layer serving as a connection terminal to the first wiring, and a third n-type diffusion layer disposed in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the floating gate. A control gate line connected to the type diffusion layer by contact and a second n-type diffusion layer serving as the source of the transistor are arranged in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the second n-type diffusion layer. And a second metal wiring connected to the second n-type diffusion layer through a contact, and a third n-type diffusion layer serving as a connection terminal of the control gate in the arrangement of the memory cells. For the two memory cells arranged symmetrically to the left and right so that they are shared with each other and the two memory cells arranged symmetrically to the left and right The four memory cells, which are the basic units of the above-described configuration, are arranged in parallel in the left-right direction. And arranged side by side in parallel in the vertical direction.

  In addition, the nonvolatile semiconductor memory device of the present invention includes a memory cell which is a floating gate type single layer polysilicon nonvolatile memory element formed by a standard CMOS process on a semiconductor substrate, and crosses a word line and a data line. A non-volatile semiconductor memory device arranged in a matrix form, wherein the memory cell represents a layout of its constituent parts in a first direction on the semiconductor substrate in a vertical direction, and the first direction When the second direction orthogonal to the vertical direction is expressed in the left-right direction, the first n-type diffusion layer serving as the drain of the transistor, the gate region forming the channel of the transistor, the source of the transistor in the vertical direction, A square-shaped transistor forming portion in which second n-type diffusion layers are sequentially arranged, and on the left side of the transistor forming portion. On the right side, on the semiconductor substrate, a first metal wiring that is arranged in parallel to the transistor formation portion and at a predetermined distance from the surface of the semiconductor substrate and connected to the drain of the transistor by a contact, On the left side of the transistor formation portion, a square-shaped D-type (depletion-type) channel implant formed in the left-right direction with a predetermined width and depth, and disposed in the left-right direction facing the semiconductor substrate surface And a rectangular floating gate arranged such that a region on the left end side faces the surface of the channel implanter and a region on the right end side faces the gate region portion of the transistor, A floatin disposed with a square area expansion portion in a left end region facing the surface of the channel implanter A gate, a third n-type diffusion layer adjacent to the left side of the channel implanter, having a predetermined width and depth and formed in a horizontal direction and serving as a connection terminal to the control gate wiring; and the floating A control gate line disposed in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the gate, and connected to the third n-type diffusion layer by a contact; a source of the transistor; The second n-type diffusion layer is disposed in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the second n-type diffusion layer, and is connected to the second n-type diffusion layer by a contact. And a third n-type diffusion layer serving as a connection terminal of the control gate in the arrangement of the memory cells. In this way, the second metal wiring is common to the two memory cells arranged symmetrically on the left and right and the two memory cells arranged symmetrically on the left and right, and arranged symmetrically in the downward direction. As a basic unit of arrangement, a total of four memory cells of the two memory cells, the four memory cells as the basic unit of the above configuration are arranged side by side in parallel in the horizontal direction and arranged in parallel in the vertical direction as well. It is characterized by doing.

  In addition, the nonvolatile semiconductor memory device of the present invention includes a memory cell which is a floating gate type single layer polysilicon nonvolatile memory element formed by a standard CMOS process on a semiconductor substrate, and crosses a word line and a data line. A non-volatile semiconductor memory device arranged in a matrix form, wherein the memory cell represents a layout of its constituent parts in a first direction on the semiconductor substrate in a vertical direction, and the first direction When the second direction orthogonal to the vertical direction is expressed in the left-right direction, the first n-type diffusion layer serving as the drain of the transistor, the gate region forming the channel of the transistor, the source of the transistor in the vertical direction, A square-shaped transistor forming portion in which second n-type diffusion layers are sequentially arranged, and on the left side of the transistor forming portion. On the right side, on the semiconductor substrate, a first metal wiring that is arranged in parallel to the transistor formation portion and at a predetermined distance from the surface of the semiconductor substrate and connected to the drain of the transistor by a contact, On the left side of the transistor formation portion, a square-shaped D-type (depletion-type) channel implant formed in the left-right direction with a predetermined width and depth, and disposed in the left-right direction facing the semiconductor substrate surface And a rectangular floating gate arranged such that a region on the left end side faces the surface of the channel implanter and a region on the right end side faces the gate region portion of the transistor, A floatin disposed with a square area expansion portion in a left end region facing the surface of the channel implanter A gate, a third n-type diffusion layer adjacent to the left side of the channel implanter, having a predetermined width and depth and formed in a horizontal direction and serving as a connection terminal to the control gate wiring; and the floating A control gate line disposed in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the gate, and connected to the third n-type diffusion layer by a contact; a source of the transistor; The second n-type diffusion layer is disposed in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the second n-type diffusion layer, and is connected to the second n-type diffusion layer by a contact. And a third n-type diffusion layer serving as a connection terminal of the control gate in the arrangement of the memory cells. Thus, the two memory cells are arranged symmetrically, and the memory cells are arranged symmetrically upward with respect to the two memory cells arranged symmetrically on the left and right, and these four memory cells are used as a unit. The memory cell arrays are arranged in the left-right direction, and the memory cell arrays arranged in the left-right direction are arranged in parallel in the up-down direction.

  The nonvolatile semiconductor memory device of the present invention is a floating gate type single-layer polysilicon nonvolatile memory device configured by a standard CMOS process on a semiconductor substrate, and the first direction on the semiconductor substrate is vertically changed. The first n-type diffusion layer serving as the drain of the transistor and the channel of the transistor are formed in the vertical direction when the second direction expressed by the direction and the second direction perpendicular to the first direction is expressed by the horizontal direction. A rectangular transistor forming portion in which a gate region portion and a second n-type diffusion layer serving as a source of the transistor are sequentially arranged, on the left side or the right side of the transistor forming portion, in parallel with the transistor forming portion and A first metal disposed at a predetermined distance from the surface of the semiconductor substrate and connected to the drain of the transistor by a contact A line, an n-type well formed in a horizontal direction with a predetermined width and depth on the left side of the transistor forming portion on the semiconductor substrate, and a horizontal direction facing the surface of the semiconductor substrate. And a rectangular floating gate disposed so that a region on the left end side thereof faces the surface of the n-type well and a region on the right end side faces the gate region portion, and the n-type well Adjacent to the left side of the region facing the floating gate, a p-type diffusion layer having a predetermined width and depth and formed in the left-right direction and serving as a connection terminal to the control gate wiring, and the floating gate A control gate which is arranged in a lateral direction with a predetermined distance from the surface of the semiconductor substrate so as to face each other and which is connected to the p-type diffusion layer by a contact. A wiring is disposed in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the second n-type diffusion layer, and is connected to the second n-type diffusion layer by a contact. A second metal wiring and an n-type diffusion layer for applying a desired potential to the n-type well, on the surface of the n-type well, above the p-type diffusion layer and on the first n-type well A fourth n-type diffusion layer formed with a predetermined width and depth at a predetermined position in a region on the left side of the type diffusion layer; and a predetermined distance from the surface of the semiconductor substrate in parallel with the transistor formation portion. And a third metal wiring connected to the fourth n-type diffusion layer by a contact while being spaced apart from each other.

  The nonvolatile semiconductor memory element of the present invention is a nonvolatile semiconductor memory element having a fourth n-type diffusion layer and a third metal wiring for applying a desired voltage to the n-type well. The semiconductor memory device is configured as an OTP (One Time Programmable ROM), and a first voltage is applied to the control gate of the transistor and a second voltage is applied to the drain when the charge is accumulated in the floating gate. A voltage is applied, a voltage of “0” V is applied to the source, hot electrons are generated in the vicinity of the drain of the transistor, and the hot electrons are injected into the floating gate. To do.

  The nonvolatile semiconductor memory element of the present invention includes a nonvolatile semiconductor memory element having a fourth n-type diffusion layer and a third metal wiring for applying a desired voltage to the n-type well. The nonvolatile semiconductor memory device is configured as an MTP (Multi Time Programmable ROM), and applies a first voltage to the control gate of the transistor and stores a second voltage to the drain when the charge accumulated in the floating gate is accumulated. And a voltage of “0” V is applied to the source, hot electrons are generated in the vicinity of the drain of the transistor, the hot electrons are injected into the floating gate, and charge to the floating gate is generated. When erasing, as a first erasing means, a voltage of “0” V is applied to the control gate of the transistor. And applying a third voltage to the drain and opening the source or applying a fourth voltage (third voltage> fourth voltage) and applying a high electric field between the drain and the floating gate. As a second erasing means performed after the execution of the first erasing means, and a means for discharging the floating gate charge by an FN current (Fowler-Nordheim tunneling current). “0” V or a fifth voltage is applied to the gate, the third voltage is applied to the drain, “0” V is applied to the source (third voltage> fifth voltage), and Means for generating hot electrons near the drain of the transistor and injecting the hot electrons into the floating gate for a predetermined time. To.

  In addition, the nonvolatile semiconductor memory device of the present invention is configured to set the voltage applied to the third metal wiring to be equal to or higher than the voltage of the control gate. .

  In addition, the nonvolatile semiconductor memory device of the present invention includes a memory cell which is a floating gate type single layer polysilicon nonvolatile memory element formed by a standard CMOS process on a semiconductor substrate, and crosses a word line and a data line. A non-volatile semiconductor memory device having a memory cell array arranged in a matrix, each memory cell including a fourth n-type diffusion layer for applying a desired voltage to the n-type well. The nonvolatile semiconductor memory device includes a nonvolatile semiconductor memory device having a third metal wiring, and the nonvolatile semiconductor memory device has input / output I / O bits of column address n bits (n ≧ 1) and io bits (io ≧ 1). The memory cell array is divided into the number of I / O bits in the column address in n-bit units in the column direction based on the number of I / O bits. A plurality of bit lines in which a cell block is arranged and drains of the transistors of each memory cell are commonly connected in a row direction; and a word line provided for each row, the control gate of the transistor of the memory cell being A word line commonly connected along a column direction, a source line to which sources of transistors of each memory cell are commonly connected, and a row decoder provided for each row, which receives the address signal and selects the memory cell A row decoder for generating a row selection signal; a first level shift circuit for converting a row selection signal output from each row decoder into a signal of a first signal voltage Vp1 applied to the word line; and the memory cell block A column decoder provided corresponding to the number of bits n in the column direction in the memory cell block, one from each memory cell block N column decoders for outputting a column selection signal for selecting a memory cell, a second level shift circuit for converting a column selection signal output from the column decoder into a signal of a second signal voltage Vp2, and the memory An n-bit unit column selection transistor provided for each cell block, wherein the second signal voltage Vp2 output from the second level shift circuit is used as a gate input, and one memory cell is connected from each memory cell block. A column selection transistor for selecting a bit line of the cell and selecting a memory cell having the number of I / O bits, and a bit line having the number of I / O bits selected by the column selection transistor via the column selection transistor The data input / output line connected with the number of I / O bits connected and the input signal of the write data with the number of I / O bits are received to write data. A write control circuit for outputting a third voltage signal Vp3 to be applied to the drain of the transistor through the data input / output line when writing and erasing data; and a memory cell read out to the data input / output line; And a sense amplifier circuit that amplifies data and outputs the amplified data to the outside.

  In addition, the nonvolatile semiconductor memory device of the present invention includes a memory cell which is a floating gate type single layer polysilicon nonvolatile memory element formed by a standard CMOS process on a semiconductor substrate, and crosses a word line and a data line. Each of the memory cells includes a fourth n-type diffusion layer and a third n-type diffusion layer for applying a desired voltage to the n-type well. Two memory cells that are configured by a nonvolatile semiconductor memory element having metal wiring and that are arranged symmetrically on the left and right with the n-type well in common with each other in the arrangement of the memory cells. Two memory cells arranged symmetrically in the downward direction with respect to the two memory cells arranged in the same manner, A total of four memory cells are used as basic units of arrangement, and the four memory cells serving as the basic units of the above configuration are arranged in parallel in the left-right direction and arranged in parallel in the vertical direction as well. .

  In the nonvolatile semiconductor memory device and the nonvolatile semiconductor memory device of the present invention, a nonvolatile memory can be realized by a CMOS process of standard logic, and an OTP (One Time Programmable ROM) and an MTP (Multi Time) having a one-layer polysilicon structure are realized. Programmable ROM) can be provided.

  Further, in a nonvolatile semiconductor memory element, a capacitor having a large area (a capacitor formed by a floating gate and a semiconductor substrate surface) can be compactly arranged to minimize the area. For this reason, the area of the memory cell and the memory cell array can be minimized.

1 is a configuration diagram of a nonvolatile semiconductor memory element according to a first embodiment of the present invention. FIG. 2 is a diagram for explaining the operation of the memory cell shown in FIG. 1. It is a figure which shows the characteristic of transistor T1 of the memory cell shown in FIG. It is a figure which shows the self-convergence characteristic of the threshold value by drain stress. It is a figure which shows the equivalent circuit of the coupling type | system | group of a memory cell. It is a figure which shows the structure of the non-volatile semiconductor memory device which concerns on the 2nd Embodiment of this invention. It is a figure which shows the structure of the non-volatile semiconductor memory device concerning the 3rd Embodiment of this invention. FIG. 8 is a diagram showing a configuration of a row decoder shown in FIG. 7. FIG. 9 is a diagram showing an operation table of the row decoder shown in FIG. 8. It is a figure which shows the structure of the non-volatile semiconductor memory device which concerns on the 4th Embodiment of this invention. It is a figure which shows the structure of the non-volatile semiconductor memory device which concerns on the 5th Embodiment of this invention. FIG. 12 is a diagram showing a configuration of a row decoder shown in FIG. 11. FIG. 13 is a diagram showing an operation table of the row decoder shown in FIG. 12. It is a figure which shows the structure of the non-volatile semiconductor memory device which concerns on the 6th Embodiment of this invention. It is a figure which shows the structure of the non-volatile semiconductor memory element which concerns on the 7th Embodiment of this invention. It is a figure which shows the structure of the non-volatile semiconductor memory device which concerns on the 8th Embodiment of this invention. It is a figure which shows the structure of the non-volatile semiconductor memory device which concerns on the 9th Embodiment of this invention. It is a figure which shows the structure of the non-volatile semiconductor memory device which concerns on the 10th Embodiment of this invention. It is a figure which shows the structure of the non-volatile semiconductor memory device which concerns on the 11th Embodiment of this invention. It is a figure which shows the structure of the non-volatile semiconductor memory device based on the 12th Embodiment of this invention. It is a figure which shows the structure of the non-volatile semiconductor memory element which concerns on the 13th Embodiment of this invention. FIG. 22 is a diagram for explaining the operation of the memory cell shown in FIG. 21. It is a figure which shows the structure of the non-volatile semiconductor memory device which concerns on the 14th Embodiment of this invention. It is a figure which shows the structure of the non-volatile semiconductor memory device based on 15th Embodiment of this invention. FIG. 24 is a diagram showing an operation table of the memory cell array shown in FIG. 23.

Embodiments of the present invention will be described below with reference to the accompanying drawings.
[First Embodiment]
FIG. 1 is a configuration diagram of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. In the following description, the “nonvolatile semiconductor memory element” may be simply referred to as “memory cell”.

  FIG. 1A shows a plan view of a memory cell. 1B is an equivalent circuit diagram, FIG. 1C is a cross-sectional view along AA ′ in FIG. 1A, and FIG. 1D is a cross-sectional view along BB ′. Indicates.

  As shown in the equivalent circuit of FIG. 1B, this memory cell includes a transistor T1 and a capacitor C1, and has a drain D, a source S, a control gate CG, and a floating gate FG. C1 is a capacitor between the control gate CG and the floating gate FG.

Structurally, in FIGS. 1A to 1D, 1 is a p-type semiconductor substrate, 2 is an n-type well (hereinafter n-well) formed on the p-type semiconductor substrate 1, and 3 is a transistor formation portion. Reference numeral 4 denotes a channel forming portion (gate region portion) of the floating gate transistor constituting the transistor T1, 5 denotes an n-type diffusion layer of the transistor T1, 6 denotes an n-type diffusion layer serving as a source of the transistor T1, and 9 denotes a transistor T1. A polysilicon layer serving as a floating gate serves as one end of the capacitor C1. 10 is a contact connecting the diffusion layer 5 and the metal wiring 12, 11 is a contact connecting the diffusion layer 6 and the metal wiring 13, 12 is a metal wiring for drawing out the drain D of the transistor T1, and 13 is a source S of the transistor T1. Metal wiring for drawing out, 14 is a capacitor C1, and 15 is a p-type diffusion layer, which is the other end of the capacitor C1.
16 is a contact connecting the p-type diffusion layer 15 and the control gate wiring 19, 17 is an n-type diffusion layer formed on the n-type well 2, and 18 is a contact connecting the n-type diffusion layer 17 and the control gate wiring 19. , 19 is a metal wiring to be a control gate wiring, and 20 is an insulating oxide film for isolation.

  As shown in the figure, this memory cell is characterized in that the transistor forming portion 3 including the n-type diffusion layer 5 of the transistor T1 and the n-type diffusion layer 6 serving as the source of the transistor T1 is vertically arranged (vertical direction in the drawing). ). In addition, the metal wiring 12 serving as the bit line, which is the drain of the memory cell, is also arranged in the vertical direction, and the metal wiring serving as the control gate wiring 19 is arranged in the horizontal direction (left-right direction in the drawing). The capacitor C1 (comprising 2, 9, 14, 15, 16, etc.) is compactly arranged to minimize the area of the memory cell.

  FIG. 2 is a diagram for explaining the operation of the memory cell shown in FIG. The operation will be described below with reference to FIG.

  As an operation, there are a case where it is used as an OTP and a case where it is used as an MTP in which writing and erasing can be performed a plurality of times.

  FIG. 2A shows an operation table when operating as an OTP. Hereinafter, the case of operating as an OTP will be described with reference to FIG.

  In writing in the case of the OTP operation, electrons are injected into the floating gate by hot electron injection.

  In this case, 6V is applied to the control gate CG, 5V is applied to the drain D, and 0V is applied to the source S. Since a high voltage is applied to the drain and gate and the operation is performed in a saturation region described later, a high electric field is applied to the depletion layer in the vicinity of the drain, hot electrons are generated, and this is injected into the floating gate. Since electrons are injected, the threshold value of the floating gate transistor T1 is apparently increased.

  Here, the write voltage is set to 6V for the control gate CG and 5V for the drain D (CG = 6V, D = 5V). However, since hot electrons are generated, the operation may be performed in the saturation region. So this voltage is not specified. For example, the control gate CG may be 5V, the drain D may be 5V (CG = D = 5V), and even if the drain D voltage is higher than the control gate CG, there is no problem in operation.

  Next, when 3V is applied to the control gate CG, 1V is applied to the drain D, and 0V is applied to the source S, the initial threshold is about 1V. Therefore, the transistor T1 is turned on (logic “1”) when writing is not performed. Since the threshold voltage is apparently about 5 V when electrons are injected, the data is stored in the off state (logic “0”).

  FIG. 2B shows an operation table when operating as an MTP. Hereinafter, the case of operating as an MTP will be described with reference to FIG.

  Writing in the MTP operation is the same as in OTP.

In the case of erasing, it is performed in two steps of erasing 1 and erasing 2.
In the erase 1 step, the control gate CG is biased to 0V, the drain D is 8V, and the source S is open (open) or about 2V. In this state, a high electric field is applied between the drain and the floating gate, a Fowler-Nordheim tunnel current (Fauler-Nordheim: hereinafter referred to as FN tunnel current) flows, electrons are emitted from the floating gate to the drain, and apparently, The threshold appears to drop.

  Next, as the erase 2 step, the control gate CG is set to 0 or 1V, the drain D is set to 8V, and the source S is set to 0V.

  If the memory cell is over-erased, the floating gate is positively charged. Therefore, when the source is set to 0 V, an on-current flows. Here, since the drain is at a high voltage, weak hot electrons are generated and writing occurs. This is defined as weak writing (drain stress).

  FIG. 3 is a diagram showing the characteristics of the transistor T1 of the memory cell shown in FIG. 1, and shows the VCG-ID characteristics. In FIG. 3, when writing is performed in the state of the characteristic A of the initial value, the writing characteristic B is obtained.

  Next, when the erase 1 step is executed, an over-erase characteristic C is obtained. Thereafter, by executing the erase 2 step, it is possible to write back from the over-erasing characteristic C toward the state of the initial characteristic A.

  FIG. 4 shows the characteristics of weak writing. When the drain stress is applied on the horizontal axis and the threshold value is taken on the vertical axis, for example, when the gate voltage CG is set to 0 V, high energy is obtained by applying the drain stress to a small but high electric field near the drain. Hot electrons are generated, a part of which is taken into the floating gate and becomes weakly written, and finally converges to the initial state. Here, if the gate voltage CG is set to 1V, the convergence threshold level converges to a value shifted by 1V in parallel. If this characteristic is used, even if there is a cell that has been overerased by erasure 1, it can be self-converged to an arbitrary positive threshold value by erasure 2, and overerasing can be taken as a countermeasure.

FIG. 5 shows an equivalent circuit of the coupling system of this cell.
If the state of the floating gate is the initial state (neutral state), the total charge of this system is zero,
(VCG−VFG) * C (FC) + (Vsub−VFG) * C (FB) +
(VD−VFG) * C (FD) + (VS−VFG) * C (FS) = 0,
C (FC) + C (FB) + C (FD) + C (FS) = CT (total)
Then,
VFG = VCG * C (FC) / CT + Vsub * C (FB) / CT +
VD * C (FD) / CT + VS * C (FS) / CT
Here, if C (FD) = C (FS) ≈0 and Vsub = VS = 0,
VFG = VCG * C (FC) / {C (FC) + C (FB)}
Here, C (FC) / {C (FC) + C (FB)} = α (coupling ratio)
Then,
VFG = αVCG.
Normally α is set to 0.6.

  Note that the n-type diffusion layer 5 corresponds to the first n-type diffusion layer serving as the drain of the transistor, and the n-type diffusion layer 6 corresponds to the second n-type diffusion layer. The gate region portion corresponds to a region between the first n-type diffusion layer 5 and the second n-type diffusion layer 6, and the first metal wiring is the metal wiring 12, and the first metal wiring is the first metal wiring. The metal wiring 13 corresponds to the metal wiring 13.

  In addition, during charge accumulation (writing) in the floating gate, the first high voltage applied to the gate of the first transistor described above is the voltage “6” V of the control gate CG shown in FIG. The second voltage applied to the drain D corresponds to the voltage “5” V of the drain D. In the first erasing means described above, the third voltage applied to the drain D corresponds to the voltage “8” V of the drain D shown in FIG. 2B, and is applied to the source S described above. The fourth voltage corresponds to the voltage “2” V of the source S. In the second erasing means described above, the fifth voltage applied to the control gate CG corresponds to the voltage “1” V of the control gate CG shown in FIG.

  Then, a transistor forming portion 3 for forming a transistor is arranged in a first direction (vertical direction in FIG. 1) on the surface of the semiconductor substrate. The transistor forming portion 3 is arranged in order from the top with the drain of the transistor T1. A first n-type diffusion layer 5 to be formed, a gate region portion 4 for forming a channel (a region between the first diffusion layer 5 and the second diffusion layer 6), and a second n serving as a source of the transistor T1. A mold diffusion layer 6 is disposed.

  On the left side of the transistor forming portion 3, the metal wiring 12 is arranged in the vertical direction. The metal wiring 12 is arranged in parallel to the transistor formation portion 3 at a predetermined distance from the surface of the semiconductor substrate, and the metal wiring 12 is connected to the drain (first n-type diffusion layer 5) of the transistor T1 through the contact 10. Is done.

  A rectangular n-type well 2 is formed on the left side of the transistor forming portion 3 in the left-right direction with a predetermined width and depth. The rectangular floating gate 9 is disposed in the left-right direction so as to face the surface of the semiconductor substrate, the region on the left end side thereof is opposed to the surface of the n-type well 2, and the region on the right end side is the transistor T1. The gate region 4 is disposed so as to face the gate region 4 (a channel forming region intermediate between the first n-type diffusion layer 5 and the second n-type diffusion layer 6).

  On the left side of the n-type well 2, a p-type diffusion layer 15 having a predetermined width and depth is formed in the left-right direction adjacent to the left side of the region facing the floating gate 9 of the n-type well 2. . The p-type diffusion layer 15 and the control gate wiring 19 are connected by a contact 16. The control gate line 19 is disposed in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the floating gate 9, and is connected to the p-type diffusion layer 15 by a contact 16. The second metal wiring 13 is disposed in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to oppose the second n-type diffusion layer 6 serving as the source of the transistor T1, and the second metal wiring 13 13 is connected to the second n-type diffusion layer 6 by a contact 11.

  With such a configuration, a non-volatile memory can be realized by a standard logic CMOS process, and OTP or MTP can be realized. In addition, a capacitor having a large area (a capacitor formed on the surface of the floating gate and the semiconductor substrate) can be compactly arranged to minimize the area.

  In the first embodiment shown in FIG. 1, the metal wiring 12 is arranged on the left side of the transistor formation unit 3, but it can be arranged directly above or on the right side.

[Second Embodiment]
FIG. 6 is a diagram showing a configuration of a nonvolatile semiconductor memory device according to the second embodiment of the present invention. The example shown in FIG. 6 is an example in which the nonvolatile semiconductor memory element (memory cell) of the present invention is incorporated in a matrix array (memory cell array), and is an example in the case of OTP.

  In the example shown in FIG. 6, the memory array has an input / output I / O 8-bit configuration of IO-0 to IO-7, and the memory array has n bits in the column direction and m bits in the row direction. The unit memory cell blocks 100-0 to 100-7 are configured. That is, the memory cells are arranged in units of n-bit addresses in the column direction, such as M11-0 to M1n-0, M11-7 to M1n-7, and constitute memory cell blocks 100-0 to 100-7. . Note that the sources of the memory cells are all connected in common.

  Each of the row decoders 200-1 to 200-m includes an address decoder 201, an inverter 202, and a level shift circuit 203. The level shift circuit 203 converts the row selection signal output from the row decoders 200-1 to 200-n into the first signal voltage Vp1. The outputs of the level shift circuit 203 are output signals to the word lines WL1 to WLm, respectively.

  In the case of OTP, there is no need for erasing, so the word lines WL1 to WLm can be connected in common in the row direction. For example, the word line WL1 is commonly connected to all the memory cells M11-0 to M1n-0 and M11-7 to M1n-7. The same applies to the word line WLm.

  Similarly to the row decoder, the column decoders 300-1 to 300-n each include an address decoder 301, an inverter 302, and a level shift circuit 303. The level shift circuit 303 converts the column selection signal output from the column decoders 300-1 to 300-n into the second signal voltage Vp2.

  The outputs of the level shift circuit 303 are signals COL1 to COLn, which are input to the gates of the column selection transistors CG1-0 to CG1-7,... CGn-0 to CGn-7, respectively. For example, the output of the column decoder 300-1 is a gate input signal of the column selection transistors CG1-0 to CG1-7.

  Bit lines BIT1-0 to BIT1-7 connected to the drains of the memory cells are connected to data input lines D0 to D7 via column selection transistors CG1-0 to CG1-7, respectively. Similarly, bit lines BITn-0 to BITn-7 are connected to data input lines D0 to D7 through column selection transistors CGn-0 to CGn-7, respectively.

  The data input lines D0 to D7 receive the write input data Din0 to Din7, receive the data of the data conversion circuit 400 that outputs the write data (for example, the write voltage of 5 V), and the memory cell at the time of read, and send signals Sense amplifier circuits 500-0 to 500-7 that amplify and output are connected.

Next, the operation will be described.
At the time of writing, for example, when the row decoder 200-1 and the column decoder 300-1 are selected, the word line WL1 and the signal COL1 are selected, and 6V (first signal voltage Vp1) and 8V (second signal voltage), respectively. A voltage of Vp2) is applied. At this time, 5 V (third signal voltage Vp3) is output from the data conversion circuit 400 to the data input lines D0 to D7 corresponding to the write data Din0 to Din7.

  Here, it is assumed that “Din0 = Din2 = Din4 = Din6 =“ 0 ”(data is written)” and “Din1 = Din3 = Din5 = Din7 =“ 1 ”(data is not written)” are input as write data.

  In this case, “D0 = D2 = D4 = D6 = 5V” and “D1 = D3 = D5 = D7 = 0V” are output to the data input / output lines D0 to D7, and the signal COL1 is selected to be 8V. Therefore, the bit lines BIT1-0, BIT1-2, BIT1-4, BIT1-6 become 5V, the bit lines BIT1-1, BIT1-3, BIT1-5, BIT1-7 become 0V, and the memory cell M11- 0, M11-2, M11-4, and M11-6 are written, and the memory cells M11-1, M11-3, M11-5, and M11-7 are not written. In this way, arbitrary data can be written into an arbitrary memory cell.

  In reading, if the selected memory cell is in the erased state (“1”; on), a current flows through the memory cell, and if it is in the written state (“0”; off), no current flows. Then, the determination is made by the sense amplifier circuit 500, and data Dout0 to Dout7 are output.

  Thus, in the configuration of the nonvolatile semiconductor memory device shown in the second embodiment, as shown in FIG. 6, the memory cell is configured as an OTP, and this memory cell is divided into eight in the column direction. Are arranged to be composed of 8 memory cell blocks having a width of n bits.

  The drains of the transistors of each memory cell are connected in common by bit lines BIT-0 to BITn-7 along the row direction, and the control gates of the transistors of the memory cells of each row are provided by word lines WL1 to WLm provided for each row. CGs are commonly connected along the column direction. The sources of the transistors of the memory cells constituting the memory cell array are commonly connected by a source line S1, and the source line S1 is connected to GND (“0” V).

  Row decoders 200-1 to 200-m provided for each row generate an address selection signal for selecting a memory cell in response to an address signal, and convert the row selection signal into a first signal voltage Vp1 to generate a word. Apply to lines WL1-WLm.

  Column decoders 300-1 to 300-n are n column decoders provided corresponding to the number of bits n in the column direction in the memory cell block, and a column selection signal for selecting one memory cell from each memory cell block. Is output. The second level shift circuit 303 converts the column selection signal output from the column decoder into a signal of the second signal voltage Vp2 and outputs it.

  Each memory cell block is provided with a column selection transistor (CG1-0 to CGn-0,..., CG1-7 to CGn-7) in units of n bits. The column selection signal Vp2 output from the level shift circuit is used as a gate input, a bit line of one memory cell is selected for each memory cell block, and a memory cell in units of 8 bits in total is selected.

  The memory cell selected by the column selection transistor is connected to the data input / output lines D0 to D7 via the column selection transistor. Further, the data conversion circuit 400 receives the input signals Din0 to Din7 for writing data in units of 1 byte and writes data to the drains of the transistors of the memory cells through the data input / output lines D0 to D7. The signal voltage Vp3 is output. In addition, the sense amplifier circuits 500-0 to 500-7 amplify the data of the memory cells read to the data input / output lines D0 to D7 and output them to the outside.

  With such a configuration, an OTP can be configured using the nonvolatile semiconductor memory element of the present invention.

[Third Embodiment]
FIG. 7 is a diagram showing a configuration of a nonvolatile semiconductor memory device according to the third embodiment of the present invention. The example shown in FIG. 3 is an example of MTP.

  The nonvolatile semiconductor memory device shown in FIG. 7 differs from the nonvolatile semiconductor memory device shown in FIG. 6 in the configuration of the row decoders 200-1 to 200-m. Further, in order to perform erasing in units of words, the sources of the memory cells are commonly connected for each row, and the source is shared for each row by the common sources S1 to Sm. Other structures are the same as those of the nonvolatile semiconductor memory device shown in FIG. For this reason, the same code | symbol is attached | subjected to the same component.

FIG. 8 shows a configuration of row decoders 200-1 to 200-m shown in FIG.
Control signals E1 and E2 for controlling the operation mode of row decoder 200 are input to row decoder 200 shown in FIG.

  In this row decoder 200, 221 is a NAND circuit selected upon receipt of a row address, 222 is an inverter that inverts the output of the NAND circuit 221, 223 is an inverter that inverts the control signal E2, and 224 and 225 are transfer switches. 226 is an inverter, 227 is a level shift circuit, and 228 is a NOR circuit.

FIG. 9 is a diagram showing an operation table for explaining the operation of the row decoder shown in FIG.
For example, a case where the column decoder 300-1 shown in FIG. 7 is selected (that is, COL1 is selected) and the row decoder 200-1 is selected will be described. In this case, the memory cells M11-0 to M11-7 are selected.

  First, the case of writing (writing mode) will be described. In this case, in the operation table shown in FIG. 9, in the case of writing, the control signals E1 and E2 are “E1 = E2 =“ 0 ””. When the address decoder is selected, the output of the NAND circuit 221 is “0”, the output of the inverter 222 is “1”, and E2 is “0”. Therefore, the transfer switch 224 is turned on and the transfer switch 225 is turned off. The output “0” of the inverter 226 and the output of the level shift circuit 227, that is, the signal of the word line WL1 becomes the first signal voltage Vp1 (5 V).

  On the other hand, since the control signal E1 is “0”, the output signal SB1 of the NOR circuit 228 is “1”, and the source S1 of the memory cell is 0V.

  Since 5 V is applied to the drain D (D0 to D7) of the selected memory cell in this state, writing occurs in the memory cell. In the non-selected memory cell connected to the non-selected decoder 200-m, the word line WLm is 0 V and the source Sm is open (open: open), so that writing does not occur.

Next, the erase 1 step (first erase mode) will be described.
In the erase 1 step, the control signals E1 and E2 are set to “E1 = E2 =“ 1 ””. When the address decoder is selected, the NAND circuit 221 output is “0” and the control signal E2 is “1”, so that the transfer switch 224 is turned off and the transfer switch 225 is turned on, and the output of the inverter 226 is “1”. The output of the level shift circuit 227, that is, the word line WL1 becomes 0V. Since “E1 =“ 1 ””, the output of the NOR circuit 228 is always “0”, and the source line Sm is open. Since the drain D becomes 8V in this state, the memory cell is erased.

  On the other hand, for the non-selected cell connected to the non-selected row, the output of the NAND circuit 221 is “1”, so that the word line WLm is 3V, for example, and the signal to the switch transistor SBm of the source line Sm is 0V. The source line Sm is also open. Although the drain D is 8V, since the gate voltage applied to the word line WLm is as high as 3V, the electric field between the drain and the gate is relaxed and no erasure occurs. As a result, only the selected line is erased.

Next, the erase 2 step (second erase mode) will be described.
In the case of the erase 2 step, the control signals E1 and E2 are set to “E1 =“ 0 ”, E2 =“ 1 ””. Since the control signal E2 is “1”, the output of the address decoder is inverted and the word line WL1 becomes 0V. Since the control signal E1 is “0”, the NOR circuit 228 receives the output “0” of the NAND circuit 221, and the signal to the switching transistor SB1 of the source line S1 is “1” (SB1 = “1”). That is, the source line S1 becomes 0V, and the selected memory cell self-converges.

  On the other hand, the output of the non-select decoder 221 is inverted, the word line WLm is, for example, 3V, the source SBm is “0”, and the source Sm is open, and self-convergence does not occur.

  In the case of reading, since the control signals E1 and E2 are E1 = E2 = “0”, 3V is applied to the selected word line WL1 and 1V is applied to the drain D. Depending on the data of the memory cell, “1” or “0” is read.

  As described above, in the nonvolatile semiconductor memory device shown in the third embodiment, as shown in FIG. 7, the memory cell is configured as an MTP, and this memory cell is divided into eight in the column direction and n bits in the column direction. Are arranged to be composed of eight memory cell blocks having a width of

  In addition, the drains of the transistors in each memory cell are connected in common by bit lines BIT-0 to BITn-7 along the row direction, and the control gates of the transistors in the memory cells in each row are provided by word lines WL1 to WLm provided for each row. CGs are commonly connected along the column direction.

  Further, the source lines S1 to Sm provided for each row commonly connect the sources of the transistors of the memory cells in each row along the column direction. Each of the source lines is provided with switching transistors SB1 to SBm for selecting whether the source line is grounded or opened to GND (“0” V).

  Row decoders 200-1 to 200-m provided for each row generate a row selection signal for selecting a memory cell in response to an address signal, and the row decoder 200-1 to 200-m generates the row selection signal according to the write and erase modes (erase 1 and erase 2). The voltage level of the selection signal is selected and applied to the word lines WL1 to WLm, and a control signal for turning on / off the switching transistors SB1 to SBm is output.

  Column decoders 300-1 to 300-n are n column decoders provided corresponding to the number of bits n in the column direction in the memory cell block, and a column selection signal for selecting one memory cell from each memory cell block. Is output. The second level shift circuit 303 converts the column selection signal output from the column decoder into a signal of the second signal voltage Vp2 and outputs it.

  Each memory cell block is provided with a column selection transistor (CG1-0 to CGn-0,..., CG1-7 to CGn-7) in units of n bits. The column selection signal (second signal voltage Vp2) output from the level shift circuit is used as a gate input, and a bit line of one memory cell is selected for each memory cell block to select a memory cell in units of 8 bits in total. To do.

  The memory cell selected by the column selection transistor is connected to the data input / output lines D0 to D7 via the column selection transistor. In addition, when the data conversion circuit 400 receives input signals Din0 to Din7 of write data in units of 1 byte and performs data writing and data erasing, it is applied to the drains of the transistors of the memory cells through the data input / output lines D0 to D7. The third voltage signal Vp3 is output. In addition, the sense amplifier circuits 500-0 to 500-7 amplify the data of the memory cells read to the data input / output lines D0 to D7 and output them to the outside.

  With such a configuration, the MTP can be configured using the nonvolatile semiconductor memory element of the present invention.

[Fourth embodiment]
FIG. 10 is a diagram showing a configuration of a nonvolatile semiconductor memory device according to the fourth embodiment of the present invention, which is an example of MTP.

  In the fourth embodiment shown in FIG. 10, since rewriting is performed in units of 8 bits, in order to improve the layout arrangement, the memory cell array 101- is obtained by dividing the memory cell array in units of 8 bits in the column direction. 1 to 101-n. For example, the memory cell block 101-1 includes memory cells M11-0 to M11-7,..., Mm1-0 to Mm1-7, each having 8 bits in the column direction and m bits in the row direction.

  Further, in order to perform erasing in units of words, as in the nonvolatile semiconductor memory device shown in FIG. 7, the sources of the memory cells are commonly connected for each row, and the common source lines S1 to Sm are similarly shared. Is done. The row decoder is the same as the row decoder 200 shown in FIG.

  Thus, in the nonvolatile semiconductor memory device of the fourth embodiment, as shown in FIG. 10, the memory cell is configured as an MTP, and the memory cell is column-selected in units of 1 byte in the column direction for each row. The memory cell blocks are arranged in units of 8 bits.

  In addition, the drains of the transistors in each memory cell are connected in common by bit lines BIT-0 to BITn-7 along the row direction, and the control gates of the transistors in the memory cells in each row are provided by word lines WL1 to WLm provided for each row. CGs are commonly connected along the column direction.

  Further, the source lines S1 to Sm provided for each row commonly connect the sources of the transistors of the memory cells in each row along the column direction. Each of the source lines is provided with switching transistors 209-1 to 209-m for selecting whether the source line is grounded or opened to GND (“0” V).

  Row decoders 200-1 to 200-m provided for each row generate a row selection signal for selecting a memory cell in response to an address signal, and set the voltage level of the row selection signal according to a write mode and an erase mode. The control signals SB1 to SBm for turning on / off the switching transistors 209-1 to 209-m are output while being selected and applied to the word lines WL1 to WLm.

  The column decoders 300-1 to 300-n are column decoders provided for the memory cell blocks 101-1 to 101-n, and select one memory cell block in units of 8 bits in the column direction. The second level shift circuit 303 converts the column selection signal output from the column decoder into a signal of the second signal voltage Vp2 and outputs it.

  Further, column select transistors (CG1-0 to CG1-7,..., CGn-0 to CGn-7) in units of 8 bits are provided for each memory cell block. The column selection signals COL1 to COLn (second signal voltage Vp2) output from the level shift circuit are used as gate inputs to select a bit line of one memory cell block and select a memory cell in units of 8 bits.

  The bit line of the memory cell block selected by the column selection transistor is connected to the data input / output lines D0 to D7 via the column selection transistor. In addition, when the data conversion circuit 400 receives input signals Din0 to Din7 of write data in units of 1 byte and performs data writing and data erasing, it is applied to the drains of the transistors of the memory cells through the data input / output lines D0 to D7. The third voltage signal Vp3 is output. In addition, the sense amplifier circuits 500-0 to 500-7 amplify the data of the memory cells read to the data input / output lines D0 to D7 and output them to the outside.

  Thus, an MTP can be configured using the nonvolatile semiconductor memory device of the present invention, and the memory cell array is divided in the unit of 8 bits in the column direction, and data is written and read in units of 8 bits. be able to.

[Fifth Embodiment]
FIG. 11 is a diagram showing a configuration of a nonvolatile semiconductor memory device according to the fifth embodiment of the present invention. The example shown in FIG. 11 is the nonvolatile semiconductor memory device shown in FIG. 10 in which the source lines are shared by two rows. In this way, there is no useless empty area on the layout.

  A circuit of the row decoder is shown in FIG. The row decoder 200A shown in FIG. 12 adds a control signal E3B to the row decoder 200 of FIG. 8, changes the inverter 226 shown in FIG. 8 to the NAND circuit 226A, and inputs the control signal E3B.

  FIG. 13 shows an operation table of the row decoder shown in FIG. The operation table shown in FIG. 13 is different from the operation table shown in FIG. 9 in the step 2 of erasing non-selected cells. The area of interest is surrounded by a thick frame.

  In the circuit of the row decoder shown in FIG. 8, in the erase 2 step, the unselected word line WL2 is 3V and the source S is open. However, when the memory cell array shown in FIG. , 2) become common and become the signals S1 and S2 in the operation table, so that the signal SB2 is "0" and the transistor 209-2 is turned off, but since the signal SB1 is "1", the transistor 209-1 is turned on. Become.

  Therefore, when the signals S1 and S2 applied to the common source line S (1,2) are 0V and the word line WL2 is 3V, the memory cell connected to the word line WL2 is turned on. To avoid this, if the control signal E3B is provided and set to be “0” at the time of erasure 2, the output of the NAND circuit 206 becomes “1”, and the decoder output of 201 is not selected. The output signal of the level shift circuit 207 to the word line WL2 is 0V, and the current of the non-selected memory cell does not flow.

  Here, in this state, the memory cell connected to the selected word line WL1 and the non-selected memory cell connected to the adjacent word line WL2 in the erase 2 step, that is, the self-convergence operation, simultaneously The convergence voltage, that is, the drain is 5 V, the gate is 0 V, and the source is 0 V, and self-convergence occurs in the erased cell. If the memory cell connected to the word line WL2 is self-converged once in the previous state, the second self-convergence operation occurs here, so that the self-convergence is performed twice.

  However, looking at the characteristics of the self-convergence operation shown in FIG. 4, the limit of self-convergence converges to the initial value, so there is no problem even if the self-convergence operation is excessively added.

  Thus, in the nonvolatile semiconductor memory device shown in the fifth embodiment, as shown in FIG. 11, the memory cells are configured as MTP, and the memory cells are column-selected in units of 1 byte in the column direction for each row. The memory cell blocks are arranged in units of 8 bits.

  In addition, the drains of the transistors in each memory cell are connected in common by bit lines BIT-0 to BITn-7 along the row direction, and the control gates of the transistors in the memory cells in each row are provided by word lines WL1 to WLm provided for each row. CGs are commonly connected along the column direction.

  In addition, the source lines S (1,2) to S (m-1, m) provided every two rows connect the sources of the transistors of the memory cells in the two rows along the column direction. This source line receives an on / off signal (for example, signal SB1) from one row and receives the first or the first for selecting whether the source line is grounded or opened to GND (“0” V). Whether the source line is grounded or opened to GND (“0” V) in response to an on / off signal (for example, signal SB2) from the switching transistor (for example, switching transistor 209-1) and the other row A second switching transistor (for example, switching transistor 209-2) for selecting is connected in common.

  Also, the row decoders 200-1 to 200-m provided for each row generate a row selection signal for selecting the memory cell in response to the address signal, and the row selection signal of the row selection signal is selected according to the write mode and the erase mode. A voltage level is selected and applied to the word lines WL1 to WLm. The row decoders 200-1 to 200-m are paired in pairs, and one row decoder (for example, the row decoder 200-1) to the first switch transistor (for example, the switch transistor 209-). 1) A control signal (for example, signal SB1) for turning on / off is output. Further, a control signal (for example, signal SB2) for turning on / off the second switching transistor (for example, 209-2) is output from the other row decoder (for example, row decoder 200-2).

  Column decoders 300-1 to 300-n (see FIG. 10) are column decoders provided for each of the memory cell blocks 101-1 to 101-n, and select one memory cell block in units of 8 bits in the column direction. To do. The second level shift circuit 303 converts the column selection signal output from the column decoder into a signal of the second signal voltage Vp2 and outputs it.

  Further, column select transistors (CG1-0 to CG1-7,..., CGn-0 to CGn-7) in units of 8 bits are provided for each memory cell block. The column selection signal (second signal voltage Vp2) output from the level shift circuit is used as a gate input to select a bit line of a memory cell of one memory cell block and select a memory cell in units of 8 bits.

  The bit line of the memory cell block selected by the column selection transistor is connected to the data input / output lines D0 to D7 via the column selection transistor. In addition, when the data conversion circuit 400 receives input signals Din0 to Din7 of write data in units of 1 byte and performs data writing and data erasing, it is applied to the drains of the transistors of the memory cells through the data input / output lines D0 to D7. The third voltage signal Vp3 is output. In addition, the sense amplifier circuits 500-0 to 500-7 amplify the data of the memory cells read to the data input / output lines D0 to D7 and output them to the outside.

  As a result, the nonvolatile semiconductor memory element of the present invention can be used to configure the MTP, and the source lines can be shared by two rows so that a useless empty area on the layout can be eliminated.

  In the second, third, fourth, and fifth embodiments, the writing and erasing operations in byte units have been described. However, the present invention is not limited to byte units.

  For example, if a column decoder batch selection signal (not shown) is input to the column decoder 300 and the column decoders 300-1 to 300-n are set to be simultaneously selected, memory cells connected to one word line, for example, All of M11-0 to M1n-7 (n × 8) can be written or erased simultaneously. As a result, so-called page-by-page writing and erasing can be performed.

The configuration of the memory array (memory cell block) is arranged in units of column addresses (n bits) in the examples shown in FIGS. 6 and 7, but in the examples shown in FIGS. / O The number of bits is set in units (here, in bytes).
Which method is adopted is determined in consideration of layout arrangement.

  Furthermore, in the examples shown in FIGS. 10 and 11, the input / output I / O unit is a byte unit (8 bits), but this is a word unit (16 bits) or a double word unit (32 bits), or Even if it is configured with more I / O bits, the gist and effect are the same.

[Sixth Embodiment]
FIG. 14 is a diagram showing a configuration of a nonvolatile semiconductor memory device according to the sixth embodiment of the present invention. The example shown in FIG. 14 shows an example of the layout arrangement of the OTP memory cell shown in FIG. That is, the memory cells shown in FIG. 1 are arranged in an array.

  In FIG. 14, word lines (control gates) WL1, WL2, WL3,... Are passed through the metal wiring in the left-right direction (horizontal direction), source lines S1, S2 are passed in the left-right direction, and bit lines BIT1, BIT2 are passed. , BIT3... Are passed in the vertical direction (longitudinal direction) on the drawing, the nonvolatile semiconductor memory (memory cells) shown in FIG. 1 are arranged symmetrically in the vertical and horizontal directions, and the n-well is common to each other. The area is being reduced. In this way, useless empty space is eliminated and the arrangement is efficient. The arrangement is optimal both in terms of characteristics and area. This layout can also be applied to the common source nonvolatile semiconductor memory device shown in FIG.

  Thus, in the nonvolatile semiconductor memory device shown in the sixth embodiment, the nonvolatile semiconductor memory element (memory cell) of the present invention shown in FIG. 1 is used as an OTP as a memory cell.

  The memory cells arranged in this layout will be described with a focus on, for example, a memory cell in a portion A surrounded by a broken line in FIG. 14 (a memory cell selected by the word line WL1 and the bit line BIT2). The transistor forming portion 3 arranged in the vertical direction on the top includes a first n-type diffusion layer 5 serving as a drain of the transistor and a gate region portion (first n-type diffusion layer 5 and the first n-type forming a channel of the transistor). 2 and an n-type diffusion layer 6 in the middle) and a second n-type diffusion layer 6 serving as a source of the transistor.

  On the left side of the transistor formation portion 3, the first metal wiring 12 is arranged in the vertical direction. The metal wiring 12 is arranged in parallel to the transistor forming portion 3 at a predetermined distance from the surface of the semiconductor substrate, and the metal wiring 12 is connected to the drain of the transistor (first n-type diffusion layer 5) through a contact. . The first metal wiring 12 is connected to the bit line BIT2.

  A square n-type well 2 is formed on the left side of the transistor forming portion 3 in the left-right direction with a predetermined width and depth. The rectangular floating gate 9 is arranged in the left-right direction so as to face the surface of the semiconductor substrate, the region on the left end side thereof faces the surface of the n-type well 2, and the region on the right end side is a gate region portion. The first n-type diffusion layer 5 and the second n-type diffusion layer 6 are disposed so as to face each other.

  On the left side of the n-type well 2, a p-type diffusion layer 15 having a predetermined width and depth is formed in the left-right direction adjacent to the left side of the region facing the floating gate 9 of the n-type well 2. . The p-type diffusion layer 15 and the control gate wiring 19 are connected by a contact. The control gate line 19 is arranged in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the floating gate 9, and is connected to the p-type diffusion layer 15 by a contact. The control gate line 19 is connected to the common word line WL1.

  The second metal wiring 13 is disposed in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to oppose the second n-type diffusion layer 6 serving as the source of the transistor T1, and the second metal wiring 13 13 is connected to the second n-type diffusion layer 6 by a contact. The second metal wiring 13 is connected to the common source line S1.

  In each memory cell arrangement, a second n-type well 2 is shared between two memory cells arranged symmetrically on the left and right, and two memory cells arranged symmetrically on the left and right. Four memory cells serving as the basic unit of this configuration, with a total of four memory cells including two memory cells arranged symmetrically in the downward direction with the metal wiring 13 (source line S1) in common with each other. Are arranged side by side in parallel in the left-right direction, and are also arranged in parallel in the up-down direction.

  As a result, an OTP can be configured using the nonvolatile semiconductor memory element of the present invention, and a useless empty area can be eliminated on the layout.

  In the sixth embodiment shown in FIG. 14, in the memory cell (the memory cell selected by the bit line BIT2 and the word line WL1), the metal wiring 12 is arranged on the left side of the transistor formation unit 3. The same applies to the arrangement on the right side, and may also be arranged directly above. However, in this example, when the memory cell is arranged on the right side, the memory cell size is determined by the interval between the metal wirings 12, so that the memory cell size may be somewhat increased.

[Seventh Embodiment]
FIG. 15 is a diagram showing a configuration of a nonvolatile semiconductor memory device according to the seventh embodiment of the present invention. In the memory cell of the first embodiment shown in FIG. 1, the n-well is omitted, and an area reduction effect is further obtained.

  FIG. 15A is a plan view, and FIG. 15B is a cross-sectional view along B-B ′. The memory cell shown in FIG. 15 is structurally different from the memory cell shown in FIG. 1 except that the n-well (n-type well) 2 shown in FIG. 1A is omitted and the memory cell shown in FIG. The D-type (depletion-type) channel implanter 21 is provided, and the p-type diffusion layer 15 is changed to an n-type diffusion layer 15 ′. That is, in the transistor formation portion 3 shown in FIG. 1, the first n-type diffusion layer 5 that becomes the drain of the transistor T1 and the gate region portion (the first diffusion layer 5 and the second diffusion region) that forms the channel of the transistor. The middle region of the layer 6) and the arrangement of the second n-type diffusion layer 6 are the same, and the same applies to the metal wirings 12, 13 and the control gate wiring. The same applies to the equivalent circuit shown in FIG. For this reason, the same code | symbol is attached | subjected to the same component and the overlapping description is abbreviate | omitted.

  As described above, in the memory cell shown in the seventh embodiment, since the n-well is omitted, a D-type (depletion-type) channel implant 21 is provided under the gate of the capacitor 14 so that the coupling is efficiently performed. Can be done. D-type channel implantation is required for the standard CMOS process, but since the implantation process is added, the total number of processes can be increased slightly, so that the process is not burdened.

  In the seventh embodiment, the n-type diffusion layer 5 is the first n-type diffusion layer serving as the drain of the transistor, and the n-type diffusion layer 6 is the second n-type diffusion layer. Each of the n-type diffusion layers 3 corresponds to an n-type diffusion layer 15 ′. The first metal wiring corresponds to the metal wiring 12, and the second metal wiring corresponds to the metal wiring 13.

  Then, the transistor forming portion 3 is arranged in a first direction (vertical direction in the drawing) on the surface of the semiconductor substrate, and the transistor forming portion 3 is a first n serving as the drain of the transistor T1 in order from the top. Type diffusion layer 5, a gate region (a region between the first diffusion layer 5 and the second diffusion layer 6) that forms the channel of the transistor T 1, and a second n-type diffusion layer that becomes the source of the transistor T 1 6 are arranged.

  On the left side of the transistor forming portion 3, the metal wiring 12 is arranged in the vertical direction. The metal wiring 12 is arranged in parallel to the transistor forming portion 3 at a predetermined distance from the surface of the semiconductor substrate, and the metal wiring 12 is connected to the drain of the transistor (first n-type diffusion layer 5) through a contact. .

  In addition, a square-shaped D-type channel implanter 21 is formed on the left side of the transistor formation portion 3 in the left-right direction with a predetermined width and depth. The rectangular floating gate 9 is disposed in the left-right direction so as to face the surface of the semiconductor substrate, the region on the left end side thereof faces the surface of the channel implanter 21, and the region on the right end side is a gate region portion ( The first n-type diffusion layer 5 and the second n-type diffusion layer 6 are disposed so as to face each other).

  On the left side of the channel implanter 21, an n-type diffusion layer 15 ′ is formed in the left-right direction adjacent to the channel implanter 21, and the n-type diffusion layer 15 ′ and the control gate wiring 19 are connected by a contact. The control gate line 19 is disposed in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the floating gate 9, and is connected to the n-type diffusion layer 15 ′ by the contact 16. The second metal wiring 13 is arranged in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the second n-type diffusion layer 6 that becomes the source of the transistor T1, and the metal wiring 13 is a contact. 11 is connected to the second n-type diffusion layer 6.

  With such a configuration, a non-volatile memory can be realized by a standard logic CMOS process, and OTP or MTP can be realized. In addition, a capacitor having a large area (a capacitor formed on the surface of the floating gate and the semiconductor substrate) can be compactly arranged to minimize the area. Furthermore, n-well can be omitted from the memory cell shown in FIG.

  In the seventh embodiment shown in FIG. 15, the metal wiring 12 is arranged on the left side of the transistor formation portion 30, but it can be arranged on the right side or can be arranged directly above. .

[Eighth Embodiment]
FIG. 16 is a diagram showing a configuration of a nonvolatile semiconductor memory device according to the eighth embodiment of the present invention. The nonvolatile semiconductor memory device shown in FIG. 16 has the nonvolatile semiconductor memory elements (memory cells) shown in FIG. 15 arranged on an array.

  Similarly to the nonvolatile semiconductor memory device shown in FIG. 14, the memory cells are arranged symmetrically in the vertical and horizontal directions, and the area is reduced by omitting the n-well.

  As described above, in the nonvolatile semiconductor memory device shown in the eighth embodiment, the memory cell is selected by, for example, the memory cell in the portion A surrounded by the broken line in FIG. 16 (the word line WL1 and the bit line BIT2). In view of the memory cell), in the transistor forming portion 3 arranged in the vertical direction in the figure, the first n-type diffusion layer 5 that becomes the drain of the transistor and the gate region portion that forms the channel of the transistor (An intermediate region between the first n-type diffusion layer 5 and the second n-type diffusion layer 6) and the second n-type diffusion layer 6 serving as the source of the transistor are included.

  On the left side of the transistor formation portion 3, the first metal wiring 12 is arranged in parallel to the transistor formation portion 3 and at a predetermined distance from the surface of the semiconductor substrate. The first metal wiring 12 is connected to the bit line BIT2.

  In addition, on the semiconductor substrate, a D-type (depletion-type) channel implanter (see channel implanter 21 in FIG. 15B) (not shown) is provided on the left side of the transistor forming portion 3 with a predetermined width and depth. Is formed in the left-right direction.

  The floating gate 9 is arranged in the left-right direction so as to face the surface of the semiconductor substrate, the region on the left end side faces the surface of the channel implanter, and the region on the right end side is the gate region of the transistor formation portion 3. It arrange | positions so that a part (intermediate area | region of the 1st n type diffused layer 5 and the 2nd n type diffused layer 6) may be opposed.

  On the left side of the channel implanter, an n-type diffusion layer 15 'is provided adjacent to the channel implanter. Further, the control gate line 19 is arranged in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the floating gate 9. The control gate line 19 is connected to the word line WL1. Further, the second metal wiring 13 is arranged in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the second n-type diffusion layer 6, and the second metal wiring 13 is The second n-type diffusion layer 6 is connected by a contact. The second metal wiring 13 is connected to the source line S1.

  Then, in the arrangement of the memory cell array, two memory cells are arranged symmetrically so as to share the n-type diffusion layer 15 ′ (the left memory cell in the figure), and the two memories arranged symmetrically on the left and right Two memory cells are arranged symmetrically in the vertical direction so as to share the source line S1 with respect to the cells (lower two memory cells in the figure), and these four memory cells are used as a basic unit. The memory cell array is arranged in the left-right direction. The memory cell arrays arranged in the left-right direction are also arranged in parallel in the up-down direction.

  With such a configuration, the memory cells can be efficiently arranged and the arrangement area of the memory cell array can be reduced in the layout in which the source lines are shared by the memory cells in two rows.

  In the eighth embodiment shown in FIG. 16, in the memory cell (the memory cell selected by the bit line BIT2 and the word line WL1), the metal wiring 12 is arranged on the left side of the transistor formation unit 3. The same applies to the arrangement on the right side, and may also be arranged directly above. However, in this example, when the memory cell is arranged on the right side, the memory cell size is determined by the interval between the metal wirings 12, so that the memory cell size may be somewhat increased.

[Ninth Embodiment]
FIG. 17 is a diagram showing a configuration of a nonvolatile semiconductor memory device according to the ninth embodiment of the present invention. In contrast to the shape of the floating gate in FIG. 17, the width of the capacitor portion is made wider than the width of the transistor channel portion, the useless space is reduced, and the area is further reduced.

  That is, for example, the memory cells arranged in this layout will be described by focusing on the memory cells in the portion A surrounded by the broken line in FIG. 17 (memory cells selected by the word line WL1 and the bit line BIT2). The transistor forming portion 3 arranged in the vertical direction on the top includes a first n-type diffusion layer 5 serving as a drain of the transistor and a gate region portion (first n-type diffusion layer 5 and the first n-type forming a channel of the transistor). 2 and an n-type diffusion layer 6 in the middle) and a second n-type diffusion layer 6 serving as a source of the transistor.

  On the left side of the transistor formation portion 3, the first metal wiring 12 is arranged in parallel to the transistor formation portion 3 and at a predetermined distance from the surface of the semiconductor substrate. The first metal wiring 12 is connected to the bit line BIT2.

  In addition, on the semiconductor substrate, a D-type (depletion-type) channel implanter (see channel implanter 21 in FIG. 15B) (not shown) is provided on the left side of the transistor forming portion 3 with a predetermined width and depth. Is formed in the left-right direction.

  The floating gate 9 is arranged in the left-right direction so as to face the surface of the semiconductor substrate, the region on the left end side faces the surface of the channel implanter, and the region on the right end side is the gate region of the transistor formation portion 3. It arrange | positions so that a part (intermediate area | region of the 1st n type diffused layer 5 and the 2nd n type diffused layer 6) may be opposed. The floating gate 9 is provided with a square area expanding portion 9A in the left end region, and the area expanding portion 9A is configured to increase the capacitance of the capacitor.

  On the left side of the channel implanter, an n-type diffusion layer 15 'is provided adjacent to the channel implanter. Further, the control gate line 19 is arranged in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the floating gate 9. The control gate line 19 is connected to the word line WL1. Further, the second metal wiring 13 is arranged in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the second n-type diffusion layer 6, and the second metal wiring 13 is The second n-type diffusion layer 6 is connected by a contact. The second metal wiring 13 is connected to the source line S1.

  Then, in the arrangement of the memory cell array, two memory cells are arranged symmetrically so as to share the n-type diffusion layer 15 ′ (the left memory cell in the figure), and the two memories arranged symmetrically on the left and right Two memory cells are arranged symmetrically in the vertical direction so as to share the source line S1 with respect to the cells (the two lower memory cells in the figure), and these four memory cells are basically configured. As a unit, the memory cell array is arranged in the left-right direction. The memory cell arrays arranged in the left-right direction are also arranged in parallel in the up-down direction.

  With such a configuration, the memory cells can be efficiently arranged and the arrangement area of the memory cell array can be reduced in the layout in which the source lines are shared by the memory cells in two rows.

  In the ninth embodiment shown in FIG. 17, in the memory cell (the memory cell selected by the bit line BIT2 and the word line WL1), the metal wiring 12 is arranged on the left side of the transistor formation unit 3. The same applies to the arrangement on the right side, and may also be arranged directly above. However, in this example, when the memory cell is arranged on the right side, the memory cell size is determined by the interval between the metal wirings 12, so that the memory cell size may be somewhat increased.

[Tenth embodiment]
FIG. 18 is a diagram showing a configuration of a nonvolatile semiconductor memory device according to the tenth embodiment of the present invention. 7 is a layout arrangement example corresponding to the circuit configuration of the nonvolatile semiconductor memory device shown in FIG. 7 and the circuit configuration of the nonvolatile semiconductor memory device shown in FIG. 10, for example, the source line S1 is arranged corresponding to the word line WL1. Similarly, source lines S2, S3 and S4 are arranged corresponding to word lines WL2, WL2 and WL4. That is, the layout is when the source line is independent for each word line.

  The memory cells arranged in this layout will be described by focusing on the memory cell in the portion A surrounded by the broken line in FIG. 18 (memory cell selected by the word line WL3 and the bit line BIT2). The transistor forming portion 3 arranged in the vertical direction includes a first n-type diffusion layer 5 serving as a drain of the transistor and a gate region portion (the first n-type diffusion layer 5 and the second n-type forming a channel of the transistor). An intermediate region between the n-type diffusion layer 6 and the second n-type diffusion layer 6 serving as the source of the transistor is disposed.

  On the left side of the transistor formation portion 3, the first metal wiring 12 is arranged in parallel to the transistor formation portion 3 and at a predetermined distance from the surface of the semiconductor substrate. The first metal wiring 12 is connected to the bit line BIT2.

  In addition, on the semiconductor substrate, a D-type (depletion-type) channel implanter (see channel implanter 21 in FIG. 15B) (not shown) is provided on the left side of the transistor forming portion 3 with a predetermined width and depth. Is formed in the left-right direction.

  The floating gate 9 is disposed in the left-right direction so as to face the surface of the semiconductor substrate, the region on the left end side faces the surface of the channel implanter, and the region on the right end side is the gate region portion of the transistor formation portion 3 ( The first n-type diffusion layer 5 and the second n-type diffusion layer 6 are disposed so as to face each other. The floating gate 9 is provided with a square area expanding portion 9A in the left end region, and the area expanding portion 9A is configured to increase the capacitance of the capacitor.

  On the left side of the channel implanter, an n-type diffusion layer 15 'is provided adjacent to the channel implanter. Further, the control gate line 19 is arranged in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the floating gate 9. The control gate line 19 is connected to the word line WL3. Further, the second metal wiring 13 is arranged in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the second n-type diffusion layer 6, and the second metal wiring 13 is The second n-type diffusion layer 6 is connected by a contact.

  Then, in the arrangement of the memory cell array, two memory cells are arranged symmetrically so as to share the n-type diffusion layer 15 ′ (the left memory cell in the figure), and the two memories arranged symmetrically on the left and right Two memory cells are arranged symmetrically in the vertical direction with respect to the cells (the upper memory cell in the figure), and these four memory cells are arranged as a memory cell array in the left-right direction. Then, the memory cell arrays arranged in the left-right direction are arranged in parallel in the up-down direction.

  With such a configuration, in the layout in which the source line is independent for each word line, the memory cells can be efficiently arranged and the arrangement area of the memory cell array can be reduced.

  In the tenth embodiment shown in FIG. 18, in the memory cell (the memory cell selected by the bit line BIT2 and the word line WL3), the metal wiring 12 is arranged on the left side of the transistor formation unit 3. The same applies to the arrangement on the right side, and may also be arranged directly above. However, in this example, when the memory cell is arranged on the right side, the memory cell size is determined by the interval between the metal wirings 12, so that the memory cell size may be somewhat increased.

  [Eleventh embodiment]

FIG. 19 is a diagram showing a configuration of a nonvolatile semiconductor memory device according to the eleventh embodiment of the present invention. The nonvolatile semiconductor memory device shown in the figure is a modified example of the nonvolatile semiconductor memory device of the second embodiment shown in FIG.
The nonvolatile semiconductor memory device shown in FIG. 19 is different in configuration from the nonvolatile semiconductor memory device shown in FIG. 6 in that the configuration of the memory cell block is different. That is, in the example shown in FIG. 6, the memory array is divided into eight in the column direction according to the number of I / O bits (8 bits in the example in the figure), and the memory cell block is in n-bit units (address units) in the column direction. 100-0 to 100-7 are configured. On the other hand, in the eleventh embodiment shown in FIG. 19, the memory cell array is divided in the column direction in units of the number of I / O bits (8 bits in the example in the figure). That is, since the memory cell array is rewritten in units of 8 bits, the memory cell block is divided in units of 8 bits (I / O units) in the column direction in order to improve the layout arrangement. 101-1 to 101-n. For example, the memory cell block 101-1 includes memory cells M11-0 to M11-7,..., Mm1-0 to Mm1-7, each having 8 bits in the column direction and m bits in the row direction.

  Thus, in the nonvolatile semiconductor memory device of the eleventh embodiment, the memory cell is configured as an MTP, and the memory cell is column-selected in units of 1 byte (I / O bit number) in the column direction for each row. The memory cell block is arranged.

  The drains of the transistors in each memory cell are connected in common by bit lines BIT1-0 to BITn-7 along the row direction, and the control gates of the transistors in the memory cells in each row are provided by word lines WL1 to WLm provided for each row. CGs are commonly connected along the column direction.

  Further, the sources of the transistors of the memory cells in each row are commonly connected by the source line S1. The source line S1 is grounded to GND (“0” V).

  Row decoders 200-1 to 200-m provided for each row generate a row selection signal for selecting a memory cell in response to an address signal, and set the voltage level of the row selection signal according to a write mode and an erase mode. Select and apply to word lines WL1-WLm.

  The column decoders 300-1 to 300-n are column decoders provided for the memory cell blocks 101-1 to 101-n, and select one memory cell block in units of 8 bits in the column direction. The second level shift circuit 303 converts the column selection signal output from the column decoder into a signal of the second signal voltage Vp2 and outputs it.

  Further, column select transistors (CG1-0 to CG1-7,..., CGn-0 to CGn-7) in units of 8 bits are provided for each memory cell block. A column selection signal (second signal voltage Vp2) output from the level shift circuit is used as a gate input to select a bit line of one memory cell block and select a memory cell in units of 8 bits.

  The bit line of the memory cell block selected by the column selection transistor is connected to the data input / output lines D0 to D7 via the column selection transistor. In addition, when the data conversion circuit 400 receives input signals Din0 to Din7 of write data in units of 1 byte and performs data writing and data erasing, it is applied to the drains of the transistors of the memory cells through the data input / output lines D0 to D7. The third voltage signal Vp3 is output. In addition, the sense amplifier circuits 500-0 to 500-7 amplify the data of the memory cells read to the data input / output lines D0 to D7 and output them to the outside.

  Thus, an MTP can be configured using the nonvolatile semiconductor memory device of the present invention, and the memory cell array is divided in the unit of 8 bits in the column direction, and data is written and read in units of 8 bits. be able to.

  In the example shown in FIG. 19, the example in which the memory cell array is divided into n pieces in units of 8 bits in the column direction has been described. However, the present invention is not limited to this. (16-bit cell) or any number of bits such as a double word (32-bit cell) can be used.

[Twelfth embodiment]
FIG. 20 is a diagram showing a configuration of a nonvolatile semiconductor memory device according to the twelfth embodiment of the present invention. The nonvolatile semiconductor memory device shown in the figure is a modified example of the nonvolatile semiconductor memory device of the fifth embodiment shown in FIG.

  The non-volatile semiconductor memory device shown in FIG. 20 differs from the non-volatile semiconductor memory device shown in FIG. 11 in the configuration of the memory cell block. That is, in the example shown in FIG. 11, the memory cell array is divided into units of the number of I / O bits (8 bits) in the column direction to constitute a memory cell block. On the other hand, in the example shown in FIG. 20, the memory array is divided into 8 according to the number of I / O bits in the column direction (8 bits in the example in the figure), and the memory in units of n bits in the column direction and m bits in the row direction. The cell blocks 100-0 to 100-7 are configured. That is, the memory cells M11-0 to M1n-0,..., M11-7 to M1n-7 are grouped in n-bit address units in the column direction to form memory cell blocks 100-0 to 100-. Configure up to 7.

  The column decoders 300-1 to 300-n are n column decoders provided to face the address width n bits of the memory cell blocks 100-0 to 100-7. Each of the column decoders 300-1 to 300-n includes an address decoder 301, an inverter 302, and a level shift circuit 303. The level shift circuit 303 converts the column selection signal output from the column decoders 300-1 to 300-n into the second signal voltage Vp2.

  Column selection transistors CG1-0 to CGn-0,... CG1-7 to CGn-7 are n-bit unit column selection transistors provided for each of the memory cell blocks, and are used for the second level shift. A second signal voltage Vp2 (signals COL1 to COLn) output from the circuit is used as a gate input, a bit line of one memory cell is selected from each memory cell block, and a total of 8 bits (number of I / O bits) memory Select the bit line of the cell.

  The configuration of the row decoders 200-1 to 200-m is the same as that of the row decoder shown in FIG. In addition, the connection method of the bit lines BIT1-0 to BITn-7, the connection method of the word lines WL1 to WLm, the source lines S (1,2) to S (m-1, m), the switching transistor 209 in the memory cell block. -1, 209-2 to 209- (m-1), 209-m are connected in the same manner as the circuit shown in FIG.

  That is, the drains of the transistors in each memory cell are connected in common by bit lines BIT1-0 to BITn-7 along the row direction, and the control gates of the transistors in the memory cells in each row are provided by word lines WL1 to WLm provided for each row. CGs are commonly connected along the column direction.

  Further, the source lines S (1,2) to S (m-1, m) provided for every two rows connect the sources of the transistors of the memory cells in the two rows in common along the column direction. . This source line receives an on / off signal (for example, signal SB1) from one row and receives the first or the first for selecting whether the source line is grounded or opened to GND (“0” V). Whether the source line is grounded or opened to GND (“0” V) in response to an on / off signal (for example, signal SB2) from the switching transistor (for example, switching transistor 209-1) and the other row A second switching transistor (for example, switching transistor 209-2) for selecting is connected in common.

In addition, the row decoders 200-1 to 200-m provided for each row generate a row selection signal for selecting a memory cell in response to an address signal, and the voltage of the row selection signal depends on the write mode and the erase mode. A level is selected and applied to the word lines WL1 to WLm. The row decoders 200-1 to 200-m are paired in pairs, and one row decoder (for example, the row decoder 200-1) to the first switch transistor (for example, the switch transistor 209-). 1) A control signal (for example, signal SB1) for turning on / off is output.
Further, a control signal (for example, signal SB2) for turning on / off the second switching transistor (for example, 209-2) is output from the other row decoder (for example, row decoder 200-2).

  In addition, a total of eight bit lines of the memory cell block selected by the column selection transistors CG1-0 to CGn-0,... CG1-7 to CGn-7 are connected to the data input through the column selection transistors. Connected to output lines D0 to D7. In addition, when the data conversion circuit 400 receives input signals Din0 to Din7 of write data in units of 1 byte and performs data writing and data erasing, it is applied to the drains of the transistors of the memory cells through the data input / output lines D0 to D7. The third voltage signal Vp3 is output. In addition, the sense amplifier circuits 500-0 to 500-7 amplify the data of the memory cells read to the data input / output lines D0 to D7 and output them to the outside.

  As described above, in the nonvolatile semiconductor memory device shown in the twelfth embodiment, the memory cells are configured as MTP, and the memory cell block is configured by grouping n-bit address units in the column direction. Lines are shared by two lines so that useless empty areas are eliminated on the layout.

[Thirteenth embodiment]
FIG. 21 is a diagram showing a configuration of a nonvolatile semiconductor memory device (memory cell) according to the thirteenth embodiment of the present invention. The memory cell shown in FIG. 21 differs from the memory cell shown in FIG. 1 in that the n-type diffusion layer 17 and the contact 18 connected to the control gate CG (19) shown in FIG. An n-type diffusion layer 23 for connecting to the n-type well 2, a metal wiring 25 for applying a desired voltage CGWell to the n-type well 2, and a contact 24 for connecting the n-type diffusion layer 23 and the metal wiring 25 are newly provided. That is. The n-type diffusion layer 23, the contact 24, and the metal wiring 25 can be arranged in an empty space of the memory cell, and the area of the memory cell is not increased, and the n-type diffusion layer 17 and the contact 18 shown in FIG. The area reduction effect by deleting is large.

  FIG. 21A shows a plan view of a memory cell according to the thirteenth embodiment. 21B is an equivalent circuit diagram, FIG. 21C is a cross-sectional view along AA ′ in FIG. 21A, and FIG. 21D is a cross-section along BB ′. FIG. 21 (E) shows a cross-sectional view along EE ′.

  As shown in the equivalent circuit of FIG. 21B, this memory cell includes a transistor T1 and a capacitor C1, and has a drain D, a source S, a control gate CG, and a floating gate FG. The capacitor C1 is a capacitor between the control gate CG and the floating gate FG.

  Structurally, in FIGS. 1A to 1E, 1 is a p-type semiconductor substrate, 2 is an n-type well (n-well) formed on the p-type semiconductor substrate 1, and 3 is a transistor formation portion. 4 is a channel forming portion (gate region portion) of the floating gate type transistor constituting the transistor T1, 5 is an n-type diffusion layer serving as a drain of the transistor T1, 6 is an n-type diffusion layer serving as a source of the transistor T1, and 9 is a transistor A polysilicon layer serving as a floating gate of T1 serves as one end of the capacitor C1. 10 is a contact connecting the n-type diffusion layer 5 and the metal wiring 12, 11 is a contact connecting the n-type diffusion layer 6 and the metal wiring 13, 12 is a metal wiring for drawing out the drain D of the transistor T1, and 13 is a transistor T1. A metal wiring for extracting the source S, 14 is a capacitor C1, and 15 is a p-type diffusion layer, which is the other end of the capacitor C1.

  16 is a contact for connecting the p-type diffusion layer 15 and the control gate wiring 19, 23 is an n-type diffusion layer formed on the n-type well 2, and 24 is for supplying a voltage to the n-type diffusion layer 23 and the n-type well 2. A contact connecting the metal wiring 25. Reference numeral 19 denotes a metal wiring serving as a control gate wiring, and 20 denotes an isolation insulating oxide film.

  FIG. 22 is a diagram for explaining the operation of the memory cell shown in FIG. Hereinafter, the operation will be described with reference to FIG.

FIG. 22A shows the case of OTP, and FIG. 22B shows the case of MTP.
The operation table shown in FIG. 22A is the same as the operation table shown in FIG. 2A, and the operation table shown in FIG. 22B is the same as the operation table shown in FIG. The only difference is that a voltage CGWell to be applied to the n-type well 2 is added through the metal wiring 25. For this reason, a duplicate description is omitted, and only the voltage CGWell will be described.

  As shown in FIG. 22, the voltage CGWell applied to the metal wiring 25 is always set to a high voltage so that the diode formed by the n-type well 2 and the n-type diffusion layer 23 is not forward-biased. Put. For example, when the voltage of CGWell25 is higher than the voltage of the control gate CG19 (on the p-type diffusion layer side of the capacitor 14), the back bias is applied to the inversion layer of the capacitor 14, so the threshold value becomes more negative and the efficiency is somewhat higher. It gets worse, but it's small and not a big problem.

  In the thirteenth embodiment shown in FIG. 21, the metal wiring 12 is arranged on the left side of the transistor forming section 3, but it can also be arranged on the right side.

  In the nonvolatile semiconductor memory element according to the thirteenth embodiment shown in FIG. 21, the n-type diffusion layer 5 is the first n-type diffusion layer serving as the drain of the transistor, and the second n-type diffusion is the same. The n-type diffusion layer 6 corresponds to the layer, and the n-type diffusion layer 23 corresponds to the fourth n-type diffusion layer described above. Further, the above-described gate region portion corresponds to a region between the first n-type diffusion layer 5 and the second n-type diffusion layer 6. The metal wiring 12 corresponds to the first metal wiring, the metal wiring 13 corresponds to the second metal wiring, and the metal wiring 25 corresponds to the third metal wiring.

  Further, the first high voltage applied to the gate of the first transistor during charge accumulation (writing) to the floating gate is the voltage “6” V of the control gate CG shown in FIG. The second voltage applied to the drain D corresponds to the voltage “5” V of the drain D. In the first erasing means, the third voltage applied to the drain D corresponds to the voltage “8” V of the drain D shown in FIG. 22B, and is applied to the source S described above. The fourth voltage corresponds to the voltage “2” V of the source S. In the second erasing means described above, the fifth voltage applied to the control gate CG corresponds to the voltage “1” V of the control gate CG shown in FIG.

  Then, a transistor forming portion 3 for forming a transistor is disposed in a first direction (vertical direction in FIG. 21) on the surface of the semiconductor substrate. The transistor forming portion 3 is arranged in order from the top with the drain of the transistor T1. A first n-type diffusion layer 5 to be formed, a gate region portion 4 for forming a channel (a region between the first diffusion layer 5 and the second diffusion layer 6), and a second n serving as a source of the transistor T1. A mold diffusion layer 6 is disposed.

  On the left side of the transistor forming portion 3, the metal wiring 12 is arranged in the vertical direction. The metal wiring 12 is arranged in parallel to the transistor formation portion 3 at a predetermined distance from the surface of the semiconductor substrate, and the metal wiring 12 is connected to the drain (first n-type diffusion layer 5) of the transistor T1 through the contact 10. Is done.

  On the left side of the transistor formation portion 3, an n-type well 2 is formed in the left-right direction with a predetermined width and depth. The rectangular floating gate 9 is disposed in the left-right direction so as to face the surface of the semiconductor substrate, the region on the left end side thereof is opposed to the surface of the n-type well 2, and the region on the right end side is the transistor T1. The gate region 4 is disposed so as to face the gate region 4 (a channel forming region intermediate between the first n-type diffusion layer 5 and the second n-type diffusion layer 6).

  On the left side of the n-type well 2, a p-type diffusion layer 15 having a predetermined width and depth is formed in the left-right direction adjacent to the left side of the region facing the floating gate 9 of the n-type well 2. . The p-type diffusion layer 15 and the control gate wiring 19 are connected by a contact 16. The control gate line 19 is disposed in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the floating gate 9, and is connected to the p-type diffusion layer 15 by a contact 16. The second metal wiring 13 is disposed in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to oppose the second n-type diffusion layer 6 serving as the source of the transistor T1, and the second metal wiring 13 13 is connected to the second n-type diffusion layer 6 by a contact 11.

  Further, a fourth n-type diffusion layer 23 having a predetermined width and depth is formed on the upper side of the p-type diffusion layer 15 and on the left side of the first n-type diffusion layer. Then, a third metal wiring 25 arranged in parallel with the transistor formation portion 3 and at a predetermined distance from the surface of the semiconductor substrate is provided, and the metal wiring 25 and the fourth n-type diffusion layer 23 are connected to the cocontact 24. Connect with. The metal wiring 25 and the n-type diffusion layer 23 give a desired potential to the n-type well 2.

  With such a configuration, a non-volatile memory can be realized by a standard logic CMOS process, and OTP or MTP can be realized. In addition, a capacitor having a large area (a capacitor formed on the surface of the floating gate and the semiconductor substrate) can be compactly arranged to minimize the area. Furthermore, an n-type diffusion layer and a metal wiring for applying a predetermined voltage CGWell to the n-type well can be arranged in an empty space, and the area of the memory cell can be further reduced.

[Fourteenth embodiment]
FIG. 23 is a diagram showing a configuration of a nonvolatile semiconductor memory device according to the fourteenth embodiment of the present invention. The example shown in FIG. 23 is an example in which the nonvolatile semiconductor memory element (memory cell) of the present invention is incorporated in a matrix array (memory cell array), and is an example in the case of OTP.

  In the example shown in FIG. 23, the configuration of the memory array is such that the input / output I / O has an 8-bit configuration of IO-0 to IO-7, and the memory array has n bits in the column direction and m bits in the row direction. The unit memory cell blocks 100-0 to 100-7 are configured.

  That is, memory cells are grouped in units of n bits in the column direction, such as M11-0 to M1n-0, M11-7 to M1n-7, and memory cells 100-0 to 100-7 are configured. . Therefore, the memory capacity is m rows × n columns × 8 bits.

  Each of the row decoders 200-1 to 200-m includes an address decoder 201, an inverter 202, and a level shift circuit 203. The output of the level shift circuit 203 is a signal of the word lines WL1 to WLm, respectively.

  Since the OTP is not erased, the word lines can be commonly connected in the row direction. For example, the word line WL1 is commonly connected to all the memory cells M11-0 to M1n-0 and M11-7 to M1n-7. The same applies to the word line WLm.

  Similarly to the row decoder, the column decoders 300-1 to 300-n each include an address decoder 301, an inverter 302, and a level shift circuit 303. The level shift circuit 303 converts the column selection signal output from the column decoders 300-1 to 300-n into the second signal voltage Vp2.

  The outputs of the level shift circuit 303 are signals COL1 to COLn, which are input to the gates of the column selection transistors CG1-0 to CG1-7,... CGn-0 to CGn-7, respectively. For example, the output of the column decoder 300-1 is a gate input signal of the column selection transistors CG1-0 to CG1-7.

  Bit lines BIT1-0 to BIT1-7 to which the drains of the memory cells are connected are connected to data lines D0 to D7 via column selection transistors CG1-0 to CG1-7, respectively. Similarly, bit lines BITn-0 to BITn-7 are connected to data lines D0 to D7 through column selection transistors CGn-0 to CGn-7, respectively.

  The data lines D0 to D7 receive the write input data Din0 to Din7, receive the data conversion circuit 400 that outputs the write data (write voltage 5V), and the data of the memory cell at the time of read, and amplify and output the signal. Sense amplifier circuits 500-1 to 500-7 serving as read output circuits are connected.

Next, the operation will be described.
At the time of writing, for example, when the row decoder 200-1 and the column decoder 300-1 are selected, the word line WL1 and the signal COL1 are selected, and 6V (first signal voltage VP1) and 8V (second signal voltage), respectively. A voltage of VP2) is applied. At this time, in response to the write data Din0 to Din7, the data conversion circuit 400 outputs a write voltage 5V (third signal voltage VP3) to the data input / output lines D0 to D7.

  Here, it is assumed that “Din0 = Din2 = Din4 = Din6 =“ 0 ”data (write)” and “Din1 = Din3 = Din5 = Din7 =“ 1 ”data (not write)” are input as write data.

  In this case, since “D0 = D2 = D4 = D6 = 5V” and “D1 = D3 = D5 = D7 = 0V” are output to the data line and the signal COL1 is selected and becomes 8V, the bit line The signal voltages of “BIT1-0 = BIT1-2 = BIT1-4 = BIT1-6 = 5V”, “BIT1-1 = BIT1-3 = BIT1-5 = BIT1-7 = 0V”, and the memory cell M11− 0, M11-2, M11-4, and M11-6 are written, and the memory cells M11-1, M11-3, M11-5, and M11-7 are not written. In this way, arbitrary data can be written into an arbitrary memory cell.

  In reading, if the selected memory cell is in the erased state (“1”; on), a current flows through the memory cell, and if it is in the written state (“0”; off), no current flows. Then, the amplification is determined by the sense amplifier circuit 500, and data Dout0 to Dout7 are output. This circuit is an OTP and normally does not erase the data in the memory cell. However, if the memory cell needs to be erased, the selected control gate WL is set to 0 V and the selected column decoder is connected. Then, 8V may be applied to the drain.

  Note that FIG. 25A shows an operation table in the write operation described above. As shown in the figure, the voltage CGWell applied to the metal wiring 25 is always set equal to or higher than the voltage of the control gate CG (word line).

  In the nonvolatile semiconductor memory element according to the fifteenth embodiment shown in FIG. 23, the level shift circuit 203 is the first level shift circuit, and the level shift circuit 303 is the second level shift circuit. Respectively.

  In the nonvolatile semiconductor memory device according to the fifteenth embodiment, the number of input / output I / O bits of column address n bits (n ≧ 1) and io bits (io ≧ 1), for example, 8 Based on the bits, a plurality of memory cell blocks 100-0 to 100-7 configured by dividing the memory cell array into the number of I / O bits in the column address unit of n bits in the column direction are arranged.

  A plurality of bit lines BIT1-0 to BITbn-7, in which the drains of the transistors of each memory cell are commonly connected in the row direction, and word lines provided for each row, the control gates of the transistors of the memory cells Is a word line WL1 to WLm commonly connected in the column direction, a source line S to which the sources of the transistors of the memory cells are commonly connected, and a row decoder provided for each row, which receives an address signal Row decoders 200-1 to 200-m that generate row selection signals for selecting the memory cells, and row selection signals output from the respective row decoders are converted into signals of a first signal voltage Vp1 applied to the word lines. A first level shift circuit 203 and a column decoder provided corresponding to the number of bits n in the column direction in the memory cell block; Thus, n column decoders 300-1 to 300-n for outputting a column selection signal for selecting one memory cell from each memory cell block, and a column selection signal output from the column decoder as a second signal. A second level shift circuit 303 for converting the signal to a voltage Vp2 and a column selection transistor in units of n bits provided for each of the memory cell blocks, and the second level shift circuit 303 outputs the second level shift circuit 303; Column select transistors CG1-0 to CGn-7 for selecting a memory cell having the number of I / O bits by selecting a bit line of one memory cell from each memory cell block. The number of I / O bits connected to the bit line of the number of I / O bits selected by the selection transistor via the column selection transistor. The third voltage applied to the drains of the transistors through the data input / output lines when the data input / output lines D0 to D7 and the input signal of the write data having the number of I / O bits are received and data is written and erased. A data conversion circuit 400 that outputs the signal Vp3 and a sense amplifier circuit 500 that amplifies the data of the memory cells read to the data input / output lines D0 to D7 and outputs them to the outside are configured.

  Thus, OTP can be realized using the nonvolatile semiconductor memory element shown in FIG. In addition, a capacitor having a large area (a capacitor formed on the surface of the floating gate and the semiconductor substrate) can be compactly arranged to minimize the area. Furthermore, the n-type diffusion layer 23 and the metal wiring 25 for applying a desired voltage CGWell to the n-type well 2 can be arranged in an empty space, and the area of the memory cell can be further reduced.

  As described above, as the fourteenth embodiment of the present invention, the example in the case where the OTP is configured using the nonvolatile semiconductor memory element illustrated in FIG. 21 has been described. However, the present invention is not limited to this, and other configurations of the OTP, An MTP can be configured.

  For example, as in the third embodiment shown in FIG. 7 and the twelfth embodiment shown in FIG. 20, an MTP in which memory cell arrays are grouped in units of n bits in the column direction can be configured. Similarly to the fourth embodiment shown in FIG. 10, it is possible to configure an MTP in which memory cell arrays are grouped in I / O bit units (for example, 8 bits) in the column direction. Furthermore, as in the eleventh embodiment shown in FIG. 19, an OTP in which memory cell arrays are grouped in I / O bit units (for example, 8 bits) in the column direction can be configured.

  FIG. 25B shows an operation table in the case where an OTP and an MTP are configured by the nonvolatile semiconductor memory element shown in FIG.

[Fifteenth embodiment]
FIG. 24 is a diagram showing a configuration of a nonvolatile semiconductor memory device according to the fifteenth embodiment of the present invention, and shows a layout arrangement of the memory cell array.

  The layout of the memory cell array shown in FIG. 24 is obtained by arranging the nonvolatile semiconductor memory elements (memory cells) shown in FIG. 21 in an array, and this memory cell is connected to the n-type well 2 as described above. N-type diffusion layer 23, metal wiring 25 for applying a predetermined voltage CGWell to N-Well, and contact 24 for connecting n-type diffusion layer 23 and metal wiring 25.

  In the memory cell array shown in FIG. 24, the word lines WL1, WL2, WL3,... And the source lines S1 (S1, S2), S1 (S3, S4),. , BIT2, BIT3... Are vertically passed, and the metal wiring 25 is vertically passed. The memory cell units shown in FIG. 21 are arranged symmetrically left and right around the metal wiring 25, arranged symmetrically around the source line S1, and the n-type well 2 is shared by each other. We are trying to reduce it. The n-type well 2 is an n-type well shared by two columns of memory cells (for example, two columns of memory cells whose drains are connected to the bit line BIT1 and the bit line BIT2). Are connected to the metal wiring 25 by n-type diffusion layers 23 and contacts 24 formed at a plurality of locations of the n-type well 2.

  For example, the memory cells arranged in this layout will be described by focusing on the memory cell of the portion A surrounded by the broken line in FIG. 24 (the memory cell selected by the word line WL1 and the bit line BIT2). The transistor forming portion 3 arranged in the vertical direction in the figure includes a first n-type diffusion layer 5 that becomes a drain of the transistor, and a gate region portion (first n-type diffusion layer 5 that forms a channel of the transistor). And an intermediate region between the second n-type diffusion layer 6 and the second n-type diffusion layer 6 serving as the source of the transistor.

  On the left side of the transistor formation portion 3, the first metal wiring 12 is arranged in the vertical direction. The metal wiring 12 is arranged in parallel to the transistor formation portion 3 at a predetermined distance from the surface of the semiconductor substrate. The metal wiring 12 is connected to the drain of the transistor (first n-type diffusion layer 5) by a contact 10. The The first metal wiring 12 is connected to the bit line BIT2.

  The rectangular floating gate 9 is arranged in the left-right direction so as to face the surface of the semiconductor substrate, the region on the left end side thereof faces the surface of the n-type well 2, and the region on the right end side is a gate region portion. The first n-type diffusion layer 5 and the second n-type diffusion layer 6 are disposed so as to face each other.

  On the left side of the n-type well 2, a p-type diffusion layer 15 having a predetermined width and depth is formed in the left-right direction adjacent to the left side of the region facing the floating gate 9 of the n-type well 2. . The p-type diffusion layer 15 and the control gate wiring 19 are connected by a contact 16. The control gate line 19 is disposed in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the floating gate 9, and is connected to the p-type diffusion layer 15 by a contact 16. The control gate line 19 is connected to the common word line WL1.

  The second metal wiring 13 is disposed in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to oppose the second n-type diffusion layer 6 serving as the source of the transistor T1, and the second metal wiring 13 13 is connected to the second n-type diffusion layer 6 by a contact 11. The second metal wiring 13 is connected to the common source line S1.

  In addition, a fourth n-type diffusion layer 23 having a predetermined width and depth is formed on the upper side of the p-type diffusion layer 15 and on the left side of the first n-type diffusion layer 5, and the third metal The wiring 25 is arranged in the vertical direction at a predetermined distance from the surface of the semiconductor substrate in parallel with the first metal wiring 12. A fourth n-type diffusion layer 23 is connected to the third metal wiring 25 by a contact 24.

  In the nonvolatile semiconductor memory device shown in FIG. 24, two memory cells (BIT1, WL1, and BIT2, WL1) are arranged symmetrically on the left and right with the n-type well 2 in common and the metal wiring 25 as the center. And the two memory cells arranged symmetrically in the downward direction with the common source line S1 in common with each other. A total of four memory cells (two memory cells selected by BIT1, WL2 and BIT2, WL2) are used as a basic unit of arrangement.

  Then, the four memory cells that are the basic unit of this arrangement are arranged in parallel in the left-right direction, and are also arranged in parallel in the up-down direction.

  Accordingly, the nonvolatile semiconductor memory element shown in FIG. 21 can be arranged in a compact manner, and the area of the nonvolatile semiconductor memory device can be minimized.

  As described above, in the nonvolatile semiconductor memory element and the nonvolatile semiconductor memory device of the present invention, a nonvolatile memory can be realized by a standard logic CMOS process, and a logic embedded memory can be realized easily and inexpensively.

  Although the embodiments of the present invention have been described above, the nonvolatile semiconductor memory element and the nonvolatile semiconductor memory device of the present invention are not limited to the above illustrated examples, and do not depart from the gist of the present invention. Of course, various changes can be made within the range.

DESCRIPTION OF SYMBOLS 1 ... p-type semiconductor substrate, 2 ... n-type well (n-well), 3 ... transistor formation part, 4 ... transistor channel formation part (gate region part), 5 ... n-type diffusion layer (first n-type diffusion layer) Layer), 6... N-type diffusion layer (second n-type diffusion layer), 9... Floating gate, 9 A... Area expansion part 10, 11 ... Contact, 12 ... Metal wiring (first metal wiring), 13. Metal wiring (second metal wiring), 14 ... capacitor, 15 ... p-type diffusion layer, 15 '... n-type diffusion layer (third n-type diffusion layer), 19 ... control gate wiring, 21 ... D- Type (depletion-type) channel implanter, 23... N-type diffusion layer (fourth n-type diffusion layer), 24... Contact, 25... Metal wiring (third metal wiring), 100- 0 to 100-7 memory cell block 101-1 to 101-n ... memory cell block, 200, 200A, 200-1 to 200-m ... row decoder, 201 ... address decoder, 202 ... inverter, 203 ... level shift circuit (first level shift circuit), 300-1 to 300-n... Column decoder, 301... Address decoder, 302... Inverter, 303... Level shift circuit (second level shift circuit), 209-1, 209-2, 209-m. 220 ... row decoder, 400 ... data conversion circuit, 500 ... sense amplifier circuit, CG1-0 to CG1-7, CGn-0 to CGn-7 ... column selection transistor, D0-D7 ... data input / output line

Claims (25)

A floating gate type single layer polysilicon non-volatile memory device configured by a standard CMOS process on a semiconductor substrate,
When the first direction on the semiconductor substrate is represented in the up-down direction and the second direction orthogonal to the first direction is represented in the left-right direction,
A first n-type diffusion layer serving as a drain of the transistor, a gate region forming a channel of the transistor, and a second n-type diffusion layer serving as a source of the transistor are sequentially arranged in the vertical direction. A transistor forming portion having a shape;
A first metal wiring disposed on the left or right side of the transistor forming portion in parallel with the transistor forming portion and at a predetermined distance from the surface of the semiconductor substrate, and connected to the drain of the transistor by a contact;
On the semiconductor substrate, on the left side of the transistor forming portion, a rectangular n-type well formed in the left-right direction with a predetermined width and depth;
Arranged so as to face the surface of the semiconductor substrate in the left-right direction, the region on the left end side thereof facing the surface of the n-type well, and the region on the right end side facing the gate region portion A square-shaped floating gate,
A p-type diffusion layer formed adjacent to the left side of the region facing the floating gate of the n-type well and having a predetermined width and depth in the left-right direction and serving as a connection terminal to the control gate wiring;
A control gate line disposed in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the floating gate, and connected to the p-type diffusion layer by a contact;
The second n-type diffusion layer is disposed in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the second n-type diffusion layer, and is connected to the second n-type diffusion layer by a contact. Metal wiring,
A non-volatile semiconductor memory device comprising: A floating gate type single layer polysilicon non-volatile memory device configured by a standard CMOS process on a semiconductor substrate,
When the first direction on the semiconductor substrate is represented in the up-down direction and the second direction orthogonal to the first direction is represented in the left-right direction,
A first n-type diffusion layer serving as a drain of the transistor, a gate region forming a channel of the transistor, and a second n-type diffusion layer serving as a source of the transistor are sequentially arranged in the vertical direction. A transistor forming portion having a shape;
A first metal wiring disposed on the left or right side of the transistor forming portion in parallel with the transistor forming portion and at a predetermined distance from the surface of the semiconductor substrate, and connected to the drain of the transistor by a contact;
On the semiconductor substrate, on the left side of the transistor formation portion, a square-shaped D-type (Depletion-type) channel implant formed in the left-right direction with a predetermined width and depth;
The semiconductor substrate is disposed in the left-right direction so as to face the semiconductor substrate surface, and the region on the left end side faces the surface of the channel implanter, and the region on the right end side faces the gate region portion. A rectangular floating gate,
A third n-type diffusion layer adjacent to the left side of the channel implant, formed in the left-right direction with a predetermined width and depth, and serving as a connection terminal to the control gate wiring;
A control gate line disposed in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the floating gate, and connected to the third n-type diffusion layer by a contact;
The semiconductor device is arranged in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the second n-type diffusion layer serving as the source of the transistor, and is connected to the second n-type diffusion layer by a contact. A second metal wiring to be
A non-volatile semiconductor memory device comprising: The nonvolatile semiconductor memory device is configured as an MTP (Multi Time Programmable ROM),
When accumulating charges accumulated in the floating gate,
Applying a first voltage to the control gate of the transistor, applying a second voltage to the drain, applying a voltage of "0" V to the source;
Generating hot electrons near the drain of the transistor, injecting the hot electrons into the floating gate;
When erasing charges on the floating gate,
As the first erasing means,
A voltage of “0” V is applied to the control gate of the transistor, a third voltage is applied to the drain, the source is opened, or a fourth voltage is applied (third voltage> second voltage). 4 voltage),
Means for discharging the floating gate charge by FN current (Fowler-Nordheim tunneling current) by applying a high electric field between the drain and the floating gate;
As the second erasing means performed after the execution of the first erasing means,
“0” V or a fifth voltage is applied to the control gate of the transistor, the third voltage is applied to the drain, and “0” V is applied to the source (third voltage> fifth Voltage),
Means for generating hot electrons near the drain of the transistor and injecting the hot electrons into the floating gate for a predetermined time;
The nonvolatile semiconductor memory element according to claim 1, comprising: The nonvolatile semiconductor memory element is configured as an OTP (One Time Programmable ROM),
When accumulating charge in the floating gate,
Applying a first voltage to the control gate of the transistor, applying a second voltage to the drain, applying a voltage of "0" V to the source;
Generating hot electrons near the drain of the transistor and injecting the hot electrons into the floating gate;
The non-volatile semiconductor memory element according to claim 1, wherein: A memory cell array is formed by arranging memory cells, which are floating gate type single-layer polysilicon nonvolatile memory elements formed by a standard CMOS process, on a semiconductor substrate in a matrix at intersections of word lines and data lines. A non-volatile semiconductor memory device comprising:
The memory cell is an OTP (One Time Programmable ROM),
When accumulating charge in the floating gate,
Applying a first voltage to the control gate of the transistor, applying a second voltage to the drain, applying a voltage of "0" V to the source;
Generating hot electrons near the drain of the transistor, and injecting the hot electrons into the floating gate;
The nonvolatile semiconductor memory device includes:
Based on the number of input / output I / O bits of column address n bits (n ≧ 1) and io bits (io ≧ 1), the memory cell array is arranged in the column direction in the unit of the column address n bits. A plurality of memory cell blocks divided into a number are arranged,
A plurality of bit lines in which the drains of the transistors of the memory cells are commonly connected in the row direction;
A word line provided for each row, the word lines commonly connecting the control gates of the transistors of the memory cells along the column direction;
A source line commonly connected to the sources of the transistors of each memory cell;
A row decoder provided for each row, the row decoder generating a row selection signal for receiving the address signal and selecting the memory cell;
A first level shift circuit that converts a row selection signal output from each row decoder into a signal of a first signal voltage Vp1 applied to the word line;
A column decoder provided corresponding to the number n of bits in the column direction in the memory cell block, wherein n column decoders output a column selection signal for selecting one memory cell from each of the memory cell blocks;
A second level shift circuit for converting a column selection signal output from the column decoder into a signal of a second signal voltage Vp2;
An n-bit unit column selection transistor provided for each of the memory cell blocks, wherein the second signal voltage Vp2 output from the second level shift circuit is used as a gate input, and 1 column from each memory cell block. A column selection transistor for selecting a bit line of one memory cell and selecting a memory cell having the number of I / O bits;
A data input / output line of the number of I / O bits connected to the bit line of the number of I / O bits selected by the column selection transistor via the column selection transistor;
Write that outputs a third voltage signal Vp3 applied to the drain of the transistor through the data input / output line when data write and data erase are performed in response to an input signal of write data of the number of I / O bits A control circuit;
A sense amplifier circuit that amplifies the data of the memory cell read to the data input / output line and outputs the amplified data to the outside;
A non-volatile semiconductor memory device comprising: A memory cell array is formed by arranging memory cells, which are floating gate type single-layer polysilicon nonvolatile memory elements formed by a standard CMOS process, on a semiconductor substrate in a matrix at intersections of word lines and data lines. A non-volatile semiconductor memory device comprising:
The memory cell is an OTP (One Time Programmable ROM),
When accumulating charge in the floating gate,
Applying a first voltage to the control gate of the transistor, applying a second voltage to the drain, applying a voltage of "0" V to the source;
Generating hot electrons near the drain of the transistor, and injecting the hot electrons into the floating gate;
The nonvolatile semiconductor memory device includes:
A plurality of memory cell blocks configured by dividing the memory cell array in the column direction in units of the number of input / output I / O bits of io bits (io ≧ 1),
A plurality of bit lines in which the drains of the transistors of the memory cells are commonly connected in the row direction;
A word line provided for each row, the word lines commonly connecting the control gates of the transistors of the memory cells along the column direction;
A source line commonly connected to the sources of the transistors of each memory cell;
A row decoder provided for each row, the row decoder generating a row selection signal for receiving the address signal and selecting the memory cell;
A first level shift circuit that converts a row selection signal output from each row decoder into a signal of a first signal voltage Vp1 applied to the word line;
A column decoder that receives an address signal and outputs a column selection signal for selecting the memory cells in the column direction in units of the number of I / O bits;
A second level shift circuit for converting a selection signal output from the column decoder into a second signal voltage Vp2;
A column selection transistor provided for each memory cell block in units of the number of I / O bits, wherein the second signal voltage Vp2 output from the second level shift circuit is used as a gate input, and the selected memory cell A column selection transistor for selecting a bit line of the memory cell having the number of I / O bits from the block;
A data input / output line of the number of I / O bits connected to the bit line of the number of I / O bits selected by the column selection transistor via the column selection transistor;
A third voltage signal Vp3 to be applied to the drain of the first transistor through the data input / output line when data write and data erase are performed in response to an input signal of write data having the number of I / O bits. Write control circuit to
A sense amplifier circuit that amplifies the data of the memory cell read to the data input / output line and outputs the amplified data to the outside;
A non-volatile semiconductor memory device comprising: A memory cell array is formed by arranging memory cells, which are floating gate type single-layer polysilicon nonvolatile memory elements formed by a standard CMOS process, on a semiconductor substrate in a matrix at intersections of word lines and data lines. A non-volatile semiconductor memory device comprising:
The memory cell is configured as an MTP (Multi Time Programmable ROM),
A step of generating hot electrons in the vicinity of the drain of the MOS transistor during charge accumulation in the floating gate and injecting the hot electrons into the floating gate is performed;
When erasing charges on the floating gate,
A first step of injecting charges into the floating gate by an FN current (Fowler-Nordheim tunneling current);
A second step of generating hot electrons near the drain of the transistor after the first step and injecting the hot electrons into the floating gate for a predetermined time;
A non-volatile semiconductor memory device characterized in that is executed. A memory cell array is formed by arranging memory cells, which are floating gate type single-layer polysilicon nonvolatile memory elements formed by a standard CMOS process, on a semiconductor substrate in a matrix at intersections of word lines and data lines. A non-volatile semiconductor memory device comprising:
The memory cell is configured as an MTP (Multi Time Programmable ROM),
At the time of charge accumulation in the floating gate, hot electrons are generated near the drain of the MOS transistor, the hot electrons are injected into the floating gate, and
At the time of erasing the charge to the floating gate, after injecting the charge into the floating gate by an FN current (Fowler-Nordheim tunnel current), hot electrons are generated in the vicinity of the drain of the transistor, Configured to inject into the floating gate,
The nonvolatile semiconductor memory device includes:
Based on the number of input / output I / O bits of column address n bits (n ≧ 1) and io bits (io ≧ 1), the memory cell array is arranged in the column direction in the unit of the column address n bits. A plurality of memory cell blocks divided into a number are arranged,
A plurality of bit lines in which the drains of the transistors of the memory cells are commonly connected in the row direction;
A word line provided for each row, the word lines commonly connecting the control gates of the transistors of the memory cells along the column direction;
A source line provided for each row, the source line commonly connecting the sources of the transistors of the memory cells along the column direction;
A switching transistor provided for each of the source lines for selecting whether the source line is grounded or opened to GND (“0” V);
A row decoder provided for each row, which receives an address signal, generates a row selection signal for selecting the memory cell, selects a voltage level of the row selection signal and applies it to the word line, and the switch A row decoder for outputting a signal for controlling on / off of the transistor for use;
A column decoder provided corresponding to the number n of bits in the column direction in the memory cell block, wherein n column decoders output a column selection signal for selecting one memory cell from each of the memory cell blocks;
A second level shift circuit for converting a column selection signal output from the column decoder into a signal of a second signal voltage Vp2;
An n-bit unit column selection transistor provided for each of the memory cell blocks, with a column selection signal Vp2 output from the second level shift circuit as a gate input, and one memory cell from each memory cell block A column select transistor for selecting a bit line of the cell and selecting a memory cell having the number of I / O bits;
A data input / output line of the number of I / O bits connected to the bit line of the number of I / O bits selected by the column selection transistor via the column selection transistor;
Write that outputs a third voltage signal Vp3 applied to the drain of the transistor through the data input / output line when data write and data erase are performed in response to an input signal of write data of the number of I / O bits A control circuit;
A sense amplifier circuit that amplifies the data of the memory cell read to the data input / output line and outputs the amplified data to the outside;
A non-volatile semiconductor memory device comprising: The row decoder
2-bit write control signals E1 and E2 are used as control inputs,
Depending on the values of the control signals E1, E2,
A write mode for outputting the first signal voltage Vp1 to the word line and turning on the switch transistor when writing data to the memory cell;
A first erase mode for outputting "0" V to the word line and outputting a signal for turning off the switching transistor when erasing data in the memory cell;
A second erase mode for outputting "0" V of the word line and outputting a signal for turning on the switching transistor when erasing data of the memory cell;
The nonvolatile semiconductor memory device according to claim 8, comprising: A memory cell array is formed by arranging memory cells, which are floating gate type single-layer polysilicon nonvolatile memory elements formed by a standard CMOS process, on a semiconductor substrate in a matrix at intersections of word lines and data lines. A non-volatile semiconductor memory device comprising:
The memory cell is configured as an MTP (Multi Time Programmable ROM),
At the time of charge accumulation in the floating gate, hot electrons are generated near the drain of the MOS transistor, the hot electrons are injected into the floating gate, and
At the time of erasing the charge to the floating gate, after injecting the charge into the floating gate by an FN current (Fowler-Nordheim tunnel current), hot electrons are generated in the vicinity of the drain of the transistor, Configured to inject into the floating gate,
The nonvolatile semiconductor memory device includes:
A plurality of memory cell blocks configured by dividing the memory cell array in the column direction in units of the number of input / output I / O bits of io bits (io ≧ 1) are arranged,
A plurality of bit lines in which the drains of the transistors of the memory cells are commonly connected in the row direction;
A word line provided for each row, the word lines commonly connecting the control gates of the transistors of the memory cells along the column direction;
A source line provided for each row, the source line commonly connecting the sources of the transistors of the memory cells along the column direction;
A switching transistor provided for each of the source lines for selecting whether the source line is grounded or opened to GND (“0” V);
A row decoder provided for each row, which receives an address signal, generates a row selection signal for selecting the memory cell, selects a voltage level of the row selection signal and applies it to the word line, and the switch A row decoder for outputting a signal for controlling on / off of the transistor for use;
A column decoder that receives an address signal and outputs a column selection signal for selecting the memory cells in the column direction in units of the number of I / O bits;
A second level shift circuit for converting a column selection signal output from the column decoder into a second signal voltage Vp2;
A column selection transistor provided for each memory cell block in units of the number of I / O bits, wherein the second signal voltage Vp2 output from the second level shift circuit is used as a gate input, and the selected memory cell A column selection transistor for selecting a bit line of the memory cell having the number of I / O bits from the block;
A data input / output line of the number of I / O bits connected to the bit line of the number of I / O bits selected by the column selection transistor via the column selection transistor;
A fourth voltage signal Vp3 applied to the drain of the transistor of the memory cell through the data input / output line when data writing and data erasing are performed in response to an input signal of write data having the number of I / O bits. A write control circuit for outputting;
A sense amplifier circuit that amplifies the data of the memory cell read to the data input / output line and outputs the amplified data to the outside;
A non-volatile semiconductor memory device comprising: The row decoder
2-bit write control signals E1 and E2 are used as control inputs,
Depending on the values of the control signals E1, E2,
A write mode for outputting the first signal voltage Vp1 to the word line and turning on the switch transistor when writing data to the memory cell;
A first erase mode for outputting "0" V to the word line and outputting a signal for turning off the switching transistor when erasing data in the memory cell;
A second erase mode for outputting "0" V of the word line and outputting a signal for turning on the switching transistor when erasing data of the memory cell;
The nonvolatile semiconductor memory device according to claim 10, comprising: A memory cell array is formed by arranging memory cells, which are floating gate type single-layer polysilicon nonvolatile memory elements formed by a standard CMOS process, on a semiconductor substrate in a matrix at intersections of word lines and data lines. A non-volatile semiconductor memory device comprising:
The memory cell is configured as an MTP (Multi Time Programmable ROM),
At the time of charge accumulation in the floating gate, hot electrons are generated near the drain of the MOS transistor, the hot electrons are injected into the floating gate, and
At the time of erasing the charge to the floating gate, after injecting the charge into the floating gate by an FN current (Fowler-Nordheim tunnel current), hot electrons are generated in the vicinity of the drain of the transistor, Configured to inject into the floating gate,
The nonvolatile semiconductor memory device includes:
Based on the number of input / output I / O bits of column address n bits (n ≧ 1) and io bits (io ≧ 1), the memory cell array is arranged in the column direction in the unit of the column address n bits. A plurality of memory cell blocks divided into a number are arranged,
A plurality of bit lines in which the drains of the transistors of the memory cells are commonly connected in the row direction;
A word line provided for each row, the word line commonly connecting the control gates CG of the transistors of the memory cell along the column direction;
A source line provided for each pair of two rows, the source lines commonly connecting the sources of the transistors of the memory cells of the two rows along the column direction;
Two switching transistors provided for each source line, which selects whether the source line is grounded or opened to GND (“0” V) according to a signal from one of the paired two row decoders And a second switch transistor that selects whether the source line is grounded or opened to GND (“0” V) according to a signal from the other of the two paired row decoders When,
A row decoder provided for each row, which receives an address signal, generates a row selection signal for selecting the memory cell, selects a voltage level of the row selection signal, applies it to the word line, and A row decoder which forms a pair, outputs a control signal for turning on and off the first switch transistor from one side, and outputs a control signal for turning on and off the second switch transistor from the other side;
A column decoder provided corresponding to the number n of bits in the column direction in the memory cell block, wherein n column decoders output a column selection signal for selecting one memory cell from each of the memory cell blocks;
A second level shift circuit for converting a column selection signal output from the column decoder into a signal of a second signal voltage Vp2;
An n-bit unit column selection transistor provided for each of the memory cell blocks, wherein the second signal voltage Vp2 output from the second level shift circuit is used as a gate input, and 1 column from each memory cell block. A column selection transistor for selecting a bit line of one memory cell and selecting a memory cell having the number of I / O bits;
A data input / output line of the number of I / O bits connected to the bit line of the number of I / O bits selected by the column selection transistor via the column selection transistor;
Write that outputs a third voltage signal Vp3 applied to the drain of the transistor through the data input / output line when data write and data erase are performed in response to an input signal of write data of the number of I / O bits A control circuit;
A sense amplifier circuit that amplifies the data of the memory cell read to the data input / output line and outputs the amplified data to the outside;
A non-volatile semiconductor memory device comprising: The row decoder
A write mode for outputting the first signal voltage Vp1 to the word line when the data is written to the memory cell and turning on the switch transistor corresponding to the row decoder;
At the time of erasing data in the memory cell, when the selected row decoder is selected, “0” V is output to the word line, and a signal for turning off the switching transistor corresponding to the row decoder is output. A first erasing mode for outputting a predetermined voltage signal to the word line and outputting a signal for turning off the switching transistor corresponding to the row decoder when the row decoder is selected;
At the time of erasing data in the memory cell, when the selected row decoder is selected, “0” V is output to the word line, and a signal for turning on the switching transistor corresponding to the row decoder is output. A second erasing mode that outputs “0” to the word line and outputs a signal for turning off the switching transistor corresponding to the row decoder in the case of a selected row decoder;
The nonvolatile semiconductor memory device according to claim 12, comprising: A memory cell array is formed by arranging memory cells, which are floating gate type single-layer polysilicon nonvolatile memory elements formed by a standard CMOS process, on a semiconductor substrate in a matrix at intersections of word lines and data lines. A non-volatile semiconductor memory device comprising:
The memory cell is configured as an MTP (Multi Time Programmable ROM),
At the time of charge accumulation in the floating gate, hot electrons are generated near the drain of the MOS transistor, the hot electrons are injected into the floating gate, and
At the time of erasing the charge to the floating gate, after injecting the charge into the floating gate by an FN current (Fowler-Nordheim tunnel current), hot electrons are generated in the vicinity of the drain of the transistor, Configured to inject into the floating gate,
The nonvolatile semiconductor memory device includes:
a plurality of memory cell blocks configured by dividing the memory cell array in the column direction in units of the number of input / output I / O bits of io bits (io ≧ 1);
A plurality of bit lines in which the drains of the transistors of the memory cells are commonly connected in the row direction;
A word line provided for each row, the word line commonly connecting the control gates CG of the transistors of the memory cell along the column direction;
A source line provided for each pair of two rows, the source lines commonly connecting the sources of the transistors of the memory cells of the two rows along the column direction;
Two switching transistors provided for each source line, which selects whether the source line is grounded or opened to GND (“0” V) according to a signal from one of the paired two row decoders And a second switch transistor that selects whether the source line is grounded or opened to GND (“0” V) according to a signal from the other of the two paired row decoders When,
A row decoder provided for each row, which receives an address signal, generates a row selection signal for selecting the memory cell, selects a voltage level of the row selection signal, applies it to the word line, and A row decoder which forms a pair, outputs a control signal for turning on and off the first switch transistor from one side, and outputs a control signal for turning on and off the second switch transistor from the other side;
A column decoder that receives an address signal and outputs a column selection signal for selecting the memory cells in the column direction in units of the number of I / O bits;
A second level shift circuit for converting a selection signal output from the column decoder into a second signal voltage Vp2;
A column selection transistor provided for each memory cell block in units of the number of I / O bits, wherein the second signal voltage Vp2 output from the second level shift circuit is used as a gate input, and the selected memory cell A column selection transistor for selecting a bit line of the memory cell having the number of I / O bits from the block;
A data input / output line of the number of I / O bits connected to the bit line of the number of I / O bits selected by the column selection transistor via the column selection transistor;
A fourth voltage signal Vp3 to be applied to the drain of the first transistor through the data input / output line when data is written and erased in response to an input signal of write data having the number of I / O bits. Write control circuit to
A sense amplifier circuit that amplifies the data of the memory cell read to the data input / output line and outputs the amplified data to the outside;
A non-volatile semiconductor memory device comprising: The row decoder
A write mode for outputting the first signal voltage Vp1 to the word line when the data is written to the memory cell and turning on the switch transistor corresponding to the row decoder;
At the time of erasing data in the memory cell, when the selected row decoder is selected, “0” V is output to the word line, and a signal for turning off the switching transistor corresponding to the row decoder is output. A first erasing mode for outputting a predetermined voltage signal to the word line and outputting a signal for turning off the switching transistor corresponding to the row decoder when the row decoder is selected;
At the time of erasing data in the memory cell, when the selected row decoder is selected, “0” V is output to the word line, and a signal for turning on the switching transistor corresponding to the row decoder is output. A second erasing mode that outputs “0” to the word line and outputs a signal for turning off the switching transistor corresponding to the row decoder in the case of a selected row decoder;
The nonvolatile semiconductor memory device according to claim 14, comprising: A non-volatile configuration in which each memory cell, which is a floating gate type single-layer polysilicon non-volatile memory device configured by a standard CMOS process on a semiconductor substrate, is arranged in a matrix at intersections of word lines and data lines A semiconductor memory device,
The memory cell has a layout of its constituent parts,
When the first direction on the semiconductor substrate is represented in the up-down direction and the second direction orthogonal to the first direction is represented in the left-right direction,
A first n-type diffusion layer serving as a drain of the transistor, a gate region forming a channel of the transistor, and a second n-type diffusion layer serving as a source of the transistor are sequentially arranged in the vertical direction. A transistor forming portion having a shape;
A first metal wiring disposed on the left or right side of the transistor forming portion in parallel with the transistor forming portion and at a predetermined distance from the surface of the semiconductor substrate, and connected to the drain of the transistor by a contact;
On the semiconductor substrate, on the left side of the transistor forming portion, a rectangular n-type well formed in the left-right direction with a predetermined width and depth;
Arranged so as to face the surface of the semiconductor substrate in the left-right direction, the region on the left end side thereof facing the surface of the n-type well, and the region on the right end side facing the gate region portion A square-shaped floating gate,
A p-type diffusion layer formed adjacent to the left side of the region facing the floating gate of the n-type well and having a predetermined width and depth in the left-right direction and serving as a connection terminal to the control gate wiring;
A control gate line disposed in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the floating gate, and connected to the p-type diffusion layer by a contact;
It is arranged in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the second n-type diffusion layer that becomes the source of the transistor, and is connected to the second n-type diffusion layer by a contact A second metal wiring to be
With
In the arrangement of the memory cells,
For the two memory cells arranged symmetrically on the left and right with the n-type well in common and the two memory cells arranged symmetrically on the left and right, the second metal wiring is shared with each other As a basic unit of arrangement, a total of four memory cells, two memory cells arranged symmetrically in the downward direction,
The four memory cells that are the basic unit of the above configuration are arranged in parallel in the left-right direction, and are also arranged in parallel in the vertical direction,
A non-volatile semiconductor memory device. A non-volatile configuration in which each memory cell, which is a floating gate type single-layer polysilicon non-volatile memory device configured by a standard CMOS process on a semiconductor substrate, is arranged in a matrix at intersections of word lines and data lines A semiconductor memory device,
The memory cell has a layout of its constituent parts,
When the first direction on the semiconductor substrate is represented in the up-down direction and the second direction orthogonal to the first direction is represented in the left-right direction,
A first n-type diffusion layer serving as a drain of the transistor, a gate region forming a channel of the transistor, and a second n-type diffusion layer serving as a source of the transistor are sequentially arranged in the vertical direction. A transistor forming portion having a shape;
A first metal wiring disposed on the left or right side of the transistor forming portion in parallel with the transistor forming portion and at a predetermined distance from the surface of the semiconductor substrate, and connected to the drain of the transistor by a contact;
On the semiconductor substrate, on the left side of the transistor formation portion, a square-shaped D-type (Depletion-type) channel implant formed in the left-right direction with a predetermined width and depth;
It is arranged in the left-right direction so as to face the semiconductor substrate surface, so that the region on the left end side faces the surface of the channel implanter, and the region on the right end side faces the gate region portion of the transistor. A square-shaped floating gate,
A third n-type diffusion layer adjacent to the left side of the channel implant, formed in the left-right direction with a predetermined width and depth, and serving as a connection terminal to the control gate wiring;
A control gate line disposed in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the floating gate, and connected to the third n-type diffusion layer by a contact;
The semiconductor device is arranged in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the second n-type diffusion layer serving as the source of the transistor, and is connected to the second n-type diffusion layer by a contact. A second metal wiring to be
With
In the arrangement of the memory cells,
Two memory cells arranged symmetrically on the left and right so as to share a third n-type diffusion layer serving as a connection terminal of the control gate, and two memory cells arranged symmetrically on the left and right A total of four memory cells of two memory cells arranged symmetrically in the downward direction with the second metal wiring in common with each other as a basic unit of arrangement,
The four memory cells that are the basic unit of the above configuration are arranged in parallel in the horizontal direction and arranged in parallel in the vertical direction,
A non-volatile semiconductor memory device. A non-volatile configuration in which each memory cell, which is a floating gate type single-layer polysilicon non-volatile memory device configured by a standard CMOS process on a semiconductor substrate, is arranged in a matrix at intersections of word lines and data lines A semiconductor memory device,
The memory cell has a layout of its constituent parts,
When the first direction on the semiconductor substrate is represented in the up-down direction and the second direction orthogonal to the first direction is represented in the left-right direction,
A first n-type diffusion layer serving as a drain of the transistor, a gate region forming a channel of the transistor, and a second n-type diffusion layer serving as a source of the transistor are sequentially arranged in the vertical direction. A transistor forming portion having a shape;
A first metal wiring disposed on the left or right side of the transistor forming portion in parallel with the transistor forming portion and at a predetermined distance from the surface of the semiconductor substrate, and connected to the drain of the transistor by a contact;
On the semiconductor substrate, on the left side of the transistor formation portion, a square-shaped D-type (Depletion-type) channel implant formed in the left-right direction with a predetermined width and depth;
It is arranged in the left-right direction so as to face the semiconductor substrate surface, so that the region on the left end side faces the surface of the channel implanter, and the region on the right end side faces the gate region portion of the transistor. A floating gate having a rectangular shape, the floating gate being provided with a square-shaped area expansion portion in a left end region facing the surface of the channel implant;
A third n-type diffusion layer adjacent to the left side of the channel implant, formed in the left-right direction with a predetermined width and depth, and serving as a connection terminal to the control gate wiring;
A control gate line disposed in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the floating gate, and connected to the third n-type diffusion layer by a contact;
The semiconductor device is arranged in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the second n-type diffusion layer serving as the source of the transistor, and is connected to the second n-type diffusion layer by a contact. A second metal wiring to be
With
In the arrangement of the memory cells,
The two n memory cells arranged symmetrically on the left and right so that the third n-type diffusion layer serving as the connection terminal of the control gate is shared with each other, and the two memory cells arranged symmetrically on the left and right A total of four memory cells of two memory cells arranged symmetrically in the downward direction with the second metal wiring in common with each other as a basic unit of arrangement,
The four memory cells that are the basic unit of the above configuration are arranged in parallel in the horizontal direction and arranged in parallel in the vertical direction,
A non-volatile semiconductor memory device. A non-volatile configuration in which each memory cell, which is a floating gate type single-layer polysilicon non-volatile memory device configured by a standard CMOS process on a semiconductor substrate, is arranged in a matrix at intersections of word lines and data lines A semiconductor memory device,
The memory cell has a layout of its constituent parts,
When the first direction on the semiconductor substrate is represented in the up-down direction and the second direction orthogonal to the first direction is represented in the left-right direction,
A first n-type diffusion layer serving as a drain of the transistor, a gate region forming a channel of the transistor, and a second n-type diffusion layer serving as a source of the transistor are sequentially arranged in the vertical direction. A transistor forming portion having a shape;
A first metal wiring disposed on the left or right side of the transistor forming portion in parallel with the transistor forming portion and at a predetermined distance from the surface of the semiconductor substrate, and connected to the drain of the transistor by a contact;
On the semiconductor substrate, on the left side of the transistor formation portion, a square-shaped D-type (Depletion-type) channel implant formed in the left-right direction with a predetermined width and depth;
It is arranged in the left-right direction so as to face the semiconductor substrate surface, so that the region on the left end side faces the surface of the channel implanter, and the region on the right end side faces the gate region portion of the transistor. A floating gate having a rectangular shape, the floating gate being provided with a square-shaped area expansion portion in a left end region facing the surface of the channel implant;
A third n-type diffusion layer adjacent to the left side of the channel implant, formed in the left-right direction with a predetermined width and depth, and serving as a connection terminal to the control gate wiring;
A control gate line disposed in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the floating gate, and connected to the third n-type diffusion layer by a contact;
The semiconductor device is arranged in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the second n-type diffusion layer serving as the source of the transistor, and is connected to the second n-type diffusion layer by a contact. A second metal wiring to be
With
In the arrangement of the memory cells,
Two memory cells are arranged symmetrically so as to share a third n-type diffusion layer serving as a connection terminal of the control gate, and above the two memory cells arranged symmetrically on the left and right The memory cells are arranged symmetrically in the direction and arranged as a memory cell array in the left-right direction with these four memory cells as a unit,
Arranging the memory cell arrays arranged in the horizontal direction in parallel in the vertical direction;
A non-volatile semiconductor memory device. A floating gate type single layer polysilicon non-volatile memory device configured by a standard CMOS process on a semiconductor substrate,
When the first direction on the semiconductor substrate is represented in the up-down direction and the second direction orthogonal to the first direction is represented in the left-right direction,
A first n-type diffusion layer serving as a drain of the transistor, a gate region forming a channel of the transistor, and a second n-type diffusion layer serving as a source of the transistor are sequentially arranged in the vertical direction. A transistor forming portion having a shape;
A first metal wiring disposed on the left or right side of the transistor forming portion in parallel with the transistor forming portion and at a predetermined distance from the surface of the semiconductor substrate, and connected to the drain of the transistor by a contact;
On the semiconductor substrate, on the left side of the transistor formation portion, an n-type well having a predetermined width and depth and formed in the left-right direction;
Arranged so as to face the surface of the semiconductor substrate in the left-right direction, the region on the left end side thereof facing the surface of the n-type well, and the region on the right end side facing the gate region portion A square-shaped floating gate,
A p-type diffusion layer formed adjacent to the left side of the region facing the floating gate of the n-type well and having a predetermined width and depth in the left-right direction and serving as a connection terminal to the control gate wiring;
A control gate line disposed in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the floating gate, and connected to the p-type diffusion layer by a contact;
The second n-type diffusion layer is disposed in the left-right direction at a predetermined distance from the surface of the semiconductor substrate so as to face the second n-type diffusion layer, and is connected to the second n-type diffusion layer by a contact. Metal wiring,
An n-type diffusion layer for applying a desired potential to the n-type well, the region above the p-type diffusion layer and on the left side of the first n-type diffusion layer on the surface of the n-type well A fourth n-type diffusion layer formed at a predetermined position with a predetermined width and depth;
A third metal wiring that is arranged in parallel to the transistor forming portion and spaced from the surface of the semiconductor substrate and connected to the fourth n-type diffusion layer by a contact;
A non-volatile semiconductor memory device comprising: The nonvolatile semiconductor memory element is configured as an OTP (One Time Programmable ROM),
When accumulating charge in the floating gate,
Applying a first voltage to the control gate of the transistor, applying a second voltage to the drain, applying a voltage of "0" V to the source;
Generating hot electrons near the drain of the transistor and injecting the hot electrons into the floating gate;
The non-volatile semiconductor memory device according to claim 20. The nonvolatile semiconductor memory device is configured as an MTP (Multi Time Programmable ROM),
When accumulating charges accumulated in the floating gate,
Applying a first voltage to the control gate of the transistor, applying a second voltage to the drain, applying a voltage of "0" V to the source;
Generating hot electrons near the drain of the transistor, injecting the hot electrons into the floating gate;
When erasing charges on the floating gate,
As the first erasing means,
A voltage of “0” V is applied to the control gate of the transistor, a third voltage is applied to the drain, the source is opened, or a fourth voltage is applied (third voltage> second voltage). 4 voltage),
Means for discharging the floating gate charge by FN current (Fowler-Nordheim tunneling current) by applying a high electric field between the drain and the floating gate;
As the second erasing means performed after the execution of the first erasing means,
“0” V or a fifth voltage is applied to the control gate of the transistor, the third voltage is applied to the drain, and “0” V is applied to the source (third voltage> fifth Voltage),
Means for generating hot electrons near the drain of the transistor and injecting the hot electrons into the floating gate for a predetermined time;
21. The nonvolatile semiconductor memory device according to claim 20, further comprising: The voltage applied to the third metal wiring is configured to be equal to or higher than the voltage of the control gate. 23. Nonvolatile semiconductor memory device. A memory cell array is formed by arranging memory cells, which are floating gate type single-layer polysilicon nonvolatile memory elements formed by a standard CMOS process, on a semiconductor substrate in a matrix at intersections of word lines and data lines. A non-volatile semiconductor memory device comprising:
21. The nonvolatile semiconductor memory element according to claim 20, wherein each of the memory cells includes a fourth n-type diffusion layer and a third metal wiring for applying a desired voltage to the n-type well. It is composed of semiconductor memory elements,
The nonvolatile semiconductor memory device includes:
Based on the number of input / output I / O bits of column address n bits (n ≧ 1) and io bits (io ≧ 1), the memory cell array is arranged in the column direction in the unit of the column address n bits. A plurality of memory cell blocks divided into a number are arranged,
A plurality of bit lines in which the drains of the transistors of the memory cells are commonly connected in the row direction;
A word line provided for each row, the word lines commonly connecting the control gates of the transistors of the memory cells along the column direction;
A source line commonly connected to the sources of the transistors of each memory cell;
A row decoder provided for each row, the row decoder generating a row selection signal for receiving the address signal and selecting the memory cell;
A first level shift circuit that converts a row selection signal output from each row decoder into a signal of a first signal voltage Vp1 applied to the word line;
A column decoder provided corresponding to the number n of bits in the column direction in the memory cell block, wherein n column decoders output a column selection signal for selecting one memory cell from each of the memory cell blocks;
A second level shift circuit for converting a column selection signal output from the column decoder into a signal of a second signal voltage Vp2;
An n-bit unit column selection transistor provided for each of the memory cell blocks, wherein the second signal voltage Vp2 output from the second level shift circuit is used as a gate input, and 1 column from each memory cell block. A column selection transistor for selecting a bit line of one memory cell and selecting a memory cell having the number of I / O bits;
A data input / output line of the number of I / O bits connected to the bit line of the number of I / O bits selected by the column selection transistor via the column selection transistor;
Write that outputs a third voltage signal Vp3 applied to the drain of the transistor through the data input / output line when data write and data erase are performed in response to an input signal of write data of the number of I / O bits A control circuit;
A sense amplifier circuit that amplifies the data of the memory cell read to the data input / output line and outputs the amplified data to the outside;
A non-volatile semiconductor memory device comprising: A non-volatile configuration in which each memory cell, which is a floating gate type single-layer polysilicon non-volatile memory device configured by a standard CMOS process on a semiconductor substrate, is arranged in a matrix at intersections of word lines and data lines A semiconductor memory device,
21. The nonvolatile semiconductor memory element according to claim 20, wherein each of the memory cells includes a fourth n-type diffusion layer and a third metal wiring for applying a desired voltage to the n-type well. It is composed of semiconductor memory elements,
In the arrangement of the memory cells,
For the two memory cells arranged symmetrically on the left and right with the n-type well in common and the two memory cells arranged symmetrically on the left and right, the second metal wiring is shared with each other As a basic unit of arrangement, a total of four memory cells, two memory cells arranged symmetrically in the downward direction,
The four memory cells that are the basic unit of the above configuration are arranged in parallel in the left-right direction, and are also arranged in parallel in the vertical direction,
A non-volatile semiconductor memory device.

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