JP4183290B2 - Nonvolatile semiconductor device having verify function - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a nonvolatile semiconductor memory device having a verify function, and more particularly to a nonvolatile semiconductor memory device having a verifying memory cell.
[0002]
[Prior art]
In a nonvolatile memory such as an EEPROM or a flash memory, it is necessary to confirm whether data has been actually written or erased after the data has been written or erased. This confirmation operation is called verify. The verify is executed by comparing the current of the cell after writing / erasing with the current of the reference cell through a sense amplifier. In general, writing / erasing is performed for a predetermined time, and then verification is executed. When the current value of the cell reaches the specified value by repeating this, the verification is finished and the writing / erasing is finished.
[0003]
Here, it is simply described as write / erase, but generally, the write operation and the erase operation are independent, and the term “erasable verify” is used for the program verify and the erase for the write.
[0004]
[Problems to be solved by the invention]
As the degree of integration of the flash memory increases, the proportion of verification in the writing and erasing operations increases, and the time required for writing or erasing increases. In particular, since program verify is executed in units of bits, it is an impediment to reducing the write time.
[0005]
SUMMARY OF THE INVENTION An object of the present invention is to provide a nonvolatile semiconductor memory device capable of significantly reducing the writing time and erasing time of a highly integrated flash memory.
[0006]
[Means for Solving the Problems]
According to the present invention, a large number of programmable flash memory cells arranged in a matrix, word lines and bit lines connecting the flash memory cells arranged in a matrix, and the flash memory cells arranged in parallel to the flash memory cells are common. Are connected to the word lines , each connected to the word line , each of which is formed in a floating gate type memory structure having a floating gate substantially the same as the flash memory cell, and a verify cell having a different gate couple ratio ; There is provided a non-volatile semiconductor device having a verify function, comprising verify means for verifying the verify cell.
[0007]
According to an embodiment of the present invention, the verifying means includes means for selecting said word line, reads the output of the verify cells from being connected to the word line selected the verify cells via the bit lines And a reading means. A non-volatile semiconductor device is provided.
[0008]
Further, according to an embodiment of the present invention, the reading means, the reference cell for generating a reference signal, a sense amplifier for comparing the output from the reference signal and the verify cell from the reference cells, to include A non-volatile semiconductor device is provided.
[0009]
Furthermore, according to an embodiment of the present invention, there is provided a non-volatile semiconductor device, wherein the verify cell includes a first column and a second column verify cell in parallel with the flash memory cell. .
[0010]
[Action]
Verify cells can verify the memory cell connected to a word line simply by verifying, since verification is possible for each word line can significantly reduce the verify time.
[0011]
【Example】
A nonvolatile semiconductor device according to one embodiment of the present invention will be described below with reference to the drawings.
[0012]
As shown in FIG. 1, in a nonvolatile semiconductor device according to an embodiment of the present invention, a nonvolatile memory cell, and in the example shown in FIG. 1, a flash memory cell 2nk into which bit data is written and erased is X Arranged in row Y column. One column of verify cells 4n for verifying the flash memory cells 2nk arranged in the X rows and Y columns is added. The memory cell 2nk and the verify cell 4n are formed in a floating gate type memory structure having substantially the same floating gate as will be described later, but are manufactured so that their gate couple ratios are different. As shown in FIG. 1, the control gates of the memory cell 2nk and the verify cell 4n are connected to the X-decoder 10 via the word lines WLi, WLi + 1, WLi + 2,. , Bit lines BLi, BLi + 1,..., And bit line selection transistors 8n are connected to the write and sense amplifier 6, and the source of the memory cell 2nk is connected to the ground via the source lines SLi, SLi + 1,. It is connected. The gate of the transistor 8n for bit line selection is connected to the Y decoder 12.
[0013]
The drain of the verify cell 4n is connected to the verify sense amplifier 14 via the bit line BLvi and the bit line selection transistor 8v, and the source of the verify cell 4n is grounded via the source line SLvi in the same manner as the memory cell 2nk. It is connected to the. The sense amplifier 14 is connected to the output side of a reference cell 16 having the same structure as the memory cell 2nk or the verify cell 4n.
[0014]
The memory cell 2nk and the verify cell 4n shown in FIG. 1 are formed in an EEPROM structure as shown in FIGS. That is, as shown in FIGS. 2 and 3, in these cells 2nk and 4n, a p-type silicon substrate 20 is doped with n-type impurity ions to form a drain region 21 and a source as a high concentration impurity diffusion region (n +). Region 22 is formed. A tunnel oxide film 23 is formed on the silicon substrate 20 including the drain and source regions 21 and 22. A floating gate 24 made of a polysilicon film is formed on the channel region between the source and drain regions 21 and 22 and on the tunnel oxide film 23. On the tunnel oxide film 23 other than the floating gate 24, an interlayer insulating film 25 made of silicon oxide is formed.
[0015]
A cap 26 (Cap) made of polysilicon is formed so as to cover the exposed surface of the floating gate 24 and to cover the region above the surface of the interlayer insulating film 25 and above the source and drain regions 22 and 21. On the cap 26 and the interlayer insulating film 25 , an ONO film 27 as an insulating layer having a structure in which silicon oxide / silicon nitride is stacked is formed on the surface of the interlayer insulating film 25 including the cap 26. ing. On the ONO film 27, a control gate 28 made of polysilicon is formed.
[0016]
The dimensions of the cap 26 are different between the memory cell 2nk and the verify cell 4n shown in FIGS. That is, in the memory cell 2nk shown in FIG. 2, the cap 26 has a length Lx1 along the direction in which the source region 22 and the drain 21 region are arranged, and a direction orthogonal to the direction in which the source region 22 and the drain region 21 are arranged. It has a length Ly1 along, and has a substantially rectangular cap area S1 (= Lx1 × Ly1) represented by Lx1 × Ly1. On the other hand, in the verify cell 4n shown in FIG. 3, the length Lx2 along the direction in which the source region 22 and the drain region 21 are arranged, and the length along the direction orthogonal to the direction in which the source region and the drain region are arranged. And a substantially rectangular cap area S2 (= Lx2 × Ly2) represented by Lx2 × Ly2. As apparent from the comparison between FIG. 2 and FIG. 3, the cap length Lx1 of the memory cell 2nk is set larger than the cap length Lx2 of the verify cell 4n. Since the cap length Ly1 of the memory cell 2nk is set equal to the cap length Ly2 of the verify cell 4n, the cap area S1 of the memory cell 2nk is larger than the cap area S2 of the verify cell 4n.
[0017]
In the memory cell 2nk and verify cell 4 n having a structure as described above, the gate couple ratio of the verify cell 4n is set smaller than the gate couple ratio of the memory cell 2nk. The gate couple ratio is defined by the capacitance between the channel region and the floating gate 24 and the capacitance between the floating gate 24 and the control gate 28 . In the memory cell 2nk and the verify cell 4n shown in FIGS. 2 and 3, since the area where the channel region and the floating gate 24 face each other is the same, the capacitance between the channel region and the floating gate 24 is the same. . In contrast, in the memory cell 2nk and verify cells 4 n, the area S1, S2 of the floating gate 24 and control gate 28 is opposed, unlike the floating gate 24 towards the memory cell 2nk is compared to verify cell 4 n and large area S1 to the control gate 28 is opposed and therefore, towards the memory cell 2nk the capacitance between the floating gate 24 and control gate 28 is larger than the verify cell 4 n. Gate couple ratio of the memory cell 2nk is larger than the gate couple ratio of the verify cell 4 n.
[0018]
As described above, the verify cell 4n having a different gate coupling ratio from the memory cell 2nk is incorporated in the semiconductor device, and the word lines WLi, WLi + 1,. The memory cell 2nk of... Can be verified.
[0019]
The cells having different gate couple ratios described above are simply formed by adjusting the area of the tunnel oxide film portion of the cell and the surface area of the floating gate. That is, the structures shown in FIGS. 2 and 3 are those shown in US patents 4, 833, and 514 of TI. However, the polysilicon caps indicated by the oblique lines are changed from the array cell to the verify cell by the device on the photomask. Obviously, a shorter cell can be obtained with a smaller gate-couple ratio.
[0020]
Generally, writing or erasing to the flash memory cell 2nk is performed by Fowler node Heim tunnel current (hereinafter referred to as FN current) or hot electron injection (hereinafter referred to as HE injection). A verify cell 4n having a gate coupling ratio smaller than that of the array memory cell 2nk is prepared. Electron injection characteristics to each floating gate 24, electron extraction characteristics from the floating gate 24, and electron injection characteristics of hot electrons to the floating gate 24 Is as shown in FIGS. 4 (a), 4 (b) and 4 (c). FIG. 4 (a), (b) and (c) As is clear from F - in even HE injection in N current, towards the large array cell gate couple ratio fast change of the threshold Vth, and after a predetermined time has elapsed , it can be seen that the respective threshold is different. Utilizing this property, the memory cell 2nk connected to each of the word lines WLi, WLi + 1, WLi + 2,... Only by verifying program writing to the verify cell 4n and program erasure from the verify cell 4n. Can be verified.
[0021]
First, program verification will be described.
[0022]
First, a write operation is performed. That is, the word line WLi bit line BLi of the memory cell 2nk want to write with the writing selection voltage is applied is selected by X decoder 10 to the word line WLi, connected to BLi + 1 ... bit line BLvi either the verify cell 4n selectivity transistor 8v, 8n is selected by the Y decoder 12, the bit line BLi, BLi + 1 ... write voltage to one bit line BLvi is applied. In this manner, data, for example, data “1” is written into the memory cell 2nk and the verify cell 4n to be written. In this write operation, a selection voltage and a write voltage are applied for a certain period of time, and threshold values in a predetermined range are given to the memory cell 2nk and the verify cell 4n, respectively.
[0023]
A verify operation is started after this write operation. In the verify operation, the verify cell 4n of the word line WLi to which the programmed memory cell 2nk is connected is selected by the X decoder 10 and a verify voltage is applied. This verify voltage corresponds to the threshold voltage of the verify cell 4n programmed as described later. Thereafter, the Y decoder 12 selects the selection transistor 8v connected to the bit line BLvi. Therefore, the output from the programmed verify cell 4n is supplied to the sense amplifier 14. During the verify operation, the reference cell 16 is also turned on, so that a reference output is supplied from the reference cell 16 to the sense amplifier 14. In the sense amplifier 14, the reference output and the output from the verify cell 4n are compared. Here, when the verify cell 4n is correctly programmed, for example, the level of the output from the verify cell 4n is larger than the level of the reference output, which means that the sense amplifier 14 has correctly programmed. Output "1" is output. If the verify cell 4n is not programmed correctly, for example, the output level from the verify cell 4n is lower than the reference output level, which means that the sense amplifier 14 is not programmed correctly. Output “0” is output.
[0024]
The erase verify is executed as follows in substantially the same manner as the write verify. Here, the erase operation is executed for each common source or common well. That is, the erase gate voltage is applied to the word lines WLi, WLi + 1,... And the erase well voltage or erase voltage is applied to the common well or the common source, or the erase well voltage and the common source are respectively applied to the common well and the common source. An erase voltage is applied. In this way, the data in the memory cell 2nk and the verify cell 4n are erased. In this erasing operation, a selection voltage and an erasing voltage are applied for a predetermined time, and threshold values in a predetermined range are given to the memory cell 2nk and the verify cell 4n, respectively.
[0025]
After this erase operation, the verify operation is started. In the verify operation, verify cells 4n from which data has been erased are successively selected by the X decoder 10 and a verify voltage is applied. This verify voltage corresponds to the threshold voltage of the verify cell 4n at the time of erasure as will be described later. When the selection transistor 8v connected to the bit line BLvi is selected by the Y decoder 12, the output from the erased verify cell 4n is supplied to the sense amplifier 14. In this verify operation, the reference output from the reference cell 16 that is turned on is compared with the output from the verify cell 4n by the sense amplifier 14. Here, when the verify cell 4n is correctly erased, for example, the level of the output from the verify cell 4n is smaller than the level of the reference output, which means that the sense amplifier 14 has erased correctly. Output “0” is output. When the verify cell 4n is not erased, for example, the output level from the verify cell 4n is larger than the reference output level, and the sense amplifier 14 indicates that the verify cell 4n is not erased correctly. “1” is output. In this way, it is verified whether or not all of the verify cells 4n are erased.
[0026]
As described above, by verifying the verify cell 4n, the program or erase of the memory cell 2nk sharing the verify cell 4n and the word line WLi is verified. This is based on the following reasons.
[0027]
FIG. 5A shows the distribution of threshold values of a large number of cells, the horizontal axis shows the cell count corresponding to the number of cells, and the vertical axis shows the threshold voltage Vth. Graphs A1 and B1 show the threshold distributions of the memory cell 2nk and the verify cell 4n at a certain point in time when electrons are injected into the floating gate 24, respectively. Graphs A2 and B2 show threshold value distributions of the memory cell 2nk and the verify cell 4n at a certain point in time when electrons are extracted from the floating gate 24, respectively.
[0028]
As apparent from the graphs A1 and B1 in FIGS. 4A and 5A, when electrons are injected into the floating gate 24, if the threshold value of the verify cell 4n rises to a certain value, the gate couple ratio is verified. The memory cell 2nk larger than the cell reaches a higher threshold level because the threshold change is faster than that of the verify cell 4n. Therefore, if it is checked whether the verify cell 4n conducts at the threshold value, the other memory cell 2nk has a predetermined threshold value that is larger than the threshold value of the verify cell 4n. It is not necessary to check whether or not the memory cell 2nk corresponding to 4n becomes conductive at the threshold value.
[0029]
As is clear from graphs A2 and B2 in FIGS. 4B and 5A, when electrons are extracted from the floating gate 24, if the threshold value of the verify cell is lowered to a certain value, the gate couple ratio is increased. The array cell larger than the verify cell reaches a lower threshold level because the threshold change is faster than the verify cell. Therefore, if it is checked whether the verify cell 4n conducts at the threshold value, the other memory cell 2nk has a predetermined threshold value that is smaller than the threshold value of the verify cell 4n. It is not necessary to check whether or not the memory cell 2nk corresponding to 4n becomes conductive at the threshold value. From this principle, only the verify of the memory cell 2nk 1 single tone bell to verify cell 4n to the bit sharing the word line WL, so that is ensured.
[0030]
Even when hot electrons are injected into the floating gate 4n, the distribution is similar to that shown in the graphs A1 and B1 in FIG. 5A. Therefore, hot electrons are injected and data is written into the memory cell 2nk. In this case, even in the case of erasing, the memory cell 2nk can be verified simply by verifying the verify cell 4n.
[0031]
Here, if the reference cell 16 is formed in the array memory cell 2nk the same type as the cell was equal gate couple ratio of the reference cell 16 to the gate couple ratio of the array memory cell 2nk may adjust the offset between the verify cell 4n Therefore, it is necessary to check the sense ratio adjustment of the sense amplifier 14 for the TEG process. If the reference cell 16 is also the same type as the verify cell 4n, the adjustment is easy.
[0032]
From the above, the following applications are possible.
[0033]
(1) A bit line composed of a verify cell 4n having a larger gate couple ratio than that of the array cell 2nk is added.
[0034]
This verify cell 4n can be used for over-erase and over-program check. That is, the threshold distribution of the verify cells 4n and array cells 2nk as shown in FIG. 5 (b) Tsu Unlike FIG 5 (a). That is, when the electrons are injected into the floating gate 24, the relationship between the threshold values of the memory cell 2nk and the verify cell 4n at a certain point in time, as is clear from the graphs C1 and D1, In the verify cell 4n having a gate couple ratio larger than that of the memory cell 2n, the threshold value changes faster than the memory cell 4n, so that a higher threshold level is reached. In addition, when the electrons are extracted from the floating gate 24, the relationship between the threshold values of the memory cell 2nk and the verify cell 4n at a certain point in time, as is clear from the graphs C2 and D2, is as follows. The verify cell 4n having a gate couple ratio larger than the memory cell 2nk reaches a lower threshold level because the threshold change is faster than that of the memory cell 2nk.
[0035]
Using this property, the verify cell 4n shown in FIG. 1 can be used for overerasing and overprogramming the memory cell 2nk by making the gate couple ratio larger than that of the array cell 2nk.
[0036]
(2) In the circuit shown in FIG. 1, the memory cells are classified into first and second memory cells having different thresholds, and the first and second gate couple ratios are smaller than those of the first and second memory cells. A multilevel memory can be dealt with by adding two or more bit lines made of verify cells.
[0037]
When a multilevel memory is produced by changing the voltage applied to the word line , the first level is verified by the first verify cell, and the second level is verified by the second verify cell. At this time, the gate couple ratios of the first verify cell and the second verify cell are not necessarily the same.
[0038]
【The invention's effect】
Since program verify and erase verify can be performed only by a verify cell or a verify bit line , writing time and erasing time of a highly integrated flash memory can be greatly shortened.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a circuit configuration of a nonvolatile semiconductor device according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view schematically showing a structure of a flash memory cell shown in FIG.
FIG. 3 is a cross-sectional view schematically showing a structure of a verify cell shown in FIG. 1;
4A, 4B, and 4C are graphs showing electron injection characteristics, electron extraction characteristics, and hot electron injection characteristics of a flash memory cell and a verify cell, respectively.
FIGS. 5A, 5B, and 5C are graphs showing threshold distributions for a large number of cells when the gate couple ratio is changed in a flash memory cell and a verify cell, respectively.
[Explanation of symbols]
2 nk ... flash memory cell 4 n ... verify cells WLi, WLi + 1, WLi + 2, ... word lines BLi, BLi + 1, ... bit lines 8n, 8v ... bit selection transistors SLvi ... source lines 16 ... reference cells 20 ... substrate 21 ... Source region 22 ... Drain region 23 ... Tunnel oxide film 24 ... Floating gate 26 ... Cap 28 ... Control gate

Claims (4)

A large number of programmable flash memory cells arranged in a matrix;
A word line and a bit line connecting the flash memory cells arranged in a matrix;
Formed in a floating gate type memory structure that is arranged in parallel to the flash memory cell and connected by a common bit line, each connected to the word line, and each having a floating gate substantially the same as the flash memory cell. And verify cells with different gate-couple ratios ,
Verify means for verifying the verify cell;
A non-volatile semiconductor device having a verify function, comprising: The verifying means includes:
Means for selecting said word lines,
Reading means for reading an output of the verify cells from connected to the selected said word line said verification cell via the bit line,
The nonvolatile semiconductor device according to claim 1, comprising: The reading means includes
A reference cell for generating a reference signal;
A sense amplifier for comparing the output from the reference signal and the verify cell from the reference cell,
The nonvolatile semiconductor device according to claim 2, comprising: The verify cell includes a first column and a second column verify cell in parallel with the flash memory cell;
The nonvolatile semiconductor device according to claim 1.

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