WO2005050665A1

WO2005050665A1 - Semiconductor integrated circuit

Info

Publication number: WO2005050665A1
Application number: PCT/JP2003/014715
Authority: WO
Inventors: Tomomichi Wada; Teruhiko Ito; Takeaki Wada; Tatsuya Miyake; Minoru Soma
Original assignee: Renesas Technology Corp.
Priority date: 2003-11-19
Filing date: 2003-11-19
Publication date: 2005-06-02

Abstract

A semiconductor integrated circuit (1) comprising a plurality of nonvolatile memory cells (MC) in which the threshold voltage can be altered reversibly by electrically injecting/discharging charges, and a circuit (8) for controlling alteration of the threshold voltage of the plurality of nonvolatile memory cells, wherein the control circuit differentiates the threshold voltage distribution being obtained by initializing the threshold voltage of predetermined nonvolatile memory cells among the plurality of nonvolatile memory cells from the threshold voltage distribution being obtained by initializing the threshold voltage of the remaining nonvolatile memory cells. When a required read margin is ensured using a boosted voltage as the word line select level for the remaining nonvolatile memory cells, a similar read margin can be ensured for the predetermined nonvolatile memory cells without using a boosted voltage as the word line select level and a normal read operation can be carried out even if boost operation is not finished when power is turned on.

Description

Description Semiconductor integrated circuit technology

The present invention relates to a semiconductor integrated circuit having a nonvolatile memory cell whose threshold voltage can be reversibly changed by electric charge injection and charge discharge, and stores information necessary for internal operation such as trimming data. The present invention relates to a technology that is effective when applied to a read access immediately after power-on to a part of the flash memory area. Background art

A nonvolatile memory cell whose threshold voltage can be reversibly changed by electric charge injection and charge discharge has an erased state and a written state. For example, the erased state is a state where the threshold voltage seen from the selected terminal of the memory cell is low, and the written state is a state where the threshold voltage seen from the selected terminal of the memory cell is high. The selection terminal of the above-mentioned nonvolatile memory cell is connected to a node line, and the erasing operation for lowering the threshold voltage of the above-mentioned nonvolatile memory cell is performed on all the memory cells connected to the selected node line. Done. For example, in the case of a non-volatile memory cell having a floating gate structure, a high voltage is applied to a read line, and electrons stored in a floating gate are emitted toward a source line or a substrate (a well region). At this time, since the erase characteristics of each memory cell are different, when the threshold voltage of the memory cell with the slowest erase characteristic reaches the erase verify level, the memory cell with the fast erase characteristic is in the debate state (over-erased state). Things are often there. The threshold voltages of all memory cells connected to the selected ground line are After the level becomes lower than the level, the memory cell having a threshold voltage lower than the lower limit of the target erase distribution is selectively written, and a process of aligning the lower limit of the erase distribution (write-back process) is performed. Through this processing, the depleted state is eliminated. As described above, in order to initialize the threshold voltages of a plurality of nonvolatile memory cells, two processes, a process of lowering the threshold voltage (erase process) and a process of aligning the lower limit of the threshold voltage distribution (write-back process), are performed. Is desirable.

Patent Document 1 (Japanese Unexamined Patent Publication No. 2000-26089) discloses a technique for dealing with over-erasing as a technique for over-erasing all memory cells connected to a selected bit line after an erasing operation. A leak check is performed to detect that the sum of the leak currents is equal to or lower than a predetermined level.If the leak check result is not 0 K, the temporary erase operation is stopped, a weak write is performed to the memory cell in an over-erased state, and A control sequence is provided for returning to the erase operation. Disclosure of the invention

The present inventor has studied a read access immediately after power-on to a part of the flash memory area for storing information necessary for internal operation such as trimming. That is, the partial memory area replaces a conventional program circuit including a laser fuse circuit and an electric fuse circuit, and is called a flash fuse or the like. Flash fuses can be reversibly changed in threshold voltage by electric charge injection and charge discharge, similar to the non-volatile memory cells that make up a normal storage area. In the flash fuse, necessary trimming data and rescue data are written in a probe inspection process, and a part of the trimming data is rewritten. Since the trimming data and the rescue data written in the flash fuse are data necessary for internal operation, the power of the flash memory It is necessary to read at the time of ON. Normally, in a read operation, in order to increase the amount of a signal read to a bit line, a word line is selected using a boosted voltage obtained by boosting a power supply voltage by a booster circuit. However, at power-on, it is not enough to boost the common line voltage, so that the common line voltage becomes lower than the specified boosted voltage. Therefore, the present inventor has found that the threshold voltage distribution in the erased state of the flash fuse needs to be lower than the threshold voltage distribution in the erased state of the flash memory cell for normal operation. Was found. In order to obtain such a threshold voltage distribution, it has been clarified by the present inventors that there is a problem to be solved further.

The first is to save time. In other words, although the threshold voltage distribution for erasing is lower than the threshold voltage distribution for flash memory cells in normal operation, the threshold voltage cannot be set lower than normal by the erase command for flash memory cells in normal operation. If, instead, the erasure and the erase verification are specified by individual commands and manual erasure is repeated many times, the total processing time increases, and the test time required for the probe inspection process increases.

The second is to suppress over-erasure of the memory cells. That is, since the write-back process is not performed in the manual erasure, over-erase may occur in some memory cells, and rewriting to the flash fuse becomes impossible due to the influence of the over-erased memory cells. For example, a non-volatile memory cell in a debit state is in a state where current can flow or is in an on state even when a read line is not selected.However, a flash fuse shares a sub-bit line to increase the reliability of information storage. Multiple non-volatile memory cells are the same In the storage state, complementary information storage is performed using two sub-bit lines, and in the read operation, the plurality of memory cells that are complementary storing information are selected in parallel, so that erasing is performed. Undesired data inversion does not occur even if over-erasure occurs in some memory cells during the process. However, when the memory information is rewritten, the over-erased memory cells cannot be changed to the write state, and when the number of nonvolatile memory cells increases, information is stored in a complementary manner in a plurality of bits of nonvolatile memory cells. However, information cannot be stored and read accurately.

An object of the present invention is to provide a semiconductor integrated circuit capable of reducing a threshold voltage setting processing time for a specific nonvolatile memory cell provided for a flash fuse or the like.

Another object of the present invention is to provide a semiconductor integrated circuit capable of suppressing the occurrence of an excessive charge release state such as over-erasing of a specific nonvolatile memory cell provided for a flash fuse or the like. .

Still another object of the present invention is to provide a semiconductor integrated circuit capable of suppressing occurrence of abnormal rewriting of stored information in a specific nonvolatile memory cell provided for a flash fuse or the like.

The above and other objects and novel features of the present invention will become apparent from the following description of the present specification and the accompanying drawings. Disclosure of the invention

[1] A semiconductor integrated circuit according to the present invention includes: a plurality of nonvolatile memory cells whose threshold voltage can be reversibly changed by electric charge injection and charge discharge; and a threshold voltage of the plurality of nonvolatile memory cells. A control circuit for controlling a change in voltage, wherein the control circuit is configured to perform a threshold voltage process for initializing a threshold voltage for a predetermined nonvolatile memory cell of the plurality of nonvolatile memory cells. The difference between the value voltage distribution and the threshold voltage distribution by the process of initializing the threshold voltage for the remaining nonvolatile memory cells is provided. From the above, when a necessary read margin is secured for the remaining nonvolatile memory cells by using the boosted voltage at the node line selection level, the node line selection is performed for the predetermined nonvolatile memory cells. A similar read margin can be secured without using a boosted voltage for the level or before the power supply voltage is stabilized. In short, a read operation can be normally performed on a predetermined nonvolatile memory cell even if the boost operation has not been completed at power-on.

As a specific mode of the present invention, the initialization processing includes an erasing operation for releasing electric charges and a writing operation for injecting electric charges into an overerased nonvolatile memory cell. The difference in the threshold voltage distribution due to the embedding process is defined by the difference in the verify voltage accompanying the erasing and writing. This makes it possible to suppress over-erasure of the predetermined nonvolatile memory cell, and to suppress occurrence of an abnormal rewrite of stored information in the predetermined nonvolatile memory cell.

As a more specific embodiment of the present invention, the threshold voltage distribution by the initialization process for the predetermined nonvolatile memory cell is smaller than the threshold voltage distribution by the initialization process for the remaining nonvolatile memory cells. Cloth. The predetermined non-volatile memory cell constitutes a storage area dedicated for storing information necessary for the internal operation of the semiconductor integrated circuit. The information necessary for the internal operation is the trimming and rescue. [2] A semiconductor integrated circuit according to another aspect of the present invention includes: a first memory region including a plurality of nonvolatile memory cells each of which is capable of reversibly changing a threshold voltage by electric charge injection and charge release; A second memory area; and a control circuit for controlling a change in a threshold voltage of the nonvolatile memory cell. Above The control circuit performs a process of initializing a threshold voltage for the nonvolatile memory cell in the first memory area in response to the first initialization command, and performs the process of initializing the second voltage in response to the second initialization command. A process for initializing the threshold voltage is performed on the nonvolatile memory cells in the memory area. The initialization process includes an erasing operation for releasing electric charges and a writing operation for injecting electric charges into an overerased nonvolatile memory cell, and the control circuit performs erasing and writing operations according to the first command. And a verify voltage for the erase and write by the second command.

As described above, when a necessary read margin is secured to the nonvolatile memory cells in the second memory area by using the boosted voltage at the word line selection level, the word is stored in the nonvolatile memory cells in the first memory area. A similar read margin can be secured even without using a boosted voltage for the line selection level or before the power supply voltage is stabilized. Furthermore, over-erasure of the nonvolatile memory cells in the first memory area can be suppressed, and occurrence of abnormal rewriting of stored information in the nonvolatile memory cells in the first memory area can be suppressed.

As a specific mode of the present invention, a verify voltage according to the first command is lower than a verify voltage according to the second command. In addition, a booster circuit that boosts an external power supply voltage and outputs a boosted voltage is provided, and in a read operation, a word line of the nonvolatile memory cell is set to a selected level based on a boosted output of the booster circuit. The first memory area is a storage area dedicated for storing information necessary for internal operation of the semiconductor integrated circuit. The information required for the internal operation is a trimming operation and a relief operation. Further, there is provided a register for reading stored information from the first memory area in response to power-on. Brief Description of Drawings

FIG. 1 is a block diagram illustrating a flash memory according to an example of the present invention.

FIG. 2 is a circuit diagram illustrating a circuit for generating an erase verify voltage. FIG. 3 is a circuit diagram showing an example of a flash fuse circuit and a fuse latch circuit.

FIG. 4 is a longitudinal sectional view schematically illustrating the sectional structure of a nonvolatile memory cell having a floating gate structure.

FIG. 5 is a flowchart illustrating an initialization operation procedure for a nonvolatile memory cell.

FIG. 6 is an explanatory diagram of a threshold voltage distribution when an erase bias is applied.

FIG. 5 is an explanatory diagram of the threshold voltage distribution when the erase verify fails.

FIG. 8 is an explanatory diagram of the threshold voltage distribution when the erase verify passes.

FIG. 9 is an explanatory diagram of a threshold voltage distribution when performing write back. FIG. 10 is an explanatory diagram illustrating an erase threshold voltage distribution according to a first initialization command, an erase threshold voltage distribution according to a second initialization command, and an erase threshold voltage distribution according to manual erasure.

FIG. 11 is an explanatory diagram of manual erasure. BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 shows a flash memory 1 according to an example of the present invention. Flash memory 1 is formed on a single semiconductor substrate such as single crystal silicon, and has a memory array (MRY) 2, an address decoder / dryno, (DEC / D V) 3, Sense latch row (SA) 4, Column switch row (CSW) 5, Power supply circuit (POWG) 6, Interface circuit (IOIF) 7, Control circuit (CTRL) 8, Flash fuse circuit (FFS) 9, a fuse latch circuit (FLAT) 10, and a pad row 11. The memory array 2 has a large number of nonvolatile memory cells MC whose threshold voltage can be reversibly changed by electrical erasing and writing. In this specification, erasing means lowering the threshold voltage of the nonvolatile memory cell MC, and writing means raising the threshold voltage of the nonvolatile memory cell. The non-volatile memory cell MC has, for example, a stacked gate structure having an insulating gate and a control gate which are respectively insulated on a channel region between a source and a drain. The control gate of the nonvolatile memory cell MC is connected to the word line WL, the drain is connected to the bit line BL, and the source is connected to the source line SL. The selection of the lead line and the selection of the bit line by the column switch column 7 are performed based on the decode signal from the decoder driver 3 which decodes the address signal. One end of the bit line BL is connected to the sense latch of the sense latch train 4. The data read from the non-volatile memory cells by the word line selection in the read operation is detected by using the sense latch of the sense switch row 4, and the data is read in accordance with the access unit such as the byte or pad selected by the column switch row 5. The signal is transmitted to the interface circuit 7. The erase operation is not particularly limited, but is performed in a unit of a single line. In the write operation, the write data input to the interface circuit 7 is latched in the sense latch row 4 via the column switch row 5, and the write voltage is applied in accordance with the logical value of the data latched in the sense latch row 4. And the application inhibition is controlled.

The power supply circuit 6 charges an operating power supply such as a high voltage required for erasing and writing to the flash memory 1 and a word line boosted voltage required for reading. It is generated using a booster circuit including a pump circuit and a resistor voltage divider circuit. The flash fuse circuit 9 is constituted by the same memory transistors as the nonvolatile memory cells MC of the memory array 2, and holds trimming data and relief data necessary for the internal operation of the flash memory. Although not specifically shown, the memory array 2 has a redundant code line and a redundant bit line used for repairing a defective address, the decoder / driver 3 has a switching circuit for replacing the defective address with the redundant address, and the switching circuit is When detecting access to the specified defective address in the rescue operation, the memory cell of the redundant address is switched to the access target instead of the defective address and controlled. The power supply circuit 6 generates a high voltage and a verify voltage used for writing and erasing by using a charge pump circuit and a resistor voltage divider circuit, etc., but the full scale voltage of the resistor voltage divider circuit due to process variations and the like. And the offset voltage may vary. A trimming circuit is provided to compensate for such variations, and this trimming circuit selects a flip-flop designated by the trimming data and compensates for the variation. Relief data and trimming data read from the flash fuse circuit 9 are held, and the held data is transmitted to a corresponding redundancy switching circuit or trimming circuit.

The control circuit 8 controls the timing of erasing, writing, reading, etc. of the flash memory 1 in accordance with a strobe signal and a command input from the outside, and controls selection of an operating power supply required at that time. Further, the control circuit 8 reads the relief data and the trimming data from the flash fuse circuit 9 in response to the power-on, and loads the data into the fuse latch circuit 10. Power-on detection may be performed by the power supply circuit 6 itself, or may be detected by an external strobe signal. Pad 1 1 is connected to the external connection terminal. It has a bonding pad and an input / output buffer.

The commands include an erase command, an erase verify command, a write command, a write verify command, a read command, and an initialization command. For example, an erase command is specified by an address. A command to apply an erase voltage to a batch erase area in units of a single line. An erase verify command is used to erase nonvolatile memory cells in the batch erase area specified by an erase command. This command is used to determine whether or not everything is in the erased state. A write command is a command for selectively applying a write voltage to a non-volatile memory cell of a write unit such as a byte specified by an address according to a write time, and a write verify command is a write command for applying a write voltage. This is a command for determining whether or not the nonvolatile memory cell is in a write state. The read command is a command for reading the storage information of the memory cell specified by the address to the outside.

'The initialization command is a so-called automatic erase (auto erase) command, in which an erase voltage is applied to the nonvolatile memory cells in the batch erase area specified by the address, and the erase voltage is applied. Verification is performed to determine whether the non-volatile memory cell has entered the threshold voltage distribution in the erased state, and furthermore, a write voltage is applied to the over-erased non-volatile memory cell to perform a write-back operation to increase the threshold voltage. . By using this initialization command, it is possible to prevent some of the non-volatile memory cells from being over-erased and remaining. In particular, since the flash fuse circuit 9 has an initialization command (first initialization command) for nonvolatile memory cells and an initialization command for the memory array 2 (second initialization command) separately, Also in the fuse fuse circuit 9, occurrence of over-erasure can be suppressed. In particular, the verify voltage (erase verify voltage) of the first initialization command is used. Voltage and write-back verify voltage) are lower than the verify voltages (erase verify voltage and write-back verify voltage) of the second initialization command. Therefore, in a read operation, a necessary read margin is secured by using a boosted voltage to a nonvolatile memory cell of the memory array 2 at a read line selection level, but the nonvolatile memory cell of the flash fuse circuit 9 is secured. In contrast, the same read margin can be ensured without using the boosted voltage as the read line selection level or before the power supply voltage is stabilized. This makes it impossible to boost the lead line voltage at power-on, so that a sufficient read margin can be secured even if the lead line voltage is equal to or lower than the specified boost voltage. At the same time, it is possible to prevent the relieved data that is sometimes input from the flash fuse circuit 9 to the fuse latch circuit 10 and the inversion of the undesired logic value during the trimming operation, and to improve the reliability of the loaded data. I can do it.

FIG. 2 illustrates an erase verify voltage generation circuit 12. 13 is a band gap circuit which generates a stable voltage VBGR independent of temperature and power supply voltage. Reference numeral 14 denotes a voltage level conversion circuit, which is composed of a differential amplifier 15, a P-channel MOS transistor MP1, resistors R1, R2, R3, and a switch 16, and should be erased based on the voltage VBGR. Generates the verify voltage VeVfy. Use the selection signal SEL 1 to change the position of the tap to extract the erase verify voltage V evfy. At the time of erasure verification in the first initialization command, the connection between R2 and R3 is selected, and at the time of erasure verification in the second initialization command, the connection between R1 and R2 is selected. The power supply circuit 6 has an erase verify voltage generation circuit 12. Although not shown, a circuit for generating a write-back verify voltage can be similarly configured. FIG. 3 shows an example of the flash fuse circuit 9 and the latch circuit 10 for the fuse.

The flash fuse circuit 9 has a NOR type memory array configuration. The bit line BL as a sub-bit line is connected to the main bit line MBL via a separate MOS transistor MN2. Main bit line MSL is shared with memory array 2. The figure typically shows a pair of bit lines BL. The drains of a plurality of nonvolatile memory cells MC are connected to each bit line BL, and the sources are commonly connected to a source line SL. The control gate is connected to the lead line WL. A load MOS switch MN3 constituting a read load circuit is connected to the bit line BL. ø3 is the switch signal of the load MOS switch MN3.

The fuse latch circuit 10 is connected to the bit line BL by the transfer MOS transistor MN4. The pair of bit lines BL are used as complementary bit lines and are connected to the corresponding differential input terminals of the static clutch LAT. The relief data and trimming data latched in the static latch LAT are supplied to the corresponding circuit in a single end. ø2 is a switch signal of the transfer MOS transistor MN4, and ø3 is an activation signal of switch LAT.

One-bit information storage by the flash fuse circuit 9 is performed differentially using a plurality of nonvolatile memory cells MC connected to a pair of left and right bit lines. In short, non-inverted data is stored in parallel in all nonvolatile memory cells connected to one bit line, and inverted data is stored in parallel in all nonvolatile memory cells connected to the other bit line. And complementarily store information. In the figure, all the non-volatile memory cells on the left bit line BL are in a write state, and all the non-volatile memory cells on the right bit line BL are in an erase state. In read operation, all word lines are selected Is done. In the read operation, the separation MOS transistor Ml is turned off, the transfer MOS transistor MN3 and the load MOS switch MN4 are turned on, the static latch LAT is activated, and the stored information read out to the bit line is scanned.ヅ Clutch LAT launches. After latching, the transfer MOS transistor MN3 and the load MOS switch MN4 are turned off.

The flash fuse circuit 9 uses a nonvolatile memory cell so as to enable complementary information storage with a plurality of bits, for example, 16 bits, on one side for each one-bit data. It is possible to secure a margin against inversion of data due to data and malfunction due to noise. For example, even if a 1-bit nonvolatile memory cell in the written state changes its characteristics to the erased state, the amount of current caused by the change does not exceed the amount of current flowing to the opposite bit line. Even if one bit in the erased state is in an over-erased state, other memory cells sharing the bit line BL with the over-erased state are in the erased state, so there is no problem in reading data. Actually, since the first initialization mode is used, over-erasure does not occur, and therefore, rewriting a plurality of parallel bits in the erased state to the write state is not hindered. If over-erasure occurs in a portion of a plurality of parallel bits, the over-erased memory cell does not escape from the erased state even when rewritten to the write state, and the stored information may be undesirably inverted.

FIG. 4 illustrates a schematic cross-sectional structure of a nonvolatile memory cell MC having a floating gate structure. A drain 21 and a source 22 are formed in the well region 2 ◦, and a floating gate 25 and a control gate 27 are sequentially formed on the channel region 23 therebetween through the gate insulating layers 24 and 26, respectively. Is formed. Drain 21 is connected to bit line BL, source 22 is connected to source line SL, and control gate 27 is connected to lead line WL. It is.

Here, the relationship between the voltages applied to the nonvolatile memory cell MC at the time of erasing, writing, and reading will be described. The external operating power supply voltage VDD is, for example, 3.3V. For example, in reading, Vd (drain voltage) = 1 V, Vcg (control gate voltage) = 3.8 V, Vs (source voltage) = 0 V, and Vsub (substrate voltage) = 0 V. In the erase operation, Vd = OP (floating), Vcg = —llV, Vs = OP, and Vsub = 10.5 V. Due to this erase voltage relationship, electrons injected into the floating gate are emitted to the substrate (well region), and the threshold voltage seen from the control gate is lowered. In writing, Vd = 6V, Vcg = 10V, Vs = 0V, and Vsub = 0V. Due to this write voltage relationship, a current flows from the drain to the source, the generated photo-elect port is injected into the floating gate, and the threshold voltage seen from the control gate is increased. In other writing methods, Vd = 0V, Vcg = 10V, Vs = 0V, and Vsub = 0V. Due to this write voltage relationship, electrons are injected into the floating gate by the FN tunnel phenomenon between the channel region between the drain and the source and the floating gate, and the threshold voltage seen from the control gate is increased.

FIG. 5 illustrates the procedure of the initialization operation. In the erase bias application S1, the erase bias described as the erase-related voltage is applied in order to lower the threshold voltage of the nonvolatile memory cell MC. At this time, the threshold voltage distribution of the plurality of nonvolatile memory cells MC sharing the selection gate line, which is a unit of batch erasure, varies according to the erase speed. For example, as shown in FIG. 6, the initial threshold voltage distribution is reduced by the application of the erase bias S1. The threshold voltage is shown as V th.

In erase verify S2, the threshold voltage distribution after erase bias application S1 Check whether the upper limit is below the erase verify level V e V fy. In the state shown in FIG. 7, the upper limit of the threshold voltage distribution is higher than the erase verify eye level Vevfy, so that the state is determined as fail (Fai 1). In the state shown in FIG. 8, the upper limit of the threshold voltage distribution is equal to or lower than the erase verify eye level Ve V fy, so that the state becomes a pass (Pas s). Until the pass, erase bias application of S 1 and erase verify of S 2 are repeated. At this time, since the threshold distribution has a variation according to the erasing characteristics, the lower limit of the threshold distribution may be equal to or less than the depletion level Vdprt as illustrated in FIG.

In the write-back S3, in the threshold voltage distribution after erasing, as shown in FIG. 9, writing is selectively performed on the nonvolatile memory cell MC having the write-back level Vwb or lower, and the lower limit of the threshold voltage distribution is determined. To be equal to or higher than the writeback level Vwb. At this time, the non-volatile memory cell MC that has been debrided during the erasing operation is also subjected to the write-back. Therefore, if the write-back is completed normally, the non-volatile memory cell MC that has been debrided does not remain.

FIG. 10 illustrates an erase threshold voltage distribution by the first initialization command, an erase threshold voltage distribution by the second initialization command, and an erase threshold voltage distribution by manual erase. Wrng represents a write threshold voltage distribution. AErng—M is the erase threshold voltage distribution of the nonvolatile memory cells of the memory array 2 by the second initialization command, and AErng—F is the erase threshold voltage distribution of the flash memory 9 by the first initialization command, M EWr. ng-F represents the erase threshold voltage distribution of the flash fuse circuit 9 by manual erasure. In manual erasure, erasure and erasure verification are performed by sequentially inputting commands, so that it takes a long time to process and some memory cells are not sufficiently rewritten and remain in an over-erased state. When the initialization command is used, no over-erased memory cells remain. Furthermore, the erase verify voltage V e V fy—F by the first initialization command is Erase verify voltage V evfy-M by the reset command, and write-back verify voltage V wb- F by the first reset command is lower than the write-back verify voltage V wb-M by the second reset command. Therefore, a relatively large margin mr 3 is secured for the erase threshold voltage distribution AE rng-F by the first initialization command of the flash fuse circuit 9 with respect to the read line voltage for the flash fuse circuit 9. Can be. If the flash fuse circuit 9 is also initialized by the second initialization command without using the first initialization command, only a small margin mrg 1 can be secured, and the read signal amount becomes small, which may cause a data error. There is. In the case of manual erasure, a margin mrg 2 larger than mrgl can be obtained. However, as described above, there is a concern that rewriting of the flash fuse circuit 9 may be hindered by leaving overerased memory cells. The manual erasing is a process of lowering the erasing threshold voltage distribution by repeating the erasing command a plurality of times after executing the second initialization command, as exemplified in FIG. 11, for example. However, there is a risk that an over-erased (over-erased) bit will occur because no re-writing is performed at all, or insufficiently accompanied. Once an over-erased bit is generated, it may not return to the written state even if a write voltage is applied to the over-erased bit during rewriting, causing a data error.

According to the flash memory described above, the following operational effects can be obtained.

[1] When the flash fuse circuit 9 stores relief data and trimming data, it is not necessary to repeat the erasing and writing processes many times by inputting individual commands. It is possible.

[2] Optimal write-back is performed, and the effect of debris bits is eliminated. [3] The threshold voltage distribution of the flash fuse circuit 9 is optimized, and a sufficient margin can be secured for reading at power-on. in short, When a required read margin is secured by using a boosted voltage for the read line selection level of the memory array 2, the boost fuse voltage can be used without using the boosted voltage for the read line selection level of the flash fuse circuit 9 or the power supply voltage. A similar read margin can be secured even before the voltage is stabilized, and a normal read operation can be performed even if the boost operation has not been completed at power-on.

The invention made by the present inventor has been specifically described based on the embodiments, but the present invention is not limited thereto, and can be variously modified without departing from the gist thereof.

For example, the nonvolatile memory cell is not limited to a flash memory having a flash gate structure, but may be a flash memory having a split gate structure in which a select transistor portion and a memory transistor portion are separated and arranged in series. In addition, the nonvolatile memory cell may perform not only binary storage but also multi-level storage of four or more values. Further, the present invention can be applied not only to a single memory LSI but also to a microcomputer or a system LSI in which a flash memory is on-chip. Industrial applicability

The present invention can be applied to a semiconductor integrated circuit such as a flash memory having a storage area such as a flash fuse.

Claims

The scope of the claims

1. A plurality of nonvolatile memory cells whose threshold voltage can be reversibly changed by electric charge injection and charge release, and a control circuit for controlling the change of the threshold voltage of the plurality of nonvolatile memory cells. And

The control circuit initializes a threshold voltage distribution by a process of initializing a threshold voltage for a predetermined nonvolatile memory cell among the plurality of nonvolatile memory cells, and initializes a threshold voltage for the remaining nonvolatile memory cells. A semiconductor integrated circuit characterized in that the threshold voltage distribution is different from the threshold voltage distribution.

2. The initialization process includes erasing to release electric charge and writing to inject electric charge into the over-erased nonvolatile memory cell,

2. The semiconductor integrated circuit according to claim 1, wherein the control circuit defines a difference in the threshold voltage distribution due to an initialization process by a difference in a verify voltage accompanying the erasing and writing.

3. The distribution of the threshold voltage of the predetermined nonvolatile memory cell by the initialization process is lower than the distribution of the threshold voltage by the initialization process of the remaining nonvolatile memory cells. Item 2. A semiconductor integrated circuit according to item 2.

4. The semiconductor integrated circuit according to claim 1, wherein the predetermined non-volatile memory cell forms a storage area dedicated for storing information necessary for internal operation of the semiconductor integrated circuit.

5. The semiconductor integrated circuit according to claim 4, wherein the information necessary for the internal operation is trimming data and relief data.

6.A plurality of nonvolatile memory cells each having a plurality of nonvolatile memory cells whose threshold voltages can be reversibly changed by electric charge injection and charge release; and Non-volatile memory cell A control circuit for controlling the change of the threshold voltage,

The control circuit performs a process of initializing a threshold voltage for a nonvolatile memory cell in the first memory area in response to a first initialization command,

(2) performing a process of initializing a threshold voltage for the nonvolatile memory cell in the second memory area in response to the initialization command;

The initialization process includes an erasing process for releasing electric charges, and a writing process for injecting electric charges into an overerased nonvolatile memory cell,

2. The semiconductor integrated circuit according to claim 1, wherein the control circuit makes a verify voltage for erasing and writing by the first command different from a verify voltage for erasing and writing by the second command.

7. The semiconductor integrated circuit according to claim 6, wherein a verify voltage according to the first command is lower than a verify voltage according to the second command.

8. A booster circuit that boosts an external power supply voltage and outputs a boosted voltage, and in a read operation, a read line of the nonvolatile memory cell is set to a selected level based on a boosted output of the booster circuit. The semiconductor integrated circuit according to claim 6, wherein

9. The semiconductor integrated circuit according to claim 6, wherein the first memory area is a storage area dedicated for storing information necessary for internal operation of the semiconductor integrated circuit.

10. The semiconductor integrated circuit according to claim 9, wherein the information necessary for the internal operation is trimming data and relief data.

11. The semiconductor integrated circuit according to claim 10, further comprising a register for loading storage information from said first memory area in response to power-on.