JP2005025800A - Semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily detect any defect such as short circuit having directivity caused in a semiconductor memory. <P>SOLUTION: This device is provided with nonvolatile memory cells M00-M03, M10-M13 which are arranged respectively at intersections of a plurality of bit lines BL0-BL3 and word lines WL0, WL1, and of which the drains are connected to the bit lines, the gates are connected to the word lines, and write-in and erasing of data can be performed electrically. At the time of a test, a reference potential VSS is supplied to a bit line adjacent to a bit line to be tested, a potential of the bit line adjacent to the bit line to be tested is pulled down to the reference potential so that a current is caused to flow among bit lines even if short circuit SH1 has directivity caused among bit lines, and the defect can be detected easily. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device capable of electrically writing and erasing data.
[0002]
[Prior art]
FIG. 5 is a diagram showing a configuration of a conventional flash memory which is one of the nonvolatile semiconductor memory devices, and FIG. 5 shows a NOR type flash memory. As shown in FIG. 5, the conventional flash memory has a memory cell array 50, a column decoder 51, a row decoder 52, and a sense amplifier (sense amplifier) 53.
[0003]
The memory cell array 50 includes a plurality of memory cells M0i arranged at intersections of bit lines BLi (i is a subscript, i = 0 to n, the same applies to the following) and word lines WL0 and WL1. M1i. In the memory cells M0i and M1i, the drain is connected to the bit line BLi, and the reference potential VSS (for example, the ground level) is supplied to the source. The gate of the memory cell M0i is connected to the word line WL0, and the gate of the memory cell M1i is connected to the word line WL1.
[0004]
In addition, one end of the bit line BLi is commonly connected to one end of the global bit line through a selection transistor with two bit lines as a set. For example, one end of the bit lines BL0 and BL1 is commonly connected to one end of the global bit line GBL0 via selection transistors TR50 and TR51 whose gates are connected to the control signal lines SG0 and SG1. Similarly, one end of the bit lines BL2 and BL3 is commonly connected to one end of the global bit line GBL1 via selection transistors TR52 and TR53 whose gates are connected to the control signal lines SG0 and SG1. Note that the other end of the bit line BLi is open.
[0005]
The column decoder 51 and the row decoder 52 are for driving the control signal lines SG0 and SG1 and the word lines WL0 and WL1, respectively. Based on the supplied address signals and the like, the control signal lines SG0, SG1, and The word lines WL0 and WL1 are selectively activated. The sense amplifier 53 is connected to the other ends of the global bit lines GBL0, GBL1,..., And the global bit lines GBL0, GBL0 based on the memory cells selected by the control signal lines SG0, SG1 and the word lines WL0, WL1. The amplitude of GBL1,... (Bit line BLi) is amplified and output.
[0006]
FIG. 6 is a schematic diagram showing the structure of the memory cell of the flash memory. The memory cell of the flash memory includes a semiconductor (silicon) substrate 61, a floating gate (floating gate: FG) 62, a control gate (control gate: CG) 63, a first diffusion layer 64, and a second diffusion layer. 65.
[0007]
The floating gate 62 and the control gate 63 are made of, for example, polysilicon, and are sequentially stacked in a predetermined region on the semiconductor substrate 61 via an insulating layer (not shown). The diffusion layers 64 and 65 are formed by introducing an n-type impurity into a predetermined region of the semiconductor substrate 61, for example, if the semiconductor substrate 61 is a p-type silicon substrate. For example, the first diffusion layer 64 has a drain (D ), The second diffusion layer 65 becomes the source (S).
[0008]
In the flash memory shown in FIGS. 5 and 6, in the program operation for writing data “0” to the memory cell, for example, the gate (control gate) 63 of the memory cell is set to the first positive potential and the drain 64 is set to the first positive potential. A second positive potential lower than the potential, the source 65 is set to the ground level. As a result, electrons are injected into the floating gate 62 and the threshold value (Vth) of the memory cell is increased. That is, data “0” is written.
[0009]
In a read operation for reading data stored in the memory cell, a positive potential is applied to the control gate 63 so that the transistor as the memory cell is turned on (conductive) in accordance with the charge (electrons) of the floating gate 62. (Data “1”) or off (non-conducting) state (data “0”). As a result, the potential of the bit line changes according to the data stored in the memory cell, and the data is read out.
[0010]
In the erase operation for erasing data in the memory cell, for example, the control gate 63 of the memory cell is set to a negative potential, the drain 64 is set in a floating state, and the source 65 is set to a positive potential. As a result, electrons are extracted from the floating gate 62 to the source 65, and data is erased.
Note that the potentials of the control gate 63, the drain 64, and the source 65 of the memory cell in each of the above operations are applied by appropriately driving the word lines WL0 and WL1, the bit line BLi, and the like.
[0011]
Heretofore, a defect detection test at the wafer level for removing the initial failure in the flash memory, so-called screening, has been conventionally performed through a program operation, an erase operation, and a read operation which are basic operations of the flash memory. Further, for example, in a test for testing whether or not a memory cell after data erasure is in an over-erased (over-erased) state, there is a test mode that operates in a special state for testing. (For example, refer to Patent Document 1).
[0012]
[Patent Document 1]
JP-A-6-84400
[0013]
[Problems to be solved by the invention]
However, in a conventional flash memory, for example, when a directional short circuit occurs between adjacent bit lines (for example, a short circuit such as a PN junction), the current flowing through the short circuit is directional. Therefore, in the screening, one bit line is determined to be defective, but the other bit line is not determined to be defective. At this time, one bit line determined to be defective is normally redundant and is not used in the actual use state (actual use state), but the other bit line not determined to be defective is not redundant.
[0014]
Further, in a flash memory, an algorithm for preventing over-erasing of a memory cell is provided for a normal bit line that is not determined to be defective. On the other hand, an algorithm for preventing over-erasing of a memory cell is not provided for a bit line determined to be defective and redundant.
[0015]
Therefore, when the program operation and the erase operation are repeatedly executed in the actual use state, an overerase state occurs in the memory cell connected to the redundant bit line, and at this time, the other bit line becomes defective for the first time. . In other words, a bit line that is not judged to be defective by screening because it is a short circuit having directionality even though it is short-circuited with other bit lines will be defective for the first time in actual use in the market. Become.
[0016]
Hereinafter, the above-described problem will be described in detail with reference to FIGS.
7A to 7C are diagrams for explaining the above-described problems in the conventional flash memory, and only the memory cell array is shown for convenience of explanation. 7A to 7C, a gate short circuit SH71 occurs in the select transistor TR72, and a directional short circuit between the bit lines BL1 and BL2 (the direction from the bit line BL1 to the bit line BL2). (Short circuit in which current flows only) SH72. Further, it is assumed that data is written in the memory cell and is always in an off (non-conducting) state.
[0017]
First, FIG. 7A shows a case where the selection signal line SG0 is activated. At this time, the selection transistors TR70 and TR72 are turned on. However, since the gate short circuit SH71 is generated in the selection transistor TR72, the bit line BL2 is determined to be defective. Therefore, the global bit line GBL1 to which the bit lines BL2 and BL3 are commonly connected is redundant.
[0018]
If the short circuit SH72 between the bit lines BL1 and BL2 is a normal short circuit and has no directionality, the potential of the bit line BL1 also changes (increases) with the potential change (potential increase) of the bit line BL2. Therefore, the bit line BL1 is also determined to be defective, and the global bit line GBL0 is made redundant. However, in the example shown in FIG. 7, since the short circuit SH72 between the bit lines BL1 and BL2 has directionality, the potential of the bit line BL1 does not change. Therefore, the bit line BL1 is not determined to be defective and is not redundant.
[0019]
FIG. 7B shows a case where the selection signal line SG1 is activated. At this time, since the bit line BL2 is in a floating state, the bit line BL1 is not affected at all. Therefore, the bit line BL1 is determined to be normal and is not redundant.
[0020]
FIG. 7C shows a case where the selection signal line SG1 is activated in a state where the memory cell MC1 is overerased. At this time, since the memory cell MC1 is in an over-erased state, it operates as a depletion type (normally on type) transistor, and is turned on (conductive) even if the word line WL0 is not activated. Therefore, the bit line BL2 is connected to the reference potential VSS, and a current flows to the bit line BL2 through the portion short-circuited SH72 from the bit line BL1. Therefore, the bit line BL1 becomes defective.
[0021]
As described above, in a conventional flash memory, a potential failure such as a directional short circuit generated between adjacent bit lines is repeatedly executed by a program operation and an erase operation and connected to redundant bit lines. The detected memory cell could not be detected unless it was over-erased. Therefore, in order to detect such a defect by screening, there has been a problem that a great amount of man-hours are required.
[0022]
The present invention has been made in view of such problems, and an object of the present invention is to make it possible to easily detect a defect such as a directional short circuit that occurs in a semiconductor memory device.
[0023]
[Means for Solving the Problems]
The semiconductor memory device of the present invention is arranged at the intersection of a plurality of bit lines and word lines, and has a drain connected to the bit line and a gate connected to the word line for electrically writing and erasing data. Possible non-volatile memory cells. In the test, a reference potential is supplied to the bit line arranged adjacent to the bit line to be tested.
As a result, the bit line adjacent to the bit line to be tested is pulled down to the reference potential instead of being in a floating state at the time of testing, so even if a short circuit occurring between the bit lines has directionality, A current flows and a defect can be easily detected.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
In the following description, for convenience of explanation, only four or seven bit lines in the memory cell array are shown and described, but the present invention is not limited to this and the number of bit lines is arbitrary. The number of memory cells connected to one bit line is also two (two cell transistors). However, the number of memory cells is not limited to two and is arbitrary. The number of memory cells connected to one bit line is Accordingly, a word line is provided.
[0025]
FIG. 1 is a view for explaining the principle of the semiconductor memory device according to the present embodiment. In FIG. 1, reference numeral 10 denotes a memory cell array, and a plurality of memory cells M00 to M03 and M10 respectively arranged at intersections between bit lines BL0 to BL3 and word lines WL0 and WL1 arranged to intersect with the bit lines BL0 to BL3. ~ M13. Each of the memory cells M00 to M03 and M10 to M13 is a non-volatile memory cell configured as shown in FIG. 6 and capable of electrically writing and erasing data, that is, electrically rewriting data. is there.
[0026]
The memory cells M00 and M10 have drains connected to the bit line BL0, and a source supplied with a reference potential VSS (for example, ground level). The gate (control gate) of the memory cell M00 is connected to the word line WL0, and the gate (control gate) of the memory cell M10 is connected to the word line WL1. Similarly, in the memory cells M0j and M1j (j is a subscript, j = 1 to 3), the reference potential VSS is supplied to the source, the drain is connected to the bit line BLj, and the gate (control gate) is the word. Connected to lines WL0 and WL1.
[0027]
One ends of the bit lines BL0 and BL1 are commonly connected to one end of the global bit line GBL0 via selection transistors ST0 and ST1, respectively. The other ends of the bit lines BL0 and BL1 are connected to a signal line GL to which a reference voltage VSS is supplied via switching elements PT0 and PT1, respectively.
[0028]
Similarly, one end of the bit lines BL2 and BL3 is commonly connected to one end of the global bit line GBL1 via the select transistors ST2 and ST3, and the other end is connected to the signal line GL via the switching elements PT2 and PT3.
[0029]
The switching elements PT0 to PT3 are circuits for setting the potential at the other end of the bit lines BL0 to BL3 to the reference potential VSS (pull down) according to signals supplied from the control signal lines CTL0 to CTL3. For example, as shown in FIG. 1, the switching elements PT0 to PT3 have drains connected to the other ends of the bit lines BL0 to BL3, sources connected to the signal line GL, and gates connected to the control signal lines CTL0 to CTL3. It is composed of a transistor (MOS transistor).
[0030]
The select transistors ST0 and ST2 have gates connected to the control signal line SG0, respectively, and the select transistors ST1 and ST3 have gates connected to the control signal line SG1.
[0031]
A column decoder 11 drives the control signal lines SG0 and SG1, and selectively activates the control signal lines SG0 and SG1 based on the supplied address signal and the like. Reference numeral 12 denotes a row decoder for driving the word lines WL0 and WL1, and selectively activates the word lines WL0 and WL1 based on the supplied address signal or the like.
[0032]
A control circuit 13 drives the control signal lines CTL0 to CTL3, and appropriately activates the control signal lines CTL0 to CTL3 when testing (screening) the semiconductor memory device. Specifically, as shown in FIG. 3, when the bit line BL (n) (n is an integer) to be tested is selected, the control circuit 13 at least places the bit lines BL ( The control signal lines CTL (n−1) and CTL (n + 1) are driven so that the switching elements TR33 and TR35 related to n−1) and BL (n + 1) are turned on (conductive). At this time, the switching element TR34 related to the selected bit line BL (n) is turned off (non-conducting). In FIG. 3, transistors TR30 to TR32 are selection transistors, and MC is a memory cell.
[0033]
Returning to FIG. 1, reference numeral 14 denotes a sense amplifier, to which the other ends of the global bit lines GBL0 and GBL1 are respectively connected. The sense amplifier 14 determines the amplitude (potential change) of the global bit lines GBL0 and GBL1 (bit lines BL0 to BL3) according to the data stored in the memory cell selected by the control signal lines SG0 and SG1 and the word lines WL0 and WL1. ) Is amplified and output.
[0034]
An operation in the semiconductor memory device shown in FIG. 1 will be described.
In the normal operation (program operation, erase operation, and read operation), all of the control signal lines CTL0 to CTL3 are inactivated by the control circuit 13, and the switching elements (transistors) PT0 to PT3 are turned off (non-conducting). Since only the state is the same as in the prior art, the description is omitted, and only the operation at the time of performing the test (screening) will be described.
[0035]
Further, it is assumed that data “0” is previously written in the memory cells M00 to M03 and M10 to M13 by the program operation. That is, the memory cells M00 to M03 and M10 to M13 are non-conductive even when selected by the word lines WL0 and WL1.
The column decoder 11 maintains the control signal line SG0 in an inactive state and activates the control signal line SG1. The control circuit 13 activates the control signal lines CTL0 and CTL2. Note that the control signal lines CTL1 and CTL3 are inactive.
[0036]
Thereby, the selection transistors ST0 and ST2 are turned off, and the selection transistors ST1 and ST3 are turned on. Similarly, the switching elements (transistors) PT0 and PT2 are turned on (conductive), and the switching elements (transistors) PT1 and PT3 are turned off (non-conductive). Therefore, the bit lines BL0 and BL2 adjacent to the selected bit line BL1 are pulled down to the reference potential VSS.
[0037]
At this time, if no defect such as a short circuit or gate short circuit between adjacent bit lines occurs in the bit line BL1, the current from the sense amplifier 14 does not flow through the global bit line GBL0 and the bit line BL1. . Therefore, based on the comparison between the current from the sense amplifier 14 and the reference current from another current source, it is determined that the bit line BL1 is normal with no defects.
[0038]
On the other hand, as shown in FIG. 1, there is a short circuit between the bit lines BL1 and BL2, for example, a short circuit SH1 having a direction in which current flows only in the direction from the bit line BL1 to the bit line BL2 as described in the related art. Suppose there was. In this case, the current from the sense amplifier 14 leaks between the bit lines BL1 and BL2, and at the reference potential VSS via the global bit line GBL0 and the bit line BL1, and further via the bit line BL2 and the switching element PT2. It flows with respect to a certain signal line GL. As a result, the bit line BL1 is determined to be defective, and the global bit line GBL0 is made redundant.
[0039]
Such a directional short circuit SH1 generated between the bit lines BL1 and BL2 cannot be detected in the conventional test (screening) because the bit lines BL0 and BL2 are in a floating state. Had to repeatedly execute a program operation and an erase operation to put the memory cell in an overerased state. On the other hand, in this embodiment, even a potential failure such as a directional short circuit SH1 can be detected very easily in a test (screening).
[0040]
Hereinafter, a specific configuration example will be described. In the following description, only the memory cell array is illustrated and described.
(First embodiment)
FIG. 2 is a diagram showing a configuration example of the semiconductor memory device according to the first embodiment of the present invention. In FIG. 2, the same components as those shown in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted.
[0041]
In FIG. 2, transistors (MOS transistors) TR0, TR1, TR2, and TR3 correspond to the selection transistors ST0, ST1, ST2, and ST3 shown in FIG. The gates of the transistors TR0 and TR2 are connected to the control signal line SG0, and the gates of the transistors TR1 and TR3 are connected to the control signal line SG1.
[0042]
Transistors (MOS transistors) TR4, TR5, TR6, and TR7 correspond to the switching elements (transistors) PT0, PT1, PT2, and PT3 shown in FIG. 1, respectively. The gates of the transistors TR4 and TR6 are connected to the control signal line SEV, and the gates of the transistors TR5 and TR7 are connected to the control signal line SOD.
[0043]
Further, the control signal lines SEV and SOD are connected to the output terminal of the control circuit 13, and normally the transistors TR4 to TR7 are turned off in the same manner as described above, and the control signal lines SEV and SOD are reversed when performing the test. It is controlled to output a phase signal.
[0044]
As described above, in the first embodiment, the transistors TR4 and TR6 for pulling down the even-numbered bit lines BL0 and BL2 are controlled by the control signal line SEV. Transistors TR5 and TR7 for pulling down odd-numbered bit lines BL1 and BL3 are controlled by a control signal line SOD.
[0045]
As a result, when a test (screening) is performed, when an odd-numbered bit line is selected as a test target, the selected bits are pulled down by turning on the transistors TR4 and TR6 and pulling down all the even-numbered bit lines. The bit lines on both sides adjacent to the line are pulled down to the reference potential VSS. At this time, the transistors TR5 and TR7 related to the odd-numbered bit lines are in the off state.
[0046]
Conversely, when an even-numbered bit line is selected as a test target, the transistors TR5 and TR7 are turned on to pull down all the odd-numbered bit lines, and the bit lines on both sides adjacent to the selected bit line are connected. Pull down to the reference potential VSS. At this time, the transistors TR5 and TR7 related to the even-numbered bit lines are in the off state.
[0047]
That is, in the first embodiment, when a bit line as a test (screening) target is selected, every other bit line is pulled down to the reference potential VSS so as not to include the bit line.
The operation is the same as that of the semiconductor memory device shown in FIG.
[0048]
According to the first embodiment, the bit lines on both sides of the bit line selected as the test target in the screening can be pulled down to the reference potential VSS, and between the selected bit line and the bit line adjacent to the selected bit line. Even if a directional short circuit occurs, the short circuit (defect) can be easily detected without repeatedly executing the program operation and the erase operation. In addition, since only the signals supplied via the control signal lines SEV and SOD are used and every other bit line is pulled down to the reference potential VSS so as not to include the bit line selected as the test object, the control is also very high. Easy.
[0049]
(Second Embodiment)
Next, a second embodiment of the present invention will be described.
In the semiconductor memory device according to the first embodiment described above, one transistor for pulling down the bit lines BL0 to BL3 to the reference potential VSS must be newly provided for each bit line. Increases (area penalty occurs).
[0050]
In the semiconductor memory device according to the second embodiment described below, the bit line pair connected to the global bit line is appropriately arranged as shown in FIG. The line can be pulled down to the reference potential VSS.
[0051]
FIG. 4 is a diagram showing a configuration example of the semiconductor memory device according to the second embodiment of the present invention.
As shown in FIG. 4, in the memory cell array 10 ′, the memory cells M0k and M1k (k is a subscript and k = 0 to 6) are connected to the bit line BLk at the drain and to the bit line BLk at the gate. The word lines WL0 and WL1 are arranged so as to cross each other. The memory cells M0k and M1k are supplied with the reference potential VSS at their sources.
[0052]
One end of the bit line BLk is connected to one end of the global bit line via the selection transistor TR1k. Bit lines BL0 and BL2 are commonly connected to global bit line GBL0, and bit lines BL1 and BL4 are commonly connected to global bit line GBL1. In addition, bit lines BL3 and BL6 are commonly connected to global bit line GBL2, and bit line BL5 is connected to global bit line GBL3. Note that the other end of the bit line BLk is open.
[0053]
The gates of the selection transistors TR10 and TR13 are connected to the control signal line SG0, and the gates of the selection transistors TR12 and TR16 are connected to the control signal line SG1. The gate of the selection transistor TR14 is connected to the control signal line SG2, and the gates of the selection transistors TR11 and TR15 are connected to the control signal line SG3.
[0054]
The global bit lines GBL0 to GBL3 (the drain of the selection transistor TR1k) are connected to the signal lines to which the global bit lines GB0 to GB3 or the reference potential VSS are supplied via the switch circuits 40 to 43. The switch circuits 40 to 43 are controlled independently from each other by a control circuit 13 (not shown). The global bit lines GB0 to GB3 are connected to a sense amplifier (not shown).
[0055]
Next, the operation of the semiconductor memory device shown in FIG. 4 will be described.
The normal operation may be performed by connecting the global bit lines GBL0 to GBL3 and the global bit lines GB0 to GB3 via the switch circuits 40 to 43, and the description thereof is omitted because it is the same as the conventional one. Only the operation when performing the above will be described.
[0056]
For example, it is assumed that the bit line BL2 is a bit line selected as a test target. Note that data “0” is previously written in the memory cells M0k and M1k.
At this time, the control circuit 13 controls the switch circuit 40 so that the global bit line GBL0 to which the selected bit line BL2 is connected is connected to the global bit line GB0. In addition, the control circuit 13 controls the switch circuits 41 to 43 so that the reference potential VSS is supplied to the other (non-selected) global bit lines GBL1 to GBL3. At least the control signal lines SG0, SG1, and SG3 are activated by a column decoder (not shown). Note that the control signal line SG2 may also be activated.
[0057]
Thus, the selected bit line BL2 is connected to the sense amplifier via the global bit lines GBL0 and GB0, and the bit lines BL1 and BL3 adjacent to the bit line BL2 can be pulled down to the reference potential VSS.
[0058]
That is, in the second embodiment, the global bit lines GBL0 to GBL3 to which the bit line selected as the test (screening) target is connected are connected to the sense amplifier, and the other global bit lines GBL0 to GBL3 are the reference. The switch circuits 40 to 43 are controlled so that the potential VSS is supplied. Then, by turning on the selection transistor TR1k, the bit lines on both sides of the selected bit line can be pulled down to the reference potential VSS. Therefore, even if a directional short circuit has occurred between the selected bit line and the adjacent bit line, the short circuit (defect) can be easily performed without providing a new transistor for each bit line. Can be detected.
[0059]
The configuration of the semiconductor memory device in the second embodiment shown in FIG. 4 is an example, and the bit lines on both sides of the bit line selected as the test target at the time of the test can be pulled down to the reference potential VSS. It suffices if a bit line is arranged in each other.
[0060]
The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.
Various aspects of the present invention will be described below as supplementary notes.
[0061]
(Supplementary note 1) a plurality of bit lines;
A word line arranged to intersect the plurality of bit lines;
Non-volatile memory capable of electrically writing and erasing data, which is arranged at the intersection of the bit line and the word line, has a drain connected to the bit line, and a gate connected to the word line With a cell,
A semiconductor memory device, wherein a reference potential is supplied to a bit line arranged adjacent to the bit line to be tested during a test.
(Additional remark 2) Further provided with the said each bit line, The reference potential is supplied to one terminal, The other terminal is further provided with the switching element connected to the end of the said bit line, The additional description 1 characterized by the above-mentioned Semiconductor memory device.
(Supplementary note 3) The semiconductor memory device according to supplementary note 2, wherein the switching element is a transistor having a reference potential supplied to a source and a drain connected to one end of the bit line.
(Supplementary note 4) In the test, the reference potential is supplied to a bit line including a bit line arranged adjacent to the bit line to be tested every other one of the plurality of bit lines. Or a semiconductor memory device according to 3;
(Supplementary Note 5) The switching element connected to the even-numbered bit lines of the plurality of bit lines is controlled by a first control signal,
The semiconductor memory device according to claim 4, wherein the switching element connected to the odd-numbered bit lines of the plurality of bit lines is controlled by a second control signal different from the first control signal. .
(Supplementary note 6) The semiconductor memory device according to supplementary note 5, wherein the second control signal is a reverse phase signal of the first control signal.
(Additional remark 7) It is further provided with the selection transistor by which the source was connected to one end of the said bit line for each of these bit lines, and selecting the said bit line,
During testing, a reference potential is supplied to the drain of the selection transistor of the bit line arranged adjacent to the bit line to be tested, and the reference potential is supplied to the bit line via the selection transistor. The semiconductor memory device according to appendix 1.
(Supplementary note 8) The semiconductor memory according to Supplementary note 7, further comprising a switch circuit for selectively switching between supplying a reference potential to the drain of the selection transistor or connecting the drain to a sense amplifier. apparatus.
(Supplementary note 9) The semiconductor memory device according to any one of supplementary notes 1 to 8, wherein the reference potential is a ground level.
[0062]
【The invention's effect】
As described above, according to the present invention, a semiconductor memory device including nonvolatile memory cells capable of electrically writing and erasing data, which are respectively arranged at intersections of a plurality of bit lines and word lines. During the test, a reference potential is supplied to the bit line adjacent to the bit line to be tested. As a result, the bit line adjacent to the bit line to be tested can be pulled down to the reference potential at the time of the test. It is possible to easily detect a defect without repeatedly performing the operation. Therefore, a potential defect can be detected with a small number of man-hours.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining the principle of a semiconductor memory device according to an embodiment;
FIG. 2 is a diagram showing a configuration example of the semiconductor memory device according to the first embodiment.
FIG. 3 is a diagram showing a control principle during screening of the semiconductor memory device according to the present embodiment.
FIG. 4 is a diagram illustrating a configuration example of a semiconductor memory device according to a second embodiment.
FIG. 5 is a diagram showing a configuration of a conventional flash memory.
FIG. 6 is a schematic diagram showing the structure of a memory cell of a flash memory.
FIG. 7 is a diagram for explaining a problem in a conventional flash memory.
[Explanation of symbols]
10 Memory cell array
11 column decoder
12-line decoder
13 Control circuit
14 sense amplifier
SG0, SG1 control signal line
WL0, WL1 Word line
BL0 to BL3 bit lines
M00 to M03, M10 to M13 memory cells
ST0 to ST3 Select transistor
PT0 to PT3 Switching element (pull-down transistor)

Claims (5)

Multiple bit lines,
A word line arranged to intersect the plurality of bit lines;
Non-volatile memory capable of electrically writing and erasing data, which is arranged at the intersection of the bit line and the word line, has a drain connected to the bit line, and a gate connected to the word line With a cell,
A semiconductor memory device, wherein a reference potential is supplied to a bit line arranged adjacent to the bit line to be tested during a test. 2. The semiconductor memory device according to claim 1, further comprising a switching element provided on each of the bit lines, wherein a reference potential is supplied to one terminal, and the other terminal is connected to one end of the bit line. . 3. The semiconductor memory device according to claim 2, wherein the switching element is a transistor in which a reference potential is supplied to a source and a drain is connected to one end of the bit line. 4. The test circuit according to claim 2, wherein the reference potential is supplied to a bit line including a bit line arranged adjacent to the bit line to be tested every other bit line in the test. The semiconductor memory device described. Each of the plurality of bit lines further includes a selection transistor having a source connected to one end of the bit line for selecting the bit line,
During testing, a reference potential is supplied to the drain of the selection transistor of the bit line arranged adjacent to the bit line to be tested, and the reference potential is supplied to the bit line via the selection transistor. The semiconductor memory device according to claim 1.

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