JP3160451B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM), and more particularly to an EEPROM having a memory cell array having a NAND cell structure.
The present invention relates to a memory system using OM.

[0002]

2. Description of the Related Art As one type of EEPROM, a NAND cell type EEPROM capable of high integration is known. In this method, a plurality of memory cells are connected in series in such a manner that their sources and drains are shared by adjacent ones, and are connected to bit lines as a unit. The memory cell usually has an FETMOS structure in which a floating gate (charge storage layer) and a control gate are stacked. The memory cell array is integrally formed in a p-type well formed on a p-type substrate or an n-type substrate. The drain side of the NAND cell is connected to a bit line via a selection gate, and the source side is also connected to a common source line via a selection gate. The control gates of the memory cells are continuously connected in the row direction to form word lines.

The operation of a NAND cell type EEPROM is as follows. The data write operation is performed sequentially from the memory cell located farthest from the bit line. The high voltage Vpp (approximately 20 V) is applied to the control gate of the selected memory cell, and the intermediate voltages VMCG and VMS are applied to the control gate and the selection gate of the memory cell on the bit line side.
G (= about 10 V) is applied, and 0 V or an intermediate voltage VMBL (= about 8 V) is applied to the bit line according to data.

When 0 V is applied to the bit line, the potential is transmitted to the drain of the selected memory cell, and electrons are injected from the drain to the floating gate. As a result, the threshold value of the selected memory cell shifts in the positive direction. This state is, for example, data “0”. When an intermediate potential is applied to the bit line, electron injection does not occur, so that the threshold value does not change and remains negative. This state is data "1". During the write operation, the source line and the select gate on the source line side are set to 0V.

[0005] Data erasure is performed simultaneously on all memory cells in the NAND cell. That is, all control gates and select gates are set to 0 V, the bit lines and source lines are set in a floating state, and a high voltage 20
V is applied. As a result, in all the memory cells, electrons of the floating gate are emitted to the p-type well, and the threshold value shifts in the negative direction.

In a data read operation, the control gate of the selected memory cell is set to 0 V, and the control gates and select gates of the other memory cells are set to the power supply potential Vcc (= 5 V).
The detection is performed by setting the source line to 0 V and detecting whether a current flows in the selected memory cell.

The above-mentioned Vpp, VMCG, VMSG, VMBL
All potentials are generated by a booster circuit inside the chip, and the supply capability is generally much lower than the Vcc and Vss potentials.

FIG. 11 is a timing chart for explaining the data write operation in the selected block. In the case of the operation as shown in FIG. 11, "*"
The VMBL is connected to the channel portion in the NAND string (in the selected block) connected to the bit line corresponding to the data write.
The potential is transferred, and the drain portion of the source side select gate SG2 also becomes 0V → VMBL (（8V). Then, the coupling of the selection gate SG2 becomes 0V → ΔV (ΔV>
0V).

At the SG2 node located at a position distant from the SG2 potential charged portion at the end of the memory cell array, the resistance between the charged portion and the SG2 node has a weak charge supply capability from the charged portion. Instead, ΔV> [threshold voltage of the selection gate]. And V
The bit line at the MBL potential and the source line at the Vss potential are short-circuited, which causes a problem that the VMBL potential is reduced and the reliability of the write operation is reduced.

If writing is performed after waiting for the intermediate potential to return to the original level after lowering, the writing time becomes extremely long because the supply capability of the intermediate potential is not so high. Further, there is a problem that the chip area is increased if the capability of the booster circuit for generating the VMBL potential is increased in order to suppress the decrease amount of the VMBL potential.

[0011]

As described above, the conventional N
In the AND cell type EEPROM, since the potential of the gate of the selection gate on the source line side rises due to the coupling, the selection gate is turned on, and the level of the intermediate potential applied to the bit line in order to write "1" data is changed. Therefore, there is a problem that the reliability of the write operation is reduced. Further, if data writing is performed after waiting for the intermediate level to return to the original level after lowering, the writing time becomes longer, and the supply capacity of the intermediate potential generating circuit will be increased in order to reduce the decrease in the intermediate potential level. Then, there is a problem that the chip size becomes large.

The present invention has been made in consideration of the above circumstances, and has as its object to provide a NAND cell type EEPROM capable of performing a highly reliable high-speed write operation without increasing the chip area. Is to provide.

[0013]

The gist of the present invention is to set the voltage of the source line to a voltage higher than the ground potential while the select gate on the bit line side is in the ON state during the data write operation. That is, the present invention (claim 1) provides a memory cell or a memory cell column in which a charge storage layer and a control gate are formed on a semiconductor substrate and electrical rewriting is performed by transferring charges between the charge storage layer and the substrate. Are connected to one end of a memory cell or a memory cell column directly or via a transistor, and are connected directly to the other end of a memory cell or a memory cell column or via a transistor. In the EEPROM including the source line, the potential of the source line is set to a potential higher than the ground potential, for example, a power supply voltage when a high potential is applied to the bit line.

Further, according to the present invention (claim 2), there is provided a memory cell in which a charge storage layer and a control gate are formed on a semiconductor substrate and electrically rewritten by transferring charges between the charge storage layer and the substrate. A plurality of NAND cells connected in series are arrayed, a bit line is connected to one end of each NAND cell via a first select gate, and a source is connected to the other end of the NAND cell via a second select gate. N to which the wire is connected
In an EEPROM provided with an AND cell array, when a predetermined block is selected and data is written, while the first selection gate on the bit line side in the selected block is in the ON state, the potential of the source line is changed. It is characterized in that it is set to a potential higher than the ground potential, for example, a power supply voltage.

[0015]

According to the present invention, during the data write operation,
By setting the potential of the source line in the memory cell array to be higher than the ground potential, for example, the power supply potential, the selection gate on the source line side is prevented from being turned on when the selection gate on the bit line side is turned on. Therefore, the level of the intermediate potential applied to the bit line can be prevented from lowering.

Therefore, there is no need to wait for the intermediate level to return to the original level after the intermediate level has been lowered before writing data, and the chip size does not increase in order to increase the supply capacity of the intermediate potential generating circuit. Thus, according to the present invention, it is possible to realize highly reliable high-speed data writing without increasing the chip area.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a NAND according to a first embodiment of the present invention.
FIG. 2 is a block diagram illustrating a schematic configuration of a cell type EEPROM. A bit line control circuit 2 is provided for performing data write, read, rewrite, and verify read on the memory cell array 1. This bit line control circuit 2 is connected to a data input / output buffer 6 and receives as an input the output of a column decoder 3 that receives an address signal from an address buffer 4. A row decoder 5 is provided for controlling a control gate and a selection gate for the memory cell array 1.
A substrate potential control circuit 7 for controlling the potential of the p substrate (or p-type well) on which the semiconductor device is formed, and a source line potential control circuit 8 for controlling the potential of the source line in the memory cell array 1 are provided. .

The bit line control circuit 2 is mainly composed of a CMOS flip-flop, and latches data to be written, senses a bit line potential, senses a verify read after writing, and rewrites. Latch data.

FIGS. 2A and 2B are a plan view and an equivalent circuit diagram of one NAND cell part of the memory cell array.
3A and 3B are cross-sectional views taken along the lines AA 'and BB' of FIG. 2A, respectively.

A memory cell array composed of a plurality of NAND cells is formed on a p-type silicon substrate (or p-type well) 11 surrounded by an element isolation oxide film 12. One NA
In this embodiment, eight memory cells M1 to M8 are connected in series to form one NAND cell.
Make up the cell. Each of the memory cells has a substrate 11
Floating gate 14 (14 ₁ , 14 ₁₎ via gate insulating film 13
14 ₂ ,..., 14 ₈ ), and the interlayer insulating film 1
5, the control gate 16 (16 ₁ , 16 ₂ ,..., 16
₈ ) is formed. Memory cells are connected in series in such a manner that adjacent n-type diffusion layers 19, which are the source and drain of these memory cell arrays, are commonly used.

The drain of the NAND cell side, the source side, a floating gate, selected simultaneously formed with the control gate gate 14 _9, 16 ₉ and 14 _10, 16 ₁₀ of the memory cell are respectively provided. CV on the substrate on which the element is formed
It is covered with a D oxide film 17, on which a bit line 18 is provided. The bit line 18 is in contact with the drain diffusion layer 19 at one end of the NAND cell. The control gates 14 of the NAND cells arranged in the row direction are commonly arranged as control gate lines CG1, CG2,..., CG8.
These control gate lines CG become word lines. Select gate 14 _9, 16 ₉ and 14 _10, 16 ₁₀ are also arranged in each row direction successively selected gate lines SG1, SG2.

FIG. 4 shows an equivalent circuit of a memory cell array in which such NAND cells are arranged in a matrix. FIG. 5 shows the timing of the write operation in the first embodiment. FIG. 5 is a diagram showing the operation timing of each unit in the selected block during the write operation. In this case, one of the eight CGs in the selected block is selected and the rest are unselected CGs. Details of FIG. 5 will be described below.

When the write operation starts, first, the bit line B
L changes from 0V to Vcc, and the Cell-Source line also changes from 0V to
Vcc. Subsequently, after the bit line BL becomes Vcc → VMBL (where VMBL is a voltage generated by a booster circuit inside the chip and is higher than Vcc, for example, about 8 V), a memory for writing “0” data N including cells (that is, memory cells whose threshold voltage changes from negative to positive)
Only the bit line BL connected to the AND cell is VMBL → 0
V.

Subsequently, the selected CG, unselected CG, and SG1 change from 0V to Vcc, and further, Vcc → VMCG or Vcc → V
MSG (both VMCG and VMSG are voltages generated by a booster circuit inside the chip and are higher than Vcc, for example, about 10 to 12 V). In addition, select CG
Only VMCG → Vpp (where Vpp is the voltage generated by the booster circuit inside the chip, VMBL, VMCG, VMSG
The voltage is higher, for example, about 20 V), and this state is maintained for a while, and data is written to the memory cell.

When the data writing to the memory cell is completed, the selected CG, unselected CG, and SG1 are all set to 0V,
Subsequently, the bit line BL at the potential of VMBL is set to VMBL → 0V. At this time, the Cell-Source line is also set to Vcc → 0V. This completes the write operation.

The feature of this embodiment described above is that the potential of the Cell-Source line is kept at Vcc while the select gate SG1 on the bit line side is in the ON state during the write operation. The advantages of this feature are described below.

FIG. 6A shows an example of an arrangement of a memory cell array, a row decoder, and a sense amplifier / latch circuit on a chip. The potential of SG2 in the memory cell array is applied via a transistor in the row decoder. SG2 wiring in the memory cell array is Cell-pwell and Cell-pwell.
Since there is a capacitance between the source and the other wiring and the resistance of the SG2 wiring itself, when charging and discharging the SG2 in the memory cell, the charging / discharging waveform of each part of the SG2 does not have the same shape. When the SG2 wiring in the memory cell is charged / discharged from only one side (the left side in the figure) of the memory cell array as shown in FIG. 6 (a), FIG.
The charge / discharge waveform is as shown in FIG.

As described above, depending on the capacitance and resistance of the SG2 wiring, the required charging / discharging time differs in each part of the SG2. The same can be said for the case where the SG2 potential rises due to the rise in the potential of the diffusion layer (node _{19SG2 in} FIGS. 2 and 4) on the side opposite to the Cell-Source line.

FIG. 7A is a cross-sectional view (cross-sectional view taken along the line AA 'in FIG. 2) of the S2 selection gate in FIGS.
Of the capacitances in the memory cell of the gate _14SG2 of the selection gate S2, the main ones are C1, C2 and C3 in FIG. 7A (16 _SG2 is generally the same potential as 14 _SG2 or floating). _Therefore , there is practically no capacity between 14 _SG2 ). Cell- of the selection gate S2
If there is a depletion in the Cell-pwell side of pwell / SiO ₂ interface, 14 _SG2 and Cell-pwell capacitance C3 of C1, C2
, C1 and C2 become the main capacitance of 14 _SG2 .

In this case, considering the operation in the case of the * part in FIG. 5, when SG1 changes from 0V → Vcc → VMCG,
NAND including memory cell for writing “1” data
In the column, the channel part of all memory cells is 0V → VMBL
(〜8 V), and therefore the node of 19 _{SG2 in} FIGS. 2 and 4 changes from 0 → VMBL (〜8 V). Therefore, the 14 _SG2 node becomes C1 / (C1 + C2) due to capacity coupling.
・ VMBL potential (4 when C1 = C2, VMBL = 8V)
V).

In this case, the part 1 in FIG.
Since the charge can be supplied from the outside of the memory cell array at a high speed near the charge / discharge portion of No. 2, the potential rise is easily suppressed.
However, since the portions 2 and 3 in FIG. 6A are separated from the charging / discharging portion of SG2, the rise in potential cannot be suppressed.
As shown in FIG. 7B, the potential of _14SG2 in FIG. 7A becomes higher than the threshold voltage Vth _SG2 of the selection gate SG2.

In this case, in the conventional method in which the Cell-Source line is fixed at 0V, the selection transistor S2 is turned on, and the bit line at the VMBL potential and the Cell-So line at 0V are connected.
The urce line is shorted. Then, the VMBL potential is a voltage generated by the booster circuit inside the chip, and the level is easily lowered due to the low supply capability. Further, once the level is lowered, it takes a long time to return to the original level. In this case, since the level cannot be returned to the original level, the reliability of the write operation is reduced.

Further, if the supply capacity is increased in order to suppress the decrease in the level of the VMBL potential, the chip area increases. If the selected CG is changed from VMCG to Vpp after waiting for the VMBL potential to return to the original level, the time required for writing becomes very long because the VMBL potential supply capability is not so high, and a high-speed writing operation is realized. Becomes impossible.

On the other hand, during the period of ☆ in FIG.
In the method of this embodiment in which the urce is fixed to Vcc, unless the 14 _SG2 potential in FIG. 7A becomes higher than ( _Vcc + Vth _SG2 ), the bit line at the VMBL potential and the Cell-Source line are not short-circuited. As shown in FIG. 7 (b), the short circuit does not occur in the portions 2 and 3. Therefore, highly reliable writing can be performed without lowering VMBL.

For the above-described reason, it is not necessary to wait for the intermediate level applied to the bit line BL to return to the original level after lowering for data writing, and high-speed writing becomes possible. Further, there is no need to increase the supply capacity of the intermediate potential generation circuit in order to reduce the decrease in the intermediate potential level, and it is possible to avoid disadvantages such as an increase in chip size.

In the above embodiment, after the bit lines are first set to 0V → Vcc → VMBL, only the bit lines connected to the NAND string including the memory cells for writing “0” data are selectively reduced to 0V. Although the example in the case of causing the
The present invention is also effective in the case where only the bit line corresponding to the “1” data write memory cell is charged from 0V → Vcc → VMBL from the beginning.

In the embodiment, the Cell-Source line is set to 0 V
The timing of → Vcc and Vcc → 0V was performed at the same time as the charging / discharging of the bit line. However, even if the timing is shifted, when SG1 is in the ON state, Cell−
It is effective if the Source line is at Vcc.

In the embodiment, the bit line is changed from 0 → Vcc →
After setting VMBL, SG1 was changed from 0 → Vcc → VMSG,
Charge both at the same time, or first set SG1 to 0 → Vcc
Even if the bit line is changed from 0 to Vcc to VMBL after setting to VMSG, when the SG1 is in the ON state, Cell-So
Needless to say, it is effective if the urce line is at Vcc. Also, needless to say, the present invention is effective even when SG2 is lined with a low-resistance material.

Although the above has been described with reference to a NAND type EEPROM as an example, the present invention is not limited to the above embodiment. Hereinafter, a description will be given of a case where the present invention is applied to a device other than the NAND type EEPROM.

FIG. 8 shows a configuration example to which the present invention can be applied other than the NAND type EEPROM. (A) and (b) are examples of a structure in which a memory cell and a selection gate are connected in series, (c) is an example of a memory cell alone, and (d) and (e) are examples of a transistor alone. 9 (a) to 9 (e) and FIGS. 10 (a) to 10 (e) show operation examples of FIGS. 8 (a) to 8 (e), respectively.

First, FIG. 9 which is an example of the operation of FIG.
(A) will be described. In FIG. 9A, VBL3 is set to 0V →
When the voltage is set to VBLH, when the memory cell M3 is in the active state (in this case, Vcg3 may be 0 V or VcgH), the voltage of the node N3 also increases, and the voltage between the node N3 and the gate Vsg3 of the selection gate S3 is increased. Vsg3 rises due to the coupling, the selection gate S3 turns on, and VBL3 and V
There is a problem that S3 is short-circuited. In order to prevent this problem, VS3 is changed from 0V to Vcc before VBL3 becomes VBLH potential.
, The voltage at which the selection gate S3 is turned on becomes V
ths3 → (Vcc + Vths3) (where Vths3 is the select gate S
3), and the select gate S
3 can be prevented from turning on.

The operation example of FIG. 9A is effective especially when VBLH is a high voltage higher than Vcc generated inside the chip. As in the case of the embodiment of FIGS. By preventing the gate S3 from turning on, it is possible to prevent the leakage of the VBLH through the selection gate S3, and to realize a more reliable operation. As in the operation timing of FIG. 9A in FIG. 8A, FIG.
The operation timings of FIG. 9C in FIG. 8C and FIG. 9D in FIG. 8D are also effective.

The operation timing of FIG. 9E in FIG. 8E is obtained by reversing the polarity of the operation timing of FIGS. 8A to 8D, and the VS7 is controlled so that Qp1 is not turned on. Is set to the “L” level voltage VSL. FIG.
(D) and (e) can be used in portions other than the memory cells such as the row decoder and the sense amplifier.
The operation as shown in FIGS. 10D and 10E described later is possible.

The above-described embodiment is particularly effective as a means for preventing leakage of the boosted voltage when the boosted voltage higher than Vcc is charged on the bit line side (VBL side) or the drain side (VD side). However, the present invention is not limited to the above embodiment. For example, the case of FIG. 10 in which the bit line / drain side and the source side are switched at the operation timing of FIG. 9 is also effective.

FIGS. 10A to 10E respectively show FIGS.
3A illustrates operation timings of the circuit configurations of FIGS. FIG. 10 is basically the same as FIG. 9, except that the rise and fall of the source line are later than that of the bit line. In the case of FIG. 10, the bit line is set to the “H” level voltage in order to prevent the leakage of the “H” level voltage charged on the source side, and can be understood similarly to FIG. Further, the present invention is not limited to the above-described embodiments, and can be implemented with various modifications without departing from the scope of the invention.

[0046]

As described above, according to the present invention, the voltage of the source line is set to a voltage higher than the ground potential while the select gate on the bit line side is in the ON state during the data write operation. It is possible to realize an EEPROM capable of performing a highly reliable high-speed writing operation while suppressing an increase in area.

[Brief description of the drawings]

FIG. 1 is a NAND cell type EEPROM according to a first embodiment;
FIG. 2 is a block diagram illustrating a schematic configuration of an OM.

FIG. 2 is a layout and an equivalent circuit diagram of a NAND cell according to the first embodiment.

FIG. 3 is a sectional view taken along lines AA ′ and BB ′ of FIG. 2;

FIG. 4 is an equivalent circuit diagram of the memory cell array in the first embodiment.

FIG. 5 is a timing chart for explaining the operation of the first embodiment.

FIG. 6 is a diagram showing an arrangement example of an array, a decoder, and a sense amplifier / latch circuit on a chip, and a charge / discharge waveform of each part of SG2.

FIG. 7 is a diagram showing a cross-sectional configuration of a source-side selection gate and a rise in potential due to coupling of each part of SG2.

FIG. 8 is a circuit configuration diagram of an EEPROM according to a second embodiment.

FIG. 9 is a timing chart for explaining the operation in the second embodiment.

FIG. 10 is a timing chart for explaining the operation in the second embodiment.

FIG. 11 is another timing chart for explaining the data write operation of the conventional example.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 memory cell array 2 bit line control circuit 3 column decoder 4 address buffer 5 row decoder 6 data input / output buffer 7 substrate potential control circuit 8 source line potential control circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-58-185094 (JP, A) JP-A-2-40198 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 16/00-16/34

Claims (9)

(57) [Claims] 1. A memory cell array in which memory cell units each including a memory cell for storing data and a selection transistor are formed on a semiconductor substrate, a bit line connected to one end of the memory cell unit, and the memory A source line connected to the other end of the cell unit, wherein a first select transistor exists between the other end and the memory cell in the memory cell unit, and At the time of an operation in which part or all of the word line is higher than the power supply voltage and the first selection transistor in the selected memory cell unit is turned off,
The nonvolatile semiconductor memory device according to claim 1, wherein a voltage of the source line is higher than a minimum value of the bit line set voltage during the operation. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the minimum value of said bit line setting voltage is a ground potential. 3. A memory cell array in which memory cell units each including a memory cell for storing data and a selection transistor are formed on a semiconductor substrate, a bit line connected to one end of the memory cell unit, and the memory. A source line connected to the other end of the cell unit, wherein a first select transistor exists between the other end and the memory cell in the memory cell unit, and When the voltage of a part or all of the word line is higher than the power supply voltage and the first selection transistor in the selected memory cell unit is turned off, the gate voltage of the first selection transistor is set to the source line. A non-volatile semiconductor memory device, which is lower than the voltage of the non-volatile semiconductor memory device. 4. The nonvolatile semiconductor memory device according to claim 1, wherein a gate voltage of said first select transistor is set to a ground voltage during said operation. 5. The operation according to claim 1, wherein said operation is an operation of electrically rewriting by injecting electrons into a charge storage layer of said memory cell or emitting electrons from said charge storage layer. The nonvolatile semiconductor memory device according to any one of the above. 6. The nonvolatile semiconductor memory according to claim 1, wherein said operation is an operation of writing data by injecting electrons into a charge storage layer of said memory cell. apparatus. 7. The nonvolatile semiconductor memory device according to claim 1, wherein a second select transistor exists between said one end and said memory cell in said memory cell unit. 8. The non-volatile semiconductor device according to claim 1, wherein said memory cell unit is constituted by connecting a plurality of memory cells in series and connecting a selection transistor to both ends thereof. Storage device. 9. The non-volatile semiconductor device according to claim 1, wherein said memory cell unit is configured by connecting a plurality of memory cells in parallel and connecting a selection transistor to both ends thereof. Storage device.