JP3197119B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device (EEPROM) using an electrically rewritable memory cell having a charge storage layer (floating gate) and a control gate. The present invention relates to an EEPROM having a cell array.

[0002]

2. Description of the Related Art As one type of EEPROM, a NAND cell type EEPROM capable of high integration is known. In this method, a plurality of memory cells are connected in series in such a manner that their sources and drains are shared by adjacent ones, and connected to a bit line as one unit. A memory cell is usually a FETMOS with a floating gate and a control gate stacked.
Having a structure. The memory cell array is integrally formed in a p-type well formed on a p-type substrate or an n-type substrate. NA
The drain side of the ND cell is connected to a bit line via a selection gate, and the source side is also connected to a source line (reference potential wiring) via a selection gate. The control gates of the memory cells are arranged continuously in the row direction to form word lines.

The operation of this NAND cell type EEPROM is as follows. The data write operation is performed in order from the memory cell located farthest from the bit line. A high voltage Vpp (= 20 V) is applied to the control gate of the selected memory cell.
), And an intermediate voltage VppM (= 1) is applied to the control gate and the selection gate of the memory cell on the bit line side from that.
0V) and apply 0V to the bit line according to the data.
Alternatively, an intermediate potential is applied. When 0 V is applied to the bit line, the potential is transmitted to the drain of the selected memory cell, and electrons are injected from the drain to the floating gate. As a result, the threshold value of the selected memory cell shifts in the positive direction. This state is, for example, “1”. When the intermediate potential of the bit line is applied, electron injection does not occur,
Therefore, the threshold value does not change and remains negative. This state is "0".

[0004] Data erasure is performed simultaneously on all memory cells in a NAND cell. That is, all control gates and select gates are set to 0 V, the bit lines and source lines are set in a floating state, and a high voltage of 20 V is applied to the p-type well and the n-type substrate.
Is applied. As a result, in all the memory cells, electrons of the floating gate are emitted to the p-type well, and the threshold value shifts in the negative direction.

In a data read operation, the control gate of the selected memory cell is set to 0 V, the control gates and select gates of the other memory cells are set to the power supply potential Vcc (= 5 V), and whether a current flows in the selected memory cell is determined. This is done by detecting

The NAND cell type E performing the above operation
In the EPROM, a parasitic MOS transistor is formed in a field region along a control gate direction in order to apply a high voltage Vpp to a control gate of a memory cell during a write operation.
There is a problem that a leak current is generated between adjacent memory cells. In addition, since the width of element isolation cannot be increased so much to reduce the chip size, it becomes more difficult to eliminate the leak current. Similarly, a leak current between adjacent bit line contacts is also a serious problem.

[0007] As a solution to this problem, a parasitic voltage is applied to the p-type substrate or p-well in which the memory cell is formed by applying a voltage having a polarity opposite to the high voltage applied to the control gate, that is, a negative voltage. Apply a back bias to the transistor to prevent the parasitic transistor from turning on.
(Japanese Patent Application Laid-Open No. 1-25455). By using this proposal, the leak current between adjacent bit line contacts can be reduced. FIG. 14 shows a write operation using this proposal. Hereinafter, the conventional operation will be described with reference to FIG. 14 taking a case where CG1 is selected from CG1 to CG8 as an example.

When a write operation starts, first, a p-well (Cell
-p-well: The charging operation of Vss → V _N (V _N <0) of the p-type substrate or p-type well in which the memory cell is formed starts. Further, CG1 to CG8, SG1 in the selected block,
All the bit lines BL change from Vss to Vcc. Subsequently, all the bit lines are changed from Vcc to VppM (intermediate potential), and the CGs 1 to 8 in the selected block are changed from Vcc to VppM. Subsequently, after the p-well waited until completion of charging to V _N potential of the bit line "1" those connection data to the writing memory cell is vppm → Vss. Subsequently, CG1 in the selected block changes from VppM to Vpp, and data writing to the memory cell starts.

After maintaining this state for a while, CG1 in the selected block is changed from Vpp to Vss, CG1 to 8 and SG1 are set to Vpp.
→ Vss, and the writing of data to the memory cell ends. Subsequently, the bit line at VppM potential is
ppM → Vss. Also, p-well V _N → Vss, and the write operation is completed.

In FIG. 14, CG1 in the selected block
CG1 to CG8, S in each block when is at Vpp
FIG. 15 shows the voltages of G1 and SG2. In the operation of FIG. 14, CG1～8 load capacity in the selected block in charging the p-well to a negative voltage V _N, the capacitance between SG1~2 and p-well, in the unselected block CG1~8, SG1~ 2 and p
There are a capacity between wells, a capacity between a bit line and a p-well, a capacity between a source line (Cell-Source) and a p-well, and the like.
The volume between wells is dominant.

In the case of FIG. 14, CG1 in the non-selected block
-8 and SG1-2 are all fixed at Vss.
The well when the Vss → V _N, CG1~8, SG1~
14, the capacity between the ten wirings and the p-well must be fully charged. Therefore, since the load capacity is large, the required charging time becomes longer as shown by Ta in FIG.
Such a waiting time until the completion of charging is required.

In the method of fixing CG1-8, SG1 and SG2 in the non-selected block to Vss at the time of the write operation as shown in FIG. 14, since the load capacity of the negative voltage charging is large, the Tb of FIG. Such a waiting time is required, and it is difficult to realize a high-speed writing operation. Also, if the current supply capability of the negative voltage generation circuit is to be increased to realize a high speed operation, a large-sized capacitor or transistor is required, and the pattern area is increased.

[0013]

As described above, the conventional N
In the AND cell type EEPROM, it is difficult to shorten the time required for the write operation because of the large load capacity for negative voltage charging. To solve this problem, increasing the current supply capability of the negative voltage generating circuit increases the pattern area. There was a problem of doing it.

The present invention has been made in consideration of the above circumstances, and has as its object to reduce the time required for a write operation without increasing the pattern area. Is to provide.

[0015]

In order to solve the above problems, the present invention employs the following configuration.

That is, according to the present invention, there is provided a nonvolatile memory in which a charge storage layer and a control gate are stacked on a channel region and a plurality of memory cells for writing and erasing data by transferring charges between the charge storage layer and the substrate are arranged. In a nonvolatile semiconductor memory device, a memory cell is provided in a first conductivity type well formed on a first conductivity type substrate or a second conductivity type substrate, and data for selectively applying a high potential to a control gate in a selected block. During a write operation, a potential having a polarity opposite to a potential applied to the control gate in the selected block is applied to the control gate in the non-selected block together with the first conductivity type substrate or well.

According to the present invention, there is provided a nonvolatile memory comprising a charge storage layer and a control gate stacked on a channel region, and a plurality of memory cells for writing and erasing data by transferring charges between the charge storage layer and the substrate. In a nonvolatile semiconductor memory device, a memory cell is provided in a first conductivity type well formed on a first conductivity type substrate or a second conductivity type substrate, and during a data read operation in which a high potential is applied to a selection gate in a selection block. In addition, a potential opposite in polarity to a potential applied to the control gate in the selected block is applied to the control gate in the non-selected block together with the first conductivity type substrate or well.

Here, preferred embodiments of the present invention include the following.

(1) A plurality of memory cells are connected in series to form a NAND cell, and a block is formed from the plurality of NAND cells.

(2) Applying a high potential to one of the select gates in the selected block during a data write operation.

(3) At the time of data write operation, a high potential is applied to one select gate in the selected block and a potential of the opposite polarity is applied to the other select gate.

(4) Applying a potential of the opposite polarity to some or all of the selection gates in the non-selected block.

(5) Applying a potential of the opposite polarity to the source line of the memory cell.

[0024]

In the present invention, the first operation is performed before the start of the write operation.
When charging the conductivity type substrate or well (p-well) to a negative voltage, the control gate in the non-selected block is charged to the negative voltage at the same time. Therefore, the capacitance between the control gate and the first conductivity type substrate or well in the unselected block can be excluded from the load capacitance for negative voltage charging, and the load capacitance for negative voltage charging can be reduced. As a result, it is possible to shorten the time required for the operation including the operation of charging the first conductivity type substrate or the well where the memory cell is formed, to a negative voltage, such as a write operation, without increasing the pattern area much. It becomes possible.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.
FIG. 2 is a block diagram illustrating a schematic configuration of an AND cell type EEPROM. Write data to the memory cell array 1
A bit line control circuit 2 is provided for performing read, rewrite, and verify read. This bit line control circuit 2 is connected to a data input / output buffer 6 and receives as an input the output of a column decoder 3 that receives an address signal from an address buffer 4. A row decoder 5 is provided for controlling a control gate and a selection gate for the memory cell array 1, and a substrate potential for controlling a potential of a p substrate (or a p-type well) on which the memory cell array 1 is formed. A control circuit 7 is provided.

The bit line control circuit 2 is mainly composed of a CMOS flip-flop, and latches data for writing, senses the potential of a bit line, senses a verify read after writing, and rewrites. Latch data.

FIGS. 2A and 2B are a plan view and an equivalent circuit diagram of one NAND cell part of the memory cell array.
FIGS. 3A and 3B are views taken along the line AA 'in FIG.
And BB 'sectional drawing. A memory cell array including a plurality of NAND cells is formed on a p-type silicon substrate (or p-type well) 11 surrounded by an element isolation oxide film 12.

In this embodiment, eight memory cells M1 to M8 are connected in series to form one NAND cell. In each of the memory cells, a floating gate 14 (14 ₁ , 14 ₂ ,..., 14 ₈ ) is formed on a substrate 11 with a gate insulating film 13 interposed therebetween, and a control gate 16 with an interlayer insulating film 15 formed thereon.
(16 ₁ , 16 ₂ ,..., 16 ₈ ) are formed and configured. The memory cells are connected in series so that adjacent n-type diffusion layers 19, which are the source / drain of these memory cells, are commonly used.

The drain side of the NAND cell, respectively to the source side, a floating gate, selected simultaneously formed with the control gate gate 14 ₉ of the memory cells, 16 ₉ and 14 _10, 16 ₁₀
Is provided. The substrate on which the elements are formed is covered with a CVD oxide film 17, on which a bit line 18 is provided. The bit line 18 is in contact with the drain-side diffusion layer 19 at one end of the NAND cell. N lined up in the row direction
The control gate 14 of the AND cell is commonly connected to the control gate line C
G1, CG2,..., CG8. These control gate lines become word lines. Select gate 14 ₉ ,
16 ₉ and 14 _10, 16 ₁₀ are also arranged in each row direction successively selected gate lines SG1, SG2.

FIG. 4 shows an equivalent circuit of a memory cell array in which such NAND cells are arranged in a matrix.

The operation of this embodiment will be described below with reference to FIG. FIG. 5 shows the operation timing of each part in the memory cell at the time of the write operation. Below, CG1-8
The description will be made by taking as an example the case where CG1 is selected.

At the start of the write operation, first, SG2 in the selected block, CG1-8, SG1, S1 in the non-selected block.
V2 of G2 and p-well (p-type substrate or p-type well in which memory cells are formed), and source (source line of memory cells, common potential for all NAND cells)
→ The charging operation of V _N (V _N <0, for example, −1 V) starts. Further, CG1 to CG8, SG1 in the selected block,
All the bit lines BL change from Vss to Vcc.

Next, all the bit lines are changed from Vcc to VppM.
(Voltage higher than Vcc, for example, 10 V). continue,
CG1 to CG8 in the selected block change from Vcc to VppM. During (or after) the charging operation of Vcc → VppM,
The bit line connected to the memory cell to which "1" data is written becomes VppM → Vss. At this time, the load capacity of the negative voltage in the present embodiment as described below is much smaller than the conventional, p-well it has completed already charging of the negative voltage V _N, complete charging as in the prior art (Tb in FIG. 14) is not required.

Next, CG1 in the selected block is set to VppM
→ Vpp (voltage higher than VppM, for example, 20 V)
Writing of data to the memory cell starts. After keeping this state for a while, CG1 in the selected block is changed from Vpp → Vs
s, CG2 to 8 and SG1 change from VppM to Vss, and the data writing to the memory cell ends. Subsequently, the bit line at VppM potential becomes VppM → Vss. Further, the portion at the potential V _N becomes V _N → Vss, and the write operation ends.

In FIG. 5, CG1 in the selected block is V
CG1-8, SG1, S1 in each block when at pp
FIG. 6 shows the voltage of G2. By using the operation method shown in FIG. 5, for reasons explained below, the time required for ☆ portion in FIG. 5 without so much increasing the pattern area, i.e. significantly the time for a p-well and Vss → V _N can shorten the, T in latency (Fig. 14 complete charging voltage V _N
Since b) becomes unnecessary, it is possible to realize a high-speed write operation.

Next, the reason why the portion of Tc in FIG. 5 can be shortened will be described. Load capacity in charging the p-well to a negative voltage V _N, as can be seen from FIG. 3, the capacitance between CG1~8, SG1~2 a p-well in the selected block, CG1～8 in the unselected block , SG1-2 and the p-well, the capacitance between the bit line and the p-well, and the capacitance between the source line and the p-well. Further, when the memory cells are integrally formed in the p-type well formed on the n-type substrate, the capacitance between the n-type substrate and the p-well is also added.

The dominant of these capacitances is CG1
-8, SG1 and SG2, and the capacitance between the p-well. Particularly, in a normal write operation, there is one selected block and the rest are unselected blocks (see FIG. 6).
-8, the capacitance between SG1-2 and the p-well is dominant.
In particular, when the data of the memory cell is all "1", the memory cell and the surface of the p-type well or the p-type substrate are in a charge accumulation state (accumulation region).
The capacitance between the CGs 1 to 8 and SGs 1 and 2 in the non-selected blocks and the p-well takes the maximum value, and therefore the load capacitance of the p-well becomes maximum.

As in the conventional method, C in the non-selected block
G1～8, when fixed at the potential Vss during a write operation the SG1~2, CG1~8 unselected blocks the p-well in the Vss → V _N, the total capacity of between SG1～2 and p-well must take into charging, load capacity of the negative voltage V _N becomes larger. To charge a large capacity, a negative voltage generating circuit having a high supply capability is required. However, in order to increase the supply capability of the negative voltage generating circuit, large-sized capacitors and transistors are required, and the pattern area is increased. There is.

In this embodiment, during the write operation, CG1 to CG8 and SG1 to SG2 in the non-selected block are set to
Since ss → V _N , there is no need to charge the capacitance between the CGs 1 to 8 and SGs 1 and 2 in the non-selected block and the p-well, which is the dominant capacitance described above, and the load capacitance of the negative voltage V _N Can be reduced. When this method is used, a negative voltage is transferred through the row decoder in FIG. 1, so that the p-well in which the row decoder is formed must have a negative voltage. It is sufficiently small compared to, and the increase in peripheral circuits by using this method is also
Significantly less. Therefore, according to the present embodiment, even if a negative voltage generating circuit having a relatively small supply capability is used, that is, it is possible to realize a drastic increase in writing speed while keeping the pattern area small.

In this embodiment, SG in the selected block
Since even 2 or sources are the same as Vss → V _N and p-well, even so not applied to the load capacitance of V _N capacitance between SG2 and source and p-well in the selected block. Therefore, as compared with the case of fixing the SG2 in the source and the selected block to Vss, it can be advantageously further reduced load capacity of the negative voltage V _N.

FIG. 7 is a timing chart for explaining the second embodiment of the present invention. Although the device configuration and the basic operation are the same as those of the first embodiment, in this embodiment, the potential of the source line during the data write operation is kept constant.

In this case, during the write operation, Vss → V _N → V
Although the load capacity of the p-well is increased to reduce the ss portion, only the capacity between the source and the p-well is added to the load capacity of the p-well. Is not a typical part,
The load capacity of the p-well can be significantly reduced as compared with the conventional method. In addition, since it is not necessary to treat a negative potential in the source line potential control circuit in the peripheral circuit, an extra circuit such as a negative voltage switching circuit is unnecessary when the source line potential control circuit is not provided, and the pattern area of the peripheral circuit is reduced. There are advantages that can be done.

FIG. 8 is a timing chart for explaining the third embodiment of the present invention. Although the device configuration and the basic operation are the same as those of the first embodiment, in this embodiment, the potential of the source line and the potential of the selection gate SG2 of the selected block during the data writing operation are fixed.

[0045] In this case, as in the second embodiment, the load capacitance of the p-well to reduce the portion serving as during a write operation Vss → V _N → Vss increases still join the load capacity of the p-well Is the capacitance between the source and the p-well and the two capacitances SG2 in the selected block, which are not the dominant parts of the load capacitance of the p-well in the conventional method. It can be greatly reduced in comparison. Further, similarly to the second embodiment, there is no need to treat a negative potential in the source line potential control circuit and the SG2 potential control circuit in the peripheral circuit.
An extra circuit such as a negative voltage switching circuit is not required in the source line / SG2 potential control circuit, and there is an advantage that the area of the peripheral circuit can be reduced.

FIG. 9 is a timing chart for explaining the fourth embodiment of the present invention. In this embodiment, the second and third
In addition to the source line and the selection gate SG2 of the selected block described in the embodiment, the selection gate SG2 of the non-selected block
Is constant during the data write operation.

In the case of this embodiment, S in the non-selected block
The capacitance between the portion of G2 and the p-well adds to the load capacitance of the p-well, but CG1-8, SG1
Since there are 10 wirings of ~ 2, even if the capacitance between one of them and the p-well is added as the load capacitance of the p-well, the load capacitance of the p-well can be reduced to about 1/10 as compared with the conventional method. In addition, the writing operation can be significantly speeded up as compared with the conventional method. Further, similar to the second and third embodiments, the number of parts for handling the negative voltage in the peripheral circuit is reduced, so that an extra circuit such as a partial negative voltage switching circuit is not required, and the area of the peripheral circuit can be reduced. There is.

When the potential of SG2 is the same in the selected block and the non-selected block as shown in FIGS. 5, 7, and 9, the potential of SG2 in all NAND cells is the same. Need not be decoded (the voltage is switched differently between the selected block and the non-selected block), and the pattern area of the row decoder portion can be reduced.

In the above embodiment, the case where CG1 is selected from CG1 to CG8 has been described as an example.
Even when any of CG2 to CG8 is selected instead of CG1, the write operation can be performed in the same manner if the timing of the selected one of CG2 to CG8 is replaced with CG1 in the above embodiment. Further, in the above embodiment, the NAND
The operation when the number of memory cells between the select gates SG1 and SG2 in the cell is eight has been described.
The same operation can be performed even when the number of memory cells between the two is different, such as 4, 16, 32 or the like.

Further, in the above-described embodiment, the method of reducing the load capacitance of the negative voltage when the p-well is charged to the negative voltage in the write operation has been described. However, the present invention is not limited to the write operation. , For example, when the p-well is charged to a negative voltage in a read operation or the like. Hereinafter, an embodiment applied to a read operation will be described.

FIG. 10 is a timing chart for explaining the fifth embodiment of the present invention, and FIG. 11 is a diagram showing voltages applied to the gates in each block in the fifth embodiment. This embodiment is a case where 0 V is applied to all CGs in the selected block at the time of data read operation, and a negative voltage is applied to the p-well, that is, a state in which a back bias is applied to the memory cell, and a voltage is applied to the memory cell in the NAND. This is an operation for checking whether or not all threshold voltages are negative, and is an effective operation when verifying the threshold voltage of a memory cell after an erase operation.

By setting CG and SG in the unselected block to the same negative voltage as the p-well, the load capacitance of the negative voltage can be reduced as in the case of the write operation. Also, in the read operation, the CG of the R portion in FIG.
It goes without saying that the present invention is also effective when (CG1-8) is set to a negative voltage instead of 0V.

FIG. 12 is a timing chart for explaining the sixth embodiment of the present invention, and FIG. 13 is a diagram showing voltages applied to gates in each block in the sixth embodiment. This embodiment is a case where 0 V is applied to only one selected CG in the selected block at the time of a read operation, and is selected in a state where a negative voltage is applied to the p-well, that is, a back bias is applied to the memory cell. This is an operation for checking whether the threshold voltage of the selected memory cell is negative, and is effective for checking the threshold voltage of the selected memory cell.

Also in this embodiment, by setting CG and SG in the unselected block to the same negative voltage as the p-well, the load capacity of the negative voltage can be reduced as in the case of the write operation. In the read operation, FIG.
Needless to say, the present invention is also effective when the CG (only CG1) of the R portion in 2 is set to a negative voltage instead of 0V.

The present invention is not limited to the above embodiments. In the embodiment, the NAND cell type EEP
Although only the case where the present invention is applied to a ROM has been described, the present invention is not limited to the NAND cell type EEPROM, but is also effective for memories having other structures. Others
Various modifications can be made without departing from the scope of the present invention.

[0056]

As described above, according to the present invention, when a negative voltage is charged to a p-type substrate or a p-type well on which a memory cell is formed by a write operation or the like, the load capacitance of the negative voltage is reduced. Can be smaller. Therefore, it is possible to obtain an EEPROM that realizes a high-speed operation such as a write operation including an operation of charging a p-type substrate or a p-type well on which a memory cell is formed to a negative voltage without increasing the pattern area much. it can.

[Brief description of the drawings]

FIG. 1 is a NAND cell type EEPROM according to a first embodiment;
FIG. 2 is a block diagram illustrating a configuration of an OM.

FIG. 2 is a plan view and an equivalent circuit diagram showing a NAND cell configuration in the first embodiment.

FIG. 3 is a sectional view taken along arrows AA ′ and BB ′ in FIG.

FIG. 4 is an equivalent circuit diagram of the memory cell array in the first embodiment.

FIG. 5 is a timing chart for explaining the operation of the first embodiment.

FIG. 6 is a diagram showing a voltage applied to a gate in each block in the first embodiment.

FIG. 7 is a timing chart for explaining the operation of the second embodiment.

FIG. 8 is a timing chart for explaining the operation of the third embodiment.

FIG. 9 is a timing chart for explaining the operation of the fourth embodiment.

FIG. 10 is a timing chart for explaining the operation of the fifth embodiment.

FIG. 11 is a diagram showing a voltage applied to a gate in each block in the fifth embodiment.

FIG. 12 is a timing chart for explaining the operation of the sixth embodiment.

FIG. 13 is a diagram showing a voltage applied to a gate in each block in the sixth embodiment.

FIG. 14 is a timing chart for explaining the operation of a conventional EEPROM.

FIG. 15 is a diagram showing a voltage applied to a gate in each block in a conventional example.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 memory cell array 2 bit line control circuit 3 column decoder 4 address buffer 5 row decoder 6 data input / output buffer 7 substrate buffer circuit 14 floating gate (charge storage layer) 16 control gate 18 bit line 20 ... NAND cell block.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masaki Mochitomi 1 Toshiba-cho, Komukai, Kawasaki-shi, Kanagawa Prefecture Inside the Toshiba R & D Center (72) Inventor Hideko Ohira Toshiba, Komukai-shi, Kawasaki-shi, Kanagawa No. 1, Toshiba Research and Development Center Co., Ltd. (56) References JP-A-4-276389 (JP, A) JP-A-3-88199 (JP, A) JP-A-62-26697 (JP, A) (58) ) Surveyed field (Int.Cl. ⁷ , DB name) H01L 21/8247 G11C 16/02 H01L 27/115 H01L 29/788 H01L 29/792

Claims (2)

(57) [Claims] A nonvolatile semiconductor memory in which a charge storage layer and a control gate are stacked on a channel region, and a plurality of memory cells for writing and erasing data by transferring charges between the charge storage layer and the substrate are arranged. In the device, the memory cell is provided in a first conductivity type well formed on a first conductivity type substrate or a second conductivity type substrate, and a data write operation for selectively applying a high potential to a control gate in a selected block. A non-volatile semiconductor, wherein a potential having a polarity opposite to a potential applied to the control gate in the selected block is applied to the control gate in the non-selected block together with the first conductivity type substrate or well. Storage device. 2. A nonvolatile semiconductor memory in which a charge storage layer and a control gate are stacked on a channel region, and a plurality of memory cells for writing and erasing data by transferring charges between the charge storage layer and the substrate are arranged. In the device, the memory cell is provided in a first conductivity type well formed on a first conductivity type substrate or a second conductivity type substrate, and performs a data read operation for applying a high potential to a selection gate in a selection block. A nonvolatile semiconductor memory device wherein a potential having a polarity opposite to a potential applied to a control gate in a selected block is applied to a control gate in a non-selected block together with a first conductivity type substrate or well.