JPH0963283A - Nonvolatile memory element of semiconductor and its using method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable electron to inject by FN tunneling from a channel without increasing the occupied area of memory cells and to prevent wrong writing owing to hot transient electron. SOLUTION: A nonvolatile memory element of a semiconductor is provided with plural memory cells 1-4, a capacitor 17 shared with memory cells 1, 3 and a capacitor 18 shared with memory cells 2, 4. The source of memory transistors 21 of respective memory cells 1-4 is terminated by capacitors 17, 18. Electron is injected into a floating gate 25 by FN tunneling from a channel in the case of writing. The transfer of electron between capacitors 17, 18 and bit lines 13, 14 is detected in the case of reading-out.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to F from a channel.
The present invention relates to a semiconductor nonvolatile memory element in which electrons are injected by N (Fowler Nordheim) tunneling and a method of using the same.

[0002]

2. Description of the Related Art With the recent widespread development of portable information terminal equipment, the need for a large-capacity EEPROM (electrically erasable programmable read only memory) is increasing as an external storage device. EE as an external storage device
When using a PROM, it is necessary to lower the voltage of the rewriting operation and improve the reliability. For that purpose, it has been shown that a method in which electrons are taken in and out of a floating gate or the like in writing and erasing data by FN tunneling using the entire surface of the channel (Nikkei Microdevice, May 1992, No. 1). 45 to 50 pages).

FIG. 4 is a circuit diagram showing an example of the configuration of a memory element in a conventional EEPROM. This memory device includes a plurality of memory cells 101, 10 arranged in a matrix.
2, 103, 104 and a plurality of word lines 1 corresponding to rows
11, 112 and a plurality of bit lines 113 corresponding to columns
114 and a common source line 115 corresponding to the bit lines 113, 114. The word line 111 is connected to the control gates of the memory transistors of the memory cells 101 and 102 in one row, and the word line 112 is connected to the control gates of the memory transistors of the memory cells 103 and 104 in one row. The bit lines 113 are connected to the drains of the memory transistors of the memory cells 101 and 103 in one column, and the bit lines 114 are connected to the memory cells 10 in one column.
The drains of the memory transistors 2, 104 are connected. The source line 115 includes the memory cells 101, 10
The sources of the memory transistors 2, 103 and 104 are connected.

[0004]

However, the memory device shown in FIG. 4 has the following problems when the FN injection of electrons is performed using the entire surface of the channel. That is, for example, when writing to the memory cell 101, the control gate (word line 111) is set to a high potential of 18V, the bit line 113 is set to a low potential of 0V, and the source line 115 is set.
Is performed in a floating state. At this time, the non-selected bit line 114 is set to the intermediate potential of 9 V and the non-selected cell 1
02 erroneous writing is prevented. However, when the source line 115 is connected to both the selected cell 101 and the non-selected cell 102, the low potential of the bit line 113 is the source line 1
The electrons are applied to the diffusion layer of the memory transistor of the non-selected cell 102 via 15 and electrons are also injected into the non-selected cell 102. Further, since the memory transistor of the cell 102 is also turned on, the bit lines 113 and 114 set to different potentials are electrically connected.

Therefore, the above-mentioned Nikkei microdevice, 1
As shown in the May 992 issue, pages 45 to 50, a method of separately forming a source line corresponding to each bit line has been proposed. FIG. 5 is a circuit diagram showing a configuration of a memory element according to this method. In the configuration shown in this figure, the source line 115 corresponding to the bit line 113,
It is the same as FIG. 4 except that the source line 116 corresponding to the bit line 114 is formed separately. But,
In this configuration, one cell has two wirings, which causes a problem that the memory cell area becomes large. Further, in this configuration, for example, when the non-selected bit line 114 is raised to the intermediate potential when writing to the cell 101, an excessive current flows by charging the source line 116 in a floating state. Since the source line 116 is shared by a plurality of cells in the bit line direction, its capacity is considerably large, and hot electrons are generated during its charging,
There is a problem that the non-selected cells 102 are erroneously written.

The present invention has been made in view of the above problems, and an object thereof is to enable injection of electrons by FN tunneling from a channel without increasing an occupied area of a memory cell, and to further excessive hot electrons. It is an object of the present invention to provide a semiconductor non-volatile memory device capable of preventing erroneous writing due to memory and a method of using the same.

[0007]

A semiconductor non-volatile memory device according to claim 1, wherein the memory cell comprises one memory transistor and a capacitor shared by a plurality of memory cells, and the memory transistor comprises a drain and a source. , A control gate and a charge storage unit, the control gate is connected to the word line, one of the drain and the source is connected to the bit line, and the other of the drain and the source is connected to the capacitor.

In this semiconductor nonvolatile memory element, since the source line is removed from the memory cell, it is not necessary to consider the layout of the inter-cell wiring of the source line, and the memory cell can be miniaturized. Further, since the capacitance of the capacitor can be set to be much smaller than that of the source line, there is no problem of erroneous writing due to hot electrons during charging.

A semiconductor non-volatile memory device according to a second aspect is the semiconductor non-volatile memory device according to the first aspect, in which a charge storage portion is provided between a drain-source channel formation region and a control gate. It is a floating gate.

A semiconductor non-volatile memory device according to a third aspect is the semiconductor non-volatile memory device according to the first aspect, wherein the memory transistor has a laminated insulating film between the channel forming region between the drain and the source and the control gate. Have,
The interface of this laminated insulating film is configured to serve as a charge storage portion.

According to a fourth aspect of the present invention, in the semiconductor non-volatile memory element according to the third aspect, the laminated insulating film is a laminated film of an oxide film and a nitride film.

According to a fifth aspect of the present invention, there is provided a method of using a semiconductor non-volatile memory device, wherein a memory cell comprises one memory transistor and a capacitor shared by a plurality of memory cells, and the memory transistor comprises a drain, a source and a control gate. And a charge storage portion, a control gate is connected to a word line, one of a drain and a source is connected to a bit line, and the other of the drain and the source is connected to a capacitor. Therefore, data is written by injecting electrons from the bit line to the charge storage portion of the memory transistor by using Fowler-Nordheim tunneling.

According to another aspect of the semiconductor non-volatile memory device of the present invention, the memory cell includes one memory transistor and a capacitor shared by the plurality of memory cells, and the memory transistor includes a drain, a source and a control gate. And a charge storage portion, a control gate is connected to a word line, one of a drain and a source is connected to a bit line, and the other of the drain and the source is connected to a capacitor. Therefore, the data is read by detecting the movement of the charge between the capacitor and the bit line.

According to a seventh aspect of the present invention, there is provided a method of using the semiconductor non-volatile memory element according to the sixth aspect, wherein in reading data, first, an all-erased memory of the semiconductor non-volatile memory element is first read. Data is read by charging the capacitor of the cell with a predetermined potential, then selecting the word line, and detecting the movement of the charge between the capacitor and the bit line.

A method of using the semiconductor non-volatile memory element according to claim 8 is the method of using the semiconductor non-volatile memory element according to claim 6, wherein the capacitors of all the erased memory cells of the semiconductor non-volatile memory element are set to a predetermined potential. The charging operation is performed at regular intervals.

According to a ninth aspect of the present invention, there is provided a semiconductor non-volatile memory device, wherein a memory cell has a memory transistor array composed of a plurality of memory transistors connected in series capable of individually retaining data, one selection transistor, and a plurality of memory cells. The memory transistor has a capacitor shared by the memory cells, the memory transistor has a drain, a source, a control gate, and a charge storage portion, the control gate is connected to the word line, and the selection transistor is connected to one end of the memory transistor string and the bit line. And the capacitor is connected to the other end of the memory transistor array.

In this semiconductor non-volatile memory device, the source line is removed from the memory cell as in the semiconductor non-volatile memory device according to claim 1, so it is necessary to consider the layout of the inter-cell wiring of the source line. In addition, the memory cell can be downsized, and the capacitance of the capacitor can be set to be much smaller than that of the source line.
There is no problem of erroneous writing due to hot electrons during the charging.

A semiconductor non-volatile memory element according to a tenth aspect is the semiconductor non-volatile memory element according to the ninth aspect, wherein a charge storage portion is provided between a drain-source channel forming region and a control gate. It is a floating gate.

The semiconductor non-volatile memory element according to claim 11 is the semiconductor non-volatile memory element according to claim 9, wherein the memory transistor has a laminated insulating film between the channel forming region between the drain and the source and the control gate. Have,
The interface of this laminated insulating film is configured to serve as a charge storage portion.

According to a twelfth aspect of the present invention, there is provided the semiconductor non-volatile memory element according to the eleventh aspect, wherein the laminated insulating film is a laminated film of an oxide film and a nitride film.

According to a thirteenth aspect of the present invention, there is provided a method of using a semiconductor non-volatile memory device, wherein a memory cell includes a memory transistor array consisting of a plurality of memory transistors connected in series capable of individually retaining data, and one selection transistor. , A capacitor shared by a plurality of memory cells, the memory transistor has a drain, a source, a control gate and a charge storage portion, the control gate is connected to the word line, and the selection transistor is connected to one end of the memory transistor string. A method of using a semiconductor non-volatile memory device in which a capacitor is connected to the other end of a memory transistor array, which is interposed between the bit line and a memory cell, and is used for Fowler-Nordheim tunneling from the bit line to the charge storage portion of the memory transistor. Is used to inject electrons to write data.

According to a fourteenth aspect of the present invention, there is provided a method of using a semiconductor non-volatile memory device, wherein a memory cell includes a memory transistor array composed of a plurality of memory transistors connected in series capable of individually retaining data, and one selection transistor. , A capacitor shared by a plurality of memory cells, the memory transistor has a drain, a source, a control gate and a charge storage portion, the control gate is connected to the word line, and the selection transistor is connected to one end of the memory transistor string. A method of using a semiconductor non-volatile memory device, in which a capacitor is connected to the other end of a memory transistor string, which is interposed between a bit line and a capacitor, and is used to detect data transfer by detecting charge transfer between the capacitor and the bit line. Is read out.

A method of using the semiconductor non-volatile memory device according to claim 15 is the method of using the semiconductor non-volatile memory device according to claim 14, wherein when reading data,
First, the capacitors of all erased memory cells of a semiconductor nonvolatile memory element are charged with a predetermined potential, and then a word line is selected and data transfer is performed by detecting charge transfer between the capacitors and bit lines. Is.

A method of using the semiconductor non-volatile memory element according to claim 16 is the method of using the semiconductor non-volatile memory element according to claim 14, wherein the capacitors of all the erased memory cells of the semiconductor non-volatile memory element are set to a predetermined potential. The charging operation is performed at regular intervals.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of a semiconductor nonvolatile memory element according to the first embodiment of the present invention.

This semiconductor nonvolatile memory device includes a plurality of memory cells 1, 2, 3, 4 arranged in a matrix, a plurality of word lines 11 and 12 corresponding to rows, and a plurality of bits corresponding to columns. The lines 13 and 14, the capacitor 17 shared by the two memory cells 1 and 3, and the two memory cells 2 and 4.
And the capacitor 18 shared in common. Each memory cell 1, 2, 3, 4 has a memory transistor 21,
The memory transistor 21 has a drain 22 and a source 2
3, it has a control gate 24 and a floating gate 25.

The word line 11 has one row of memory cells 1 and 2.
The control gate 24 of the memory transistor 21 is connected to the word line 12 and the control gate 24 of the memory transistor 21 of the memory cells 3 and 4 in one row is connected to the word line 12.
The bit line 13 is connected to one of the drain and source of the memory transistors 21 of the memory cells 1 and 3 in a row, here the drain 22, and to the bit line 14 of the memory transistors 21 of the memory cells 2 and 4 in a row. One of the drain and the source, here the drain 22, is connected.
The other of the drain and the source of the memory transistors 21 of the memory cells 1 and 3 in one row, here, the source 23, is connected to one end of the shared capacitor 17, and the drain and the source of the memory transistors 21 of the memory cells 2 and 4 in one row are connected. On the other hand, here the source 23 is the shared capacitor 18
Is connected to one end. The other ends of the capacitors 17 and 18 are grounded.

FIG. 2 shows a sectional structure of the memory cells 1 and 3 in the semiconductor nonvolatile memory device shown in FIG. As shown in this figure, the insulating film 26 is formed on the channel formation region between the drain and the source of the silicon substrate 20.
Through each memory transistor 21 of the memory cells 1 and 3
Floating gate 25 is formed, and control gate 24 (word line 11, 1
2) is formed. Note that the memory transistor does not have a floating gate, a laminated insulating film is used as a gate insulating film between the channel formation region and the control gate, and charges are accumulated at the interface of the laminated insulating film (MNOS, M
ONOS, MAOS, etc.) may be used. In this case, the laminated insulating film is, for example, a laminated film (ONO film) of an oxide film and a nitride film.
Film: SiO ₂ / Si ₃ N ₄ / SiO ₂ ) is used.

A common source 23 is formed on the silicon substrate 20 at a position between the floating gate 25 of the memory cell 1 and the floating gate 25 of the memory cell 3, and a position facing the source 23 with each floating gate 25 interposed therebetween. Each drain 2
2 is formed. The bit line 13 is connected to the drain 22. A capacitor electrode 1 is provided on the source 23.
7a is formed, and the ground line 27 is formed thereon via the capacitor insulating film 17b. The capacitor 17 composed of the capacitor electrode 17a and the capacitor insulating film 17b is laminated on the word lines 11 and 12,
It has a so-called stack capacitor structure. However,
Since the capacitor 17 is formed over the two memory cells 1 and 3, it is possible to secure a large capacity and a large signal with a simple structure. Further, since there is almost no area penalty due to the capacitor 17, it is possible to reduce the cell area by the amount of the source wiring reduced.

Next, the method of use and operation of the semiconductor nonvolatile memory element according to this embodiment will be described.

First, the write operation will be described by taking the case of writing data in the memory cell 1 as an example. When writing to the memory cell 1, the bit line 13 is grounded and the word line 11 is set to, for example, 18V. As a result, a channel is induced in the memory transistor 21 of the memory cell 1, and electrons are injected into the floating gate 25 by FN tunneling. When the memory transistor is of a type that does not have a floating gate and uses a laminated insulating film as the gate insulating film between the channel formation region and the control gate and accumulates charges at the interface of the laminated insulating film, , Electrons are injected into the interface of the laminated insulating film by FN tunneling. On the other hand, the non-selected bit line 14 and word line 12 are 9V
Is kept at an intermediate potential of, and writing to non-selected cells is prevented. In the present embodiment, the source 23 of the memory transistor 21 is terminated by the capacitors 17 and 18. Therefore, unlike the conventional example shown in FIG. 4, there is no problem that an extra through current flows or erroneous writing occurs in other cells. Furthermore, since the capacitance of the capacitors 17 and 18 is smaller than the capacitance of the source line in the conventional example by about one digit, almost no current flows during writing. Therefore, erroneous writing due to hot electrons rarely occurs in the non-selected cells.

Next, the read operation will be explained by taking the case of reading the data stored in the memory cell 1 as an example. First, before starting reading, as a preparatory operation, all word lines 11 and 12 in the array are set to 3 V, for example, and the bit lines 13 and 14 are grounded. At this time, for example, if the memory cell 1 is in the erased state, the memory transistor 21 is turned on and the node potential of the corresponding capacitor 17 also becomes 0V. Here, the word lines 11 and 12 are once closed, and the charge for reading is stored in the capacitor 17. After that, the same reading as in a normal DRAM (dynamic random access memory) is performed. That is, all bit lines 1
Equalize 3 and 14 to 3V to make them floating, and then turn on the selected word line 11 to 3V. By this operation, for example, if the memory cell 1 is in the erased state, the charge held in the capacitor 17 flows into the bit line 13, the potential of the bit line 13 is lowered, and data is read. On the other hand, when the memory cell 1 is in the written state, the potential of the bit line 13 does not change. As described above, in the present embodiment, the data is read by detecting the movement of the charge between the capacitor 17 and the bit line 13.

Since the read data is amplified by the sense amplifier, 0V is written in the capacitor 17 again when the memory cell 1 is in the erased state.
Therefore, if the above-described preparation operation is performed once, it is not necessary to repeat the preparation operation each time each memory cell is read, and highly flexible reading is possible.

However, since the charges of the capacitors 17 and 18 corresponding to the unread bits are gradually deteriorated, the above-described preparatory operation is performed at regular intervals.
18 needs to be refreshed. Unlike the DRAM refresh in which charging of one capacitor charges and discharges of one bit line, in the present embodiment, the bit line 13,
Most of the charges sent to 14 are efficiently stored in capacitor 1
Used to charge 7,18. Therefore, it is not necessary to perform frequent refreshing in units of word lines as in DRAM, but it may be performed at intervals of, for example, 1 msec to 100 msec in array or chip units.

Further, the capacitors 17, 1 by the preparatory operation
The set potential of 8 may be the power supply voltage Vcc level instead of 0V. When the set potential of the capacitors 17 and 18 in the preparatory operation is Vcc, the bit lines 13 and 14 are equalized at 0V. However, if the capacitors 17 and 18 are set to Vcc, they are easily affected by the soft error, so it is desirable to set them to 0V.

As described above, according to the present embodiment, since the source lines are removed from the memory cells 1 to 4, it is not necessary to consider the layout of the inter-cell wiring of the source lines, and the memory cells 1 to 4 can be miniaturized. Further, since the capacitances of the capacitors 17 and 18 can be set to be much smaller than that of the source line, there is no problem that erroneous writing due to hot electrons occurs during charging.

FIG. 3 is a circuit diagram showing the configuration of a semiconductor nonvolatile memory element according to the second embodiment of the present invention. The present embodiment is an example in which the present invention is applied to a NAND type cell.

This semiconductor nonvolatile memory device includes a plurality of memory cells 31, 32, 33 and 34, a plurality of word lines 61 to 64 and 71 to 74 corresponding to rows, and a plurality of bit lines 83 corresponding to columns. , 84 and two memory cells 31,
A capacitor 37 shared by 33 and a capacitor 38 shared by the two memory cells 32, 34 are provided. Each of the memory cells 31 and 32 has a memory transistor array composed of a plurality of memory transistors 41 to 44 connected in series capable of individually retaining data, and one selection transistor 45. Similarly, each of the memory cells 33 and 34 has a plurality of series-connected memory transistors 51 to 54 capable of individually retaining data.
And a selection transistor 55.

Each memory transistor 41-44, 51-
54 has a drain, a source, a control gate and a floating gate, respectively. Memory transistors 41 to 4
Control gates 4 are connected to word lines 61-64. Similarly, the control gates of the memory transistors 51 to 54 are connected to the word lines 71 to 74, respectively. The selection transistor 45 is interposed between one end of the memory transistor columns 41 to 44, that is, between the memory transistor 41 and the bit lines 83 and 84, and the selection transistor 55 is one end of the memory transistor columns 51 to 54, that is, the memory transistor 54 and the bit. It is interposed between the wires 83 and 84. One ends of the capacitors 37 and 38 are
The other end of the memory transistor columns 41 to 44, that is, the memory transistor 44, and the memory transistor columns 51 to 51.
The other end of 54 is connected to the memory transistor 51. The other ends of the capacitors 37 and 38 are grounded. The gates 65 of the selection transistors 45 of the memory cells 31 and 32 are connected to each other, and the gates 75 of the selection transistors 55 of the memory cells 33 and 34 are also connected to each other.

The memory transistor does not have a floating gate, a laminated insulating film is used as a gate insulating film between the channel formation region and the control gate, and a type (that accumulates charges at the interface of the laminated insulating film is used). MNOS, MONOS,
MAOS etc.) may be used. In this case, as the laminated insulating film, for example, a laminated film of an oxide film and a nitride film (ONO film; SiO
₂ / Si ₃ N ₄ / SiO ₂ ) is used.

Next, a method of using and operation of the semiconductor nonvolatile memory element according to this embodiment will be described.

First, the write operation will be described by taking the case of writing data in the memory transistor 43 of the memory cell 31 as an example. In this case, first, the gate 65 of the selection transistor 45 is turned on to 3V, the selected word line 63 is set to 18V, and the unselected word lines 61, 62, 64, and
71 to 74 and the non-selected bit line 84 are set to 9V. If the selected bit line 83 is set to 0V in this state, electrons are injected into the memory transistor 43. At this time, the state of the selection transistor 55 may be either on or off. In this example, the written memory transistor is in the enhanced state and the erased memory transistor is in the depression state.

At the time of reading, after the preparatory operation similar to that in the first embodiment is performed, the bit lines 83 and 8 are read.
4 is equalized to 3V and, for example, the selection transistor 45
Gate 65 of 3V, gate 7 of select transistor 55
5 is set to 0V, non-selected word lines 61, 62 and 64 are set to 3V, and the selected word line 64 is set to 0V. With this, if the memory transistor 43 is in the erased state, electrons flow to the bit line 83, and the potential of the bit line 83 decreases. If the memory transistor 43 is in the written state, the potential of the bit line 83 does not change. In this way, similarly to the first embodiment, data is read by detecting the movement of charges between the capacitor 37 and the bit line 83. Other operations such as the refresh operation in this embodiment are the same as those in the first embodiment.

By the way, in the conventional NAND type cell,
A pair of isolation transistors was connected to the positions of the capacitors 37 and 38 with the source line interposed therebetween. In the present embodiment, this separating transistor is connected to one capacitor 37,
By replacing with 38, the cell area is greatly reduced.
The other effects of this embodiment are similar to those of the first embodiment.

[0046]

As described above, according to the semiconductor nonvolatile memory device of the present invention and the method of using the same, the source line is removed from the memory cell and the source of the memory transistor is terminated by the capacitor. It becomes possible to inject electrons by FN tunneling from the channel without increasing the occupied area.
Since the capacitance of the capacitor can be set to be much smaller than that of the source line, there is an effect that erroneous writing due to excessive hot electrons can be prevented.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor nonvolatile memory element according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a cross-sectional structure of a memory cell in the semiconductor nonvolatile memory element shown in FIG.

FIG. 3 is a circuit diagram showing a configuration of a semiconductor nonvolatile memory element according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing an example of a configuration of a memory element in a conventional EEPROM.

FIG. 5 is a circuit diagram showing another example of the configuration of the memory element in the conventional EEPROM.

[Explanation of symbols]

 1-4 memory cells 11 and 12 word lines 13 and 14 bit lines 17 and 18 capacitors 21 memory transistors

Claims (16)

[Claims] 1. A memory cell comprises one memory transistor and a capacitor shared by a plurality of memory cells, wherein the memory transistor has a drain, a source, a control gate and a charge storage unit, and the control gate is a word. A semiconductor non-volatile memory device connected to a line, one of a drain and a source connected to a bit line, and the other of the drain and the source connected to the capacitor. 2. The semiconductor non-volatile memory device according to claim 1, wherein the charge storage unit is a floating gate provided between a control gate and a channel formation region between a drain and a source. 3. The memory transistor is a drain,
2. The semiconductor nonvolatile memory element according to claim 1, further comprising a laminated insulating film between the channel forming region between the sources and the control gate, wherein an interface of the laminated insulating film serves as a charge storage portion. 4. The semiconductor non-volatile memory device according to claim 3, wherein the laminated insulating film is a laminated film of an oxide film and a nitride film. 5. A memory cell comprises one memory transistor and a capacitor shared by a plurality of memory cells, the memory transistor having a drain, a source, a control gate and a charge storage section, the control gate being a word line. A method of using a semiconductor non-volatile memory device, wherein one of a drain and a source is connected to a bit line and the other one of the drain and the source is connected to a capacitor. A method of using a semiconductor non-volatile memory device, which comprises writing data by injecting electrons using Fowler-Nordheim tunneling. 6. The memory cell comprises one memory transistor and a capacitor shared by a plurality of memory cells, the memory transistor having a drain, a source, a control gate and a charge storage section, the control gate being a word line. A method of using a semiconductor non-volatile memory device, wherein one of a drain and a source is connected to a bit line and the other one of a drain and a source is connected to a capacitor. A method of using a semiconductor non-volatile memory device, which comprises reading data by detecting. 7. When reading data, first, the capacitors of all erased memory cells of the semiconductor non-volatile memory device are charged to a predetermined potential, and then the word line is selected to change the charge between the capacitor and the bit line. 7. The method of using a semiconductor non-volatile memory device according to claim 6, wherein data is read by detecting movement. 8. The method of using a semiconductor non-volatile memory device according to claim 6, wherein the operation of charging the capacitors of all the erased memory cells of the semiconductor non-volatile memory device at a predetermined potential is performed at regular intervals. 9. A memory transistor array, wherein the memory cell comprises a plurality of memory transistors connected in series capable of individually retaining data, and one selection transistor.
A capacitor shared by a plurality of memory cells, the memory transistor has a drain, a source, a control gate, and a charge storage unit, the control gate is connected to a word line, and the selection transistor is connected to the memory transistor column. A semiconductor nonvolatile memory device, wherein the capacitor is connected between one end and a bit line, and the capacitor is connected to the other end of the memory transistor array. 10. The semiconductor non-volatile memory device according to claim 9, wherein the charge storage portion is a floating gate provided between a control gate and a channel formation region between a drain and a source. 11. The memory transistor has a laminated insulating film between a control gate and a channel forming region between a drain and a source, and an interface of the laminated insulating film serves as a charge storage portion. Item 9. A semiconductor nonvolatile memory device according to item 9. 12. The semiconductor nonvolatile memory device according to claim 11, wherein the laminated insulating film is a laminated film of an oxide film and a nitride film. 13. A memory cell is provided with a memory transistor array including a plurality of memory transistors connected in series capable of individually retaining data, one selection transistor, and a capacitor shared by the plurality of memory cells. The memory transistor has a drain, a source, a control gate, and a charge storage unit, the control gate is connected to the word line, the selection transistor is interposed between one end of the memory transistor string and the bit line, and the capacitor is the memory. A method of using a semiconductor non-volatile memory device connected to the other end of a transistor row, in which electrons are injected from a bit line to a charge storage portion of a memory transistor by using Fowler-Nordheim tunneling to write data. A method of using a semiconductor non-volatile memory device, comprising: 14. A memory cell comprises a memory transistor array composed of a plurality of memory transistors connected in series capable of individually retaining data, one selection transistor, and a capacitor shared by the plurality of memory cells. The memory transistor has a drain, a source, a control gate, and a charge storage unit, the control gate is connected to the word line, the selection transistor is interposed between one end of the memory transistor string and the bit line, and the capacitor is the memory. A method of using a semiconductor non-volatile memory element connected to the other end of a transistor row, wherein data is read by detecting movement of charges between a capacitor and a bit line. How to use the device. 15. When reading data, first, the capacitors of all erased memory cells of the semiconductor non-volatile memory device are charged to a predetermined potential, and then the word line is selected to change the charge between the capacitor and the bit line. The data reading is performed by detecting the movement.
4. The method for using the semiconductor non-volatile memory device according to 4. 16. The method for using a semiconductor non-volatile memory device according to claim 14, wherein the operation of charging the capacitors of all the erased memory cells of the semiconductor non-volatile memory device at a predetermined potential is performed at regular intervals.