JP3095918B2 - Non-volatile semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable nonvolatile semiconductor memory, and more particularly to a nonvolatile semiconductor memory capable of selectively writing three or more values of data to each memory cell.

[0002]

2. Description of the Related Art A nonvolatile memory called an EEPROM capable of electrically writing and erasing data is known. In particular, there is an EEPROM called Flash EEPROM which can erase data at once. This FlashE
In each memory cell of the EPROM, a channel region is provided between a source electrode and a drain electrode facing each other on the substrate,
There is a device using a MOS transistor in which a tunnel insulating film, a floating gate electrode, and a control gate electrode are provided in this order via an interlayer insulating film on the channel region.

In order to write data into such a memory cell, charge is injected into the floating gate through a tunnel insulating film to set the threshold voltage of the cell high (for example, data "1"), or vice versa. The threshold voltage of the cell is set low by extracting charges from the gate electrode (data "0"). Then, in order to read out the stored data, a voltage lower than the high threshold voltage and higher than the low threshold voltage may be applied to the control gate electrode for sensing.

As described above, in the conventional EEPROM, since only data "0" or data "1" can be selectively stored in one memory cell, the storage capacity is small. In response to the increasing trend of data in recent years, development of an EEPROM having a large storage capacity with a small number of memory cells has been desired.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and has as its main object to handle a large amount of data with a small number of memory cells. An object of the present invention is to provide a nonvolatile semiconductor memory capable of storing.

[0006]

According to the present invention, there is provided a drain electrode, a source electrode, a channel region disposed between the electrodes in a substrate, and a channel region provided on the channel region. a tunnel insulating film, a floating gate electrode provided on the tunnel insulating film, a MOS transistor and a control gate electrode provided via an interlayer insulating film on the floating gate electrode is used as a memory cell, multi A non-volatile semiconductor memory capable of writing value digital data , wherein a high voltage is applied to the control gate electrode of the MOS transistor, and
While floating the electrode, prior to said drain electrode
Apply three or more types of voltage according to multi-valued digital data
By doing so, the threshold voltage of the memory cell is set in advance.
The present invention is achieved by providing a nonvolatile semiconductor memory having means for selectively setting three or more levels .

[0007]

As described above, by applying the threshold voltage of the memory cell to one of the levels corresponding to the input data to the drain electrode, the amount of charge injected from the channel region to the floating gate is changed. As a result, the data stored in each memory cell can be read by sequentially applying a voltage slightly lower than each threshold voltage to the control gate at the time of data reading.

[0008]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a preferred embodiment of the present invention.

FIG. 1 shows a FlashE to which the present invention is applied.
FIG. 2 is an enlarged circuit diagram showing a main part of the EPROM. A word line W1 has a memory cell M composed of a MOS transistor.
1, connected to the control gate electrode of M2 and the word line W
2 is a memory cell M also composed of MOS transistors.
3. The control gate electrode of M4 is connected. The drain electrodes of the memory cells M1 and M3 are connected to the bit line B1, and the drain electrodes of the memory cells M2 and M4 are connected to the bit line B2.
It is connected to the. Further, the source electrodes of the memory cells M1, M3 are connected to the source line S1, and the memory cells M2, M4
Are connected to the source line S2.

Here, the structure of the MOS transistor of each of the memory cells M1 to M4 will be briefly described. As shown in FIG. 2, a drain region 2 and a source region 3 are located inside a substrate 1 at positions separated from each other. And a channel region 4 is provided therebetween. A drain electrode 5 is provided on the surface of the drain region 2, and a source electrode 6 is provided on the surface of the source region 3. On the surface of the channel region 4, a tunnel insulating film 8 made of silicon dioxide, a floating gate electrode 9, an interlayer insulating film 10, and a control gate electrode 11 are laminated in this order.

A procedure for writing data in each of the memory cells M1 to M4 of the flash EEPROM will be described below. Here, each of the memory cells M1 to M4 corresponds to these four types of data so that four types of data "00" to "11" in binary notation can be written / read. The threshold voltage levels are 2V, 3V,
It can take four states of 4V and 5V.

For example, the data "11" is stored in the memory cell M1.
Is written, a high voltage of about 12 to 15 V is applied to the word line W1, and no voltage is applied to the other word lines. Then, the bit line B1 is grounded, and the other bit lines are set to 3V. At this time, the source lines S1 and S2 are opened to be in a floating state. As a result, a voltage of 12 to 15 V is applied to the control gate electrode of the memory cell M1, and the voltage of the drain electrode becomes 0 volt.
Then, the source electrode is in a floating state. Also, an amount of charge corresponding to the potential difference between the control gate electrode and the drain electrode is injected into the floating gate, and the threshold voltage of the memory cell M1 is set to 5V.

Next, the data "1" is similarly stored in the memory cell M1.
When writing "0", the word line W1 and the source line S1 are in the same state as described above, and a pulse voltage of 1 V is applied to the bit line B1, that is, the drain. As a result, the threshold voltage of the memory cell M1 is set to 4V. Similarly, the threshold voltage is set to 3 V by setting the drain voltage to 2 V (data “01”), and the threshold voltage is set to 2 V by setting the drain voltage to 3 V (data “0”).
0 "). FIG. 3 shows the relationship between the drain voltage and the threshold voltage of the memory cell in the present embodiment. As can be seen from this figure, in this embodiment, the threshold voltage of the memory cell is set to 2V, 3V, 4V, 5V in accordance with the voltage level of the drain voltage.
The four states of “00” to “11” can be stored by associating data with each threshold voltage. Similarly, four types of data can be stored in each of the memory cells M2 to M4.

When the data written as described above is read, for example, 5 V is applied to the word line W1 and the drain current of each reference cell whose threshold voltage is set in advance is compared with that of the reference cell. It suffices to sense which of the data "00" to "11" is stored in the memory cells M1 to M2.

In the above embodiment, the threshold voltage of each memory cell is set to four values between 2 V and 5 V.
Needless to say, if the data is further subdivided, more data can be stored. In the above embodiment, the threshold voltage of each memory cell was changed by changing the drain voltage, that is, the pulse height. However, by changing the total voltage application time, that is, the pulse width, each memory cell was changed. It goes without saying that the threshold voltage of the cell can be easily changed. Further, the relationship between the gate voltage and the drain voltage and the threshold voltage of each memory cell in the present embodiment is arbitrarily changed depending on the structure of the memory cell, the thickness of the tunnel insulating film, the thickness of the interlayer insulating film, and the like. Things.

FIG. 4 is an explanatory circuit diagram of an EEPROM showing a second embodiment to which the present invention is applied. In this embodiment, cut-off MOS transistors Q1 to Qn are provided for each of the n source lines S1 to Sn.
The memory cells M11 to M to which data is to be written
By cutting off the MOS transistor of the source line connected to the mn source electrode by the control lines D1 to Dn, the source electrode of each memory cell is brought into a floating state. Other structures are the same as those of the first embodiment.

[0017]

As is apparent from the above description, according to the nonvolatile semiconductor memory of the present invention, a high voltage is applied to the control gate electrode, and three or more types of voltages corresponding to the input multi-valued digital data are obtained. By applying the voltage, the threshold voltage of each memory cell can be easily selectively set to three or more levels.
Thus, digital data exceeding one bit can be easily stored in one cell . Therefore, the storage capacity of the semiconductor memory is remarkably improved with the same number of memory cells as the conventional one, so that the effect is great. Further, by using the Farrer-Nordheim tunneling method for writing, the amount of charge injected into the floating gate can be easily controlled as compared with the case of using the hot electron method.

[Brief description of the drawings]

FIG. 1 shows an EEP showing a first embodiment to which the present invention is applied.
FIG. 2 is a circuit diagram of a main part configuration of a ROM.

FIG. 2 is a schematic sectional view showing a structure of a MOS transistor forming the memory cell of FIG. 1;

3 is a graph showing a relationship between a voltage applied to a drain electrode when writing data to each memory cell in FIG. 1 and a threshold voltage of each memory cell;

FIG. 4 is a main part configuration circuit diagram similar to FIG. 1, showing a second embodiment to which the present invention is applied.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Drain region 3 Source region 4 Channel region 5 Drain electrode 6 Source electrode 8 Tunnel insulating film 9 Floating gate electrode 10 Interlayer insulating film 11 Control gate electrode W1-Wn Word line B1-Bn Bit line S1-Sn Source line M1- M4 memory cell Q1-Qn cut-off MOS transistor M11-Mmn memory cell D1-Dn control line

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Shoichi Iwasa 5-10-1 Fuchinobe, Sagamihara-shi Nippon Steel Corporation Electronics Research Laboratory (72) Inventor Yasuo Sato 5-10-1 Fuchinobe, Sagamihara-shi Nippon Steel Corporation (56) References JP-A-3-88199 (JP, A) JP-A-58-86777 (JP, A) JP-A-47-12256 (JP, A) JP-A-4-25182 ( JP, A) JP-A-63-119097 (JP, A) JP-A-59-3975 (JP, A) JP-A-5-275659 (JP, A) JP-A-2-264381 (JP, A) JP-A JP-A-2-194562 (JP, A) JP-A-2-96369 (JP, A) JP-A-2-40198 (JP, A) JP-A-63-283072 (JP, A) JP-A-63-276791 (JP , A) JP-A-58-86778 (JP, A) Open Akira 58-85565 (JP, A) JP Akira 62-298999 (JP, A) (58 ) investigated the field (Int.Cl. ^7, DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (3)

(57) [Claims] 1. A drain electrode, a source electrode, a channel region disposed between the electrodes in a substrate, a tunnel insulating film provided on the channel region, and provided on the tunnel insulating film. A nonvolatile semiconductor memory in which multi-level digital data can be written using a MOS transistor having a floating gate electrode and a control gate electrode provided on the floating gate electrode via an interlayer insulating film as a memory cell. The multi-level digital signal is applied to the drain electrode in a state where a high voltage is applied to the control gate electrode of the MOS transistor.
According to Le data 3 or more types of voltages selectively applied to <br/> preset three or more threshold voltages of the memory cells
A nonvolatile semiconductor memory having means for selectively setting a level . 2. The semiconductor device according to claim 2, wherein said threshold voltage setting means includes :
Applying a high voltage to the control gate electrode of the transistor,
And while floating the source electrode, the
It comprises means for selectively setting the three or more levels of the threshold voltage set in advance in the memory cell application time or the voltage level is changed in voltage applied to the drain electrode in accordance with the multi-valued digital data The nonvolatile semiconductor memory according to claim 1, wherein: 3. The method according to claim 2, wherein the voltage applied to the drain electrode comprises a pulse voltage, and
High voltage is applied to the control gate electrode of the S transistor
And, with the source electrode floating,
Selectively set to three or more levels of the threshold voltage set in advance of the pulse voltage pulse height or the memory cell by changing the pulse width in response to the multi-valued digital data
2. The non-volatile semiconductor memory according to claim 1, further comprising means for setting.