JPH11163173A - Nonvolatile semiconductor storage device, method of readout thereof, and method of writing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To read out threshold voltage of a gate of a selected memory transistor with high accuracy, without being affected by effects of diffused layers and effects of variations in resistance of other transistor. SOLUTION: A plurality of memory transistors (M11 and the like), which respectively have a source region and a drain region, are arranged on semiconductor element formation regions (p-type wells W1 and W2) in the form of matrix, and a memory array 1 is constituted. Moreover, the element formation regions are separated into the W1 and the W2 in such a way that a potential can be set in the individual element formation regions in at least the row direction. At the time of a readout, a bias voltage (from CBL to 3 V) is applied to the other regions of the source and drain regions in a state that either of the source and the drain regions are short-circuited with the element formation region W1 formed with a selected memory transistor M13, while when a prescribed voltage is applied to (a BL1) via a resistance element (built in a readout control circuit), the voltage value on a short-circuit node is read (by an A/D converter 4). A prescribed current may be made to flow through the element formation regions by a built-in current source provided to the sides of the regions on one side of the source and drain regions or the sides of the other regions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device having an EEPROM, a mask ROM, an MFSFET, or the like as a memory transistor, and a reading method and a writing method thereof.

[0002]

2. Description of the Related Art For example, in a non-volatile memory of FG (Floating Gate) type, data reading is performed by detecting a current flowing through a bit line in accordance with memory data of a selected cell by a so-called current sense type sense amplifier. After voltage conversion and amplification are performed by the sense amplifier, the magnitude of the detected voltage is compared by a comparator, and the comparison result is read to a data line.

On the other hand, in order to realize a large-capacity nonvolatile memory, a memory transistor constituting each memory cell is made multi-valued, and a plurality of bits are stored in a single transistor to substantially increase the storage capacity at the same degree of integration. Multi-valued memory technology is currently being actively studied. The data read operation in the multi-valued memory needs to be repeated while changing the potential of the selected word line or the like by the number of multi-valued data, but the sense method converts the current flowing through the bit line into a voltage, For example, the cell data "0" and "1" are determined as compared with the reference cell, and are basically of a current sensing type. FIG. 17 shows a basic circuit of a general reading method using a current sense amplifier.

On the other hand, in the write operation, by increasing the difference between the bit line potential of the selected column and the word line potential of the selected row (for example, to about 20 V), the high potential difference is applied only to the selected memory transistor. The floating gate is applied to the buried insulating film, whereby charge injection or extraction is performed on the floating gate. At this time, since the unselected memory transistors arranged in the unselected columns and connected to the selected word line are susceptible to disturbance, it is necessary to effectively prevent this.

[0005] As a measure for preventing the write disturbance, generally, the voltage applied to the gate insulating film of the memory transistor in the non-selected column which is susceptible to the disturbance is sufficiently relaxed (for example, halved) as compared with the write operation. In addition, an intermediate voltage (for example, about 10 V) is set to the bit lines in the non-selected columns. In particular, in a NAND-type nonvolatile memory, a voltage of about the power supply voltage (for example, 3.3 V) is applied to unselected bit lines, so that the need for generating an intermediate potential is eliminated. After the channel of the selected NAND string is disconnected from the bit line, a technique of automatically boosting the voltage by capacitive coupling with a word line is used.

[0006]

However, the conventional reading method and writing method have the following problems, respectively.

First, as a problem with the conventional reading method, since the conventional method reads a low-level current value using a current sensing type amplifier, it is difficult to accurately obtain the resolution of the current value, particularly when multi-leveling is performed. There is such a difficulty. That is, the detection current I that differs between cell data
Although d can be approximately expressed by the following equation, even if the gate threshold voltage Vth is different, the detected current value changes only by a factor times the coefficient. The difference in the detected current value is, for example, about 10 μA to 50 μA in the case of a NOR type cell, and the integration and multi-levels have been increasingly advanced, and the difference in the amount of accumulated charge between adjacent data in the Vth distribution tends to be reduced. Considering that, this current value difference cannot be said to be sufficient.

[0008]

Id ≒ (Wg / Lg _eff ) μ Cox [(Vgs−Vth) Vds−0.5 Vds ² ] (1) where Wg is the gate width, Lg _eff is the effective gate length, μ
Is the average surface mobility, Cox is the gate capacitance per unit area, Vgs is the source-gate voltage (gate applied voltage),
Vds is a source-drain voltage (drain applied voltage).

The resolution of the current value (cell current value) of a memory cell in a multi-valued memory is determined by comparison with a reference cell current. To increase this resolution, besides increasing the current value, increasing the cell current value It is necessary to increase the resolution of the sense amplifier itself for reading the data. Normally, in a current sense type sense amplifier, a minute potential change after voltage conversion of a cell current is amplified and read out at least by the capacitance ratio of the bit line to the sense amplifier side (normally, about 10 times).
This is mainly due to the large bit line capacity accompanying the increase in the size of the memory array, and it is difficult to sufficiently obtain a small potential change before amplification because of the balance with the reading speed. For example, when the bit line capacitance is 10 pF and the cell current value ΔI = 5 μA is 10
When reading at 0 nsec, the charge amount displacement of the bit line is Δ
Q, assuming that the voltage amplitude (the amount of minute potential change) is ΔV, ΔQ
= CΔV, the following equation holds.

[0010]

## EQU2 ## 5 μA × 100 nsec = 10 pF × ΔV (2)

Therefore, the small potential change Δ
Since V is only 0.05 V, which does not provide a sufficient sense amplifier input, there is a certain limit in improving the resolution of the sense amplifier.

On the other hand, in the NAND type nonvolatile memory, data is read out through a non-selected cell connected in series to the selected cell. If the gate threshold voltage differs depending on the program state of the non-selected cell, the bias is set. In some cases, the on-resistance of non-selected cells varies to some extent, and this may cause a decrease in readout accuracy. In the NAND type memory, generally, programming is performed in order from a cell close to the common source line side, and reading is performed from the bit line side. For this reason, the non-selected transistor on the bit line side that functions as a pass transistor at the time of reading is always programmed after the selected transistor. Therefore, if there is a change in the resistance value due to the programming of the non-selected transistor on the bit line side, it is not known how much the value is at the time of programming the selected cell. Therefore, even if the selected cell is correctly programmed for each bit while reading it out, that is, even if it is correctly programmed while repeating the bit-by-bit verification (verification), an expected read current value cannot be obtained when reading data later. The reading accuracy of the selected cell is reduced by this current difference.

In a nonvolatile memory such as an AND type,
If the diffusion resistance of the sub-bit line or the source line changes for some reason, the current value at the time of data reading will fluctuate. This change in resistance value is caused by the NAND type or NO
This is a problem common to the R type. However, particularly in the AND type or the like, the sub-bit line and the common source line are formed by impurity diffusion layers, and the impurity diffusion layers are formed prior to LOCOS. Such a buried diffusion layer buried under the LOCOS inherently has a process variation factor such that its resistivity changes during LOCOS oxidation.
Also, in a cell system having a relatively large number of diffusion layers in a read current path, such as an AND type or a NAND type, a fluctuation in resistance value due to a change with time of the diffusion layer becomes a disturbance and read accuracy is reduced as compared with a NOR type. Cheap. The variation in resistance caused by the above-described program state or aging (including process variation) is caused by writing or reading Vth distribution data whose distribution range has been narrowed by multi-leveling in a NAND-type or AND-type nonvolatile memory. NO
This is more difficult than the R type, and as a result, a non-volatile memory such as a NAND type can multivalue only a smaller number of bits than the NOR type.

Next, as a problem of the conventional writing method, in setting the write-protection voltage of the non-selected column, there is a problem of the withstand voltage of the pn junction between the source / drain impurity region of the memory transistor and the well. That is, as the size of the memory transistor is reduced (scaling), the concentration of the channel formation region is particularly increased, so that the breakdown voltage of the pn junction between the source / drain region and the well tends to decrease. Therefore, in the future, if the scaling further advances, the inhibit voltage applied to the channel of the non-selected cell via the bit line must be reduced,
As a result, the prohibition of the writing of the unselected column becomes insufficient, and a problem may occur that the unselected memory transistor connected to the selected word line is erroneously written.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has a high precision by setting the gate threshold voltage of a memory transistor of a selected cell to a high detection voltage and eliminating the influence of resistance fluctuation of diffusion layers and other transistors as much as possible. It is an object of the present invention to propose a data reading method capable of reading data to a non-volatile semiconductor memory device suitable for the reading method. Further, according to the present invention, even when the withstand voltage between the source / drain region and the channel and the well is low in the memory transistor of the non-selected column at the time of data writing, the pn junction by the source / drain impurity region and the channel and the well is broken. Another object of the present invention is to provide a writing method for a nonvolatile semiconductor memory device in which a write-protection voltage is set without being down.

[0016]

In order to solve the above-mentioned problems of the prior art and to achieve the above object, in a semiconductor memory device of the present invention, an element formation region formed on a main surface side of a semiconductor substrate is provided. A memory array is formed by arranging a plurality of memory transistors in which a source impurity region and a drain impurity region are formed and a gate electrode is stacked on at least a gate electrode via an insulating film on a channel forming region sandwiched between the impurity regions Is a method of reading a semiconductor memory device, wherein at the time of reading, one of the source impurity region and the drain impurity region and the element formation region where the selected memory transistor is formed (for example, at least A plurality of unit element formation regions which are separated in the row direction and whose potential can be individually set, and short-circuited with the other impurity region. The bias voltage is applied, upon application of a predetermined voltage through the resistive element to the one of the impurity regions, it reads the voltage value to emerge to a connection node between the said resistor element and the one of the impurity regions. Instead of applying the predetermined voltage, a predetermined current may be supplied between the impurity regions by a current source provided on the one impurity region or the other impurity region. In this case, the resistance element is not always necessary.

In the former reading method in which a predetermined voltage is applied, the source or drain is short-circuited to the element formation region, and when a predetermined voltage is applied to the short-circuited node via a resistance element, the channel of the memory transistor is caused by the substrate bias effect. Is automatically controlled to a pinch-off state. For example, in an n-channel enhancement type memory transistor, when a predetermined negative voltage is applied to a source impurity region and an element formation region via a resistance element, a voltage is applied between the source and the drain, and the gate threshold voltage is set to a substrate bias voltage. The channel current starts to flow because it is reduced by the effect. However, when the channel current increases, the voltage drop in the resistance element also increases, so that the source potential becomes larger than the negative applied voltage. Therefore, the applied voltage between the source and the drain becomes smaller, and the voltage applied to the substrate side becomes smaller. , The gate threshold voltage increases. As a result,
The increase in the amount of voltage drop in the resistance element acts in the direction of turning off the transistor, and the final source potential takes a constant voltage near the critical state of whether or not a channel is formed. The self-stabilizing source potential takes different values depending on the easiness of channel formation, as is apparent from the above measurement principle. Therefore, the gate threshold voltage can be read out by measuring the source potential, and it is possible to determine the presence / absence of data storage (storage level in the case of multiple values). In this read method, instead of reading a current flowing through a non-selection transistor or a diffusion layer as in the related art, for example, a voltage is applied to a node on a side opposite to a memory array of a resistance element connected outside the memory array. Since the voltage of the memory array side node of the resistance element which appears through the unselected transistor and the diffusion layer is read, there is no influence from the ON resistance of the non-selected transistor and the resistance fluctuation due to the diffusion layer. In the latter readout method in which a predetermined current is passed, the measurement principle is substantially the same as that described above, that is, by setting the predetermined current by the current source to, for example, a minute current value when a gate threshold voltage is defined, the element formation region is connected. Since the source or drain potential is self-stabilized, measuring this potential makes it possible to read out the gate threshold voltage without being affected by the on-resistance of non-selected transistors or resistance fluctuation due to the diffusion layer. .

These reading methods can be applied to various semiconductor memory devices as long as they store data by changing the gate threshold voltage. As a nonvolatile semiconductor memory device in which the present method can be suitably performed, for example, an EEPROM
(Electrically Erasable and Programmable ROM), Mask ROM, MFSFET (Metal-Ferroelectric-Semicon)
ductor FET). Although there is no limitation on the cell system, the present invention is particularly suitable for a NAND nonvolatile memory. In a NAND type nonvolatile memory, a plurality of memory transistors, for example, 8 to 16 memory transistors are connected in series via a selection transistor between a bit line and a common source line. This is performed with the selection transistor turned on. For this reason, if the on-resistance differs according to the program state of each non-selected transistor, the resistance value of the read path from the selected transistor to the bit line often changes each time reading is performed. In principle, the reading method of the present invention is not affected by the resistance value fluctuation of the reading path, so that high-precision reading is possible.

The reading method of the present invention is particularly suitable for a multi-valued memory. This is because, in a multi-valued memory, the distribution width of the gate threshold voltage corresponding to one storage level is narrower than in a normal binary storage memory, and data reading with higher accuracy is required.

Further, the readout method of the present invention is suitable for a nonvolatile memory in which the charge storage means is discretized at least in a plane facing the channel formation region. As such a nonvolatile memory, for example, MNOS (Metal-N
itride-Oxide Semiconductor) type, MONOS (Metal-Oxide Semiconductor)
(xide-Nitride-Oxide Semiconductor) type, nano-crystal type in which the charge storage means is composed of a small-diameter conductor having a particle size of nano-order, and finely divided FG type in which the floating gate is finely divided into nano-orders. In the readout method of the present invention, a voltage is applied only between the gate electrode and the channel formation region, which is about the gate threshold voltage. Therefore, it is not necessary to apply a high voltage to the gate electrode. Unselected memory transistors are less susceptible to read disturb. This effect is similar to the normal F
The same applies to the G type, but in the case where the charge storage means of the MNOS type or the like is discrete, the gate insulating film is thinned and is susceptible to disturbance. According to the present invention, erroneous writing / erroneous erasure due to disturb at the time of reading of the memory can be particularly effectively prevented.

The nonvolatile semiconductor memory device according to the present invention
A read control circuit is connected to the memory array as a means for controlling the bias voltage (or current) and reading the voltage during the above-described read. Preferably, a unit element forming region which transitions from a non-conducting state to a conducting state in accordance with an input control signal and in which either one of the source impurity region and the drain impurity region and the selected memory transistor are formed And a transistor for short-circuit control that causes a transition from a disconnected state to a connected state is provided for each of the unit element formation regions. Further, in order to achieve a sufficient insulation separation for the unit element formation regions that are separated from each other, it is preferable that the distance between the plurality of unit element formation regions is in the depth direction of the semiconductor substrate relative to the adjacent unit element formation regions. It is preferable to provide an element isolation region that reaches deep into the substrate.

In the writing method of the nonvolatile semiconductor memory device according to the present invention, for example, (VSG1)
After setting a predetermined voltage equal to or higher than -Vth), a voltage having the same polarity as the predetermined voltage is applied to the unit element formation region of the non-selected column. As a writing method of the NAND type nonvolatile semiconductor memory device, preferably, the selection transistor on the common line side of the non-selected transistor column is turned off, the selection transistor on the bit line side is turned on, and the gate electrode is turned on in the row direction. After applying a high voltage (pass voltage) to a plurality of word lines commonly connected to each other to boost the channel potential of the transistor column, and before applying a predetermined program voltage to the word line of the selected row, A voltage is applied to the formation region. Further, before applying the predetermined voltage, a voltage may be applied to the unit element formation region. Further, when information is sequentially written to the memory transistor in at least three storage states, the voltage application to the unit element formation region of the selected column may be performed by changing the voltage value for each storage state write.

In this writing method, since a voltage having the same polarity as the predetermined voltage for writing inhibition is applied to the unit element formation region of the non-selected column, the source impurity region or the drain impurity region for which the writing inhibition voltage is set, and The applied voltage difference between the formation channel (inversion layer) and the unit element formation region is reduced. For this reason, even if the breakdown voltage of the pn junction between the source / drain impurity region and the unit element formation region is small, it is difficult for the breakdown to occur. This means that the determination of the set value of the write inhibit voltage is less likely to be limited by the withstand voltage of the pn junction. In particular, in a multi-valued memory or the like, the write inhibit voltage can be controlled with a high degree of accuracy according to the degree of the multi-value by increasing the degree of freedom in setting the write inhibit voltage.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As described above, the type of the nonvolatile semiconductor memory device according to the present invention or in which the present invention is preferably implemented is limited to a cell type, a binary memory or a multi-level memory, and the like. However, if the data is stored by changing the gate threshold voltage, the various forms described above exist.

Hereinafter, embodiments of a nonvolatile semiconductor memory device according to the present invention and a reading method and a writing method thereof will be described in detail with reference to the drawings using a flash EEPROM (flash memory) as an example.

First Embodiment This embodiment relates to a NAND flash memory. FIG. 1 is a schematic configuration diagram showing a circuit configuration of a memory array of a NAND flash memory according to the present embodiment and peripheral circuits of a main part. 2 is a plan view showing a part of the memory array, FIG. 3 is a cross-sectional view taken along line AA of FIG. 2, FIG. 4 is a cross-sectional view taken along line BB of FIG. 5
FIG. 3 is a sectional view taken along the line CC of FIG. 2.

This NAND type flash memory is shown in FIG.
As shown in (1), there is a memory array 1, a control circuit 2 for reading, and an A / D converter 4. Control circuit 2 and A
The "read control circuit" of the present invention is constituted by the / D converter 4.

In FIGS. 1 to 5, ST11, ST1
2, ST21 and ST22 are selection transistors, M11 to M11.
M116 and M21 to M216 indicate memory transistors, SG1 and SG2 selection signal lines, BL1 and BL2 indicate bit lines, WL1 to WL16 indicate word lines, and CL indicates a common line. The NAND memory array 1 is configured by arranging a plurality of transistor rows in which two selection transistors and a predetermined number (for example, 16) of memory transistors are connected in series. That is, a selection transistor ST11 connected to the bit line BL1 and a selection transistor ST12 connected to the common line CL are provided between the bit line BL1 and the common line CL.
Between T11 and ST12, the memory transistors M11-M
116 are connected in series. Similarly, the bit line BL2
A select transistor ST21 connected to the bit line BL2 and a select transistor ST22 connected to the common line CL are provided between the select transistor ST21 and the common line CL.
To M216 are connected in series. Although FIG. 1 shows only two transistor columns adjacent to each other in the row direction, the transistor columns are repeatedly arranged in the memory array in a similar adjacent relationship. Note that the common line CL in this example is
It is a wiring provided in common between a plurality of transistor columns arranged in the row direction, and as described later, for example, functions as a common source line at the time of writing, while serving as a common bias line for supplying a predetermined drain read voltage at the time of reading. Function.

In the nonvolatile semiconductor memory device according to the present invention, the element formation regions are separated at least in the row direction. Here, the “element formation region” refers to a region where a memory transistor is formed, and includes a semiconductor substrate itself, a well formed on the front surface side in the substrate, an epitaxial growth layer formed on the substrate surface, or SOI (Silicon). O
nInsulator) type semiconductor layer with insulation separation structure
There are various forms in the element formation region. In the present invention, the individual element forming regions separated in the row direction are referred to as “unit element forming regions”. In the present embodiment, FIGS.
As shown in (1), an n-well 12 doped with an n-type impurity is formed on the surface side of a p-type semiconductor substrate 10, and a p-well doped with a p-type impurity is further formed on the surface side in the n-well 12. ing. This p-well corresponds to the “element formation region” in the present invention. The substrate of the n-well 12 is n
In the case of a mold, it can be omitted, but in this example, since the substrate is a p-type, it is necessary to secure electrical separation from the substrate.
In addition, since the peripheral circuit requires an n-type well to form a CMOS transistor, the n-well 12 that can be formed simultaneously with this is disposed as a separation layer from the substrate. The p-well has one side (common line side) in the column direction by a trench 14 as an element isolation region in the row direction so that a voltage can be individually applied between the transistor columns.
Are spatially and electrically separated into a p-well W1 and a p-well W2 on the pattern. The trench 14 is formed by burying an insulator in the groove of the semiconductor substrate. In this example, the trench 14 reaches at least deeper than the p wells W1 and W2 toward the substrate deep side, and completes the isolation between the adjacent p wells W1 and W2. It is assumed. Each of the p-wells W1, W2, etc. separated so that the potential can be individually set,
This corresponds to the “unit element formation region” in the present invention.

As shown in the plan view of FIG. 2, elongated trenches 14 are arranged in the column direction at predetermined intervals in the row direction.
An active region where a channel of a transistor row is formed is formed within the interval between the trenches. The selection transistors ST11 and ST2 intersect with each active region long in the column direction.
1, a select signal line SG1 also serving as a gate electrode (control gate), word lines WL1 to WL16 also serving as gate electrodes of memory transistors M11 to M116 and M21 to M216, and select transistors ST12 and S.
The selection signal line SG2 also serving as the gate electrode of T22 is arranged in the column direction. Select transistors ST11, ST
In the active region 21 on the side opposite to the memory transistor column, an upper bit line BL (not shown)
1 and bit contacts BC respectively connected to BL2
1 and BC2 are provided.

When this transistor row is viewed in a column direction sectional view (FIG. 3) along the line AA in FIG. 2, the p well W2
Source / drain regions 16 (n-type impurity regions) of the memory transistor are formed at predetermined intervals on the inner surface side. Each p in the interval between the source / drain regions 16
On the well region, control electrodes (control gates also serving as word lines) of the memory transistors M21 to M216 are stacked via an insulating film including at least charge storage means. In this example, the tunnel insulating film 13 and the floating gate F are sequentially formed on the p-well W2 (or W1).
G, an inter-gate insulating film 15, and a control gate (word line) are stacked. The tunnel insulating film 13, the floating gate FG, and the inter-gate insulating film 15 are, for example,
Each is composed of a thermal silicon oxide film, a polysilicon film doped with impurities, an ONO (Oxide-Nitride-Oxide) film, and the like. The bit line BL2 (or BL1) is wired via the interlayer insulating layer 18 on the transistor row having such a structure. Bit lines BL1 and BL2 are usually
And an impurity region 17 interconnecting a select transistor and a well select transistor, which will be described later, via a bit contact BC opened in the interlayer insulating layer 18.
(N-type impurity diffusion region). On the other hand, a common line CL connected to the impurity region of the select transistor ST22 is provided at the transistor column end opposite to the bit contact.
Is formed, for example, by processing a third-layer polysilicon film.

Here, the "charge storage means" is a charge formed in a stacked structure of gate electrodes on a well, exchanges charges with a substrate side in accordance with a voltage applied to the gate electrodes, and holds charges. Refers to a holding medium. In this example, the floating gate FG corresponds to the charge storage means.
Other than this example, for example, an ONO film or NO (Nitride
-Oxide) Carrier traps formed in a nitride film such as a film or near the interface between an oxide film and a nitride film, nanocrystals made of silicon, etc., having a particle size on the order of nanometers (nm), and made of conductive polysilicon, etc. The charge storage means such as a finely divided floating gate divided into various dots may be discretized in a plane. Moreover, although it is not common to realize the NAND type, in the MFSFET,
The ferroelectric thin film on the element formation region functions as charge storage means. In a mask ROM that cannot be rewritten,
Since there is no charge storage means, the memory transistor is depleted by ion implantation or the like, and data is programmed in advance.

In this embodiment, the p-well W1 or W2
Is electrically connected to the bit line of the corresponding NAND string /
A well selection transistor to be cut off is provided for each NAND string. This well selection transistor corresponds to the “short-circuit control transistor” in the present invention.
More specifically, as shown in FIG. 1, the well selection transistor SWT1 has a drain connected to the selection transistor ST1.
1 and the source is a well contact WC
1 is connected to the p-well W1. Similarly, the drain of the well selection transistor SWT2 is connected to the source of the selection transistor ST21, and the source is connected to the p-well W2 via the well contact WC2. These well select transistors SWT1, SWT
T2 is controlled by the well selection line SWL. As shown in FIG. 2, the well selection line SWL also serves as the gate electrodes of the well selection transistors SWT1 and SWT2 and is arranged in the row direction similarly to the word line. The well selection line SWL is controlled together with the selection signal lines SG1 and SG2 by, for example, a row decoder (not shown).

The well selection transistors SWT1, ST
WT2 and the select transistors ST11 to ST22
Are the layers that become the floating gates FG in the memory transistors and the various signal lines (the well selection lines SWL, SWL,
The selection signal lines SG1 and SG2) are stacked in direct contact, or a connection hole is provided in the inter-gate insulating film as shown in the sectional view of FIG. Have been. Also, the well contact WC
As shown in FIG. 4, the source impurity regions 19 (n-type impurity diffusion regions) of the well selection transistors SWT1 and SWT2 are used as unit element formation regions (p wells W1.
W2) is made of a conductive material, for example, a buried metal.

As shown in FIG. 1, each bit line BL1, B
L2 is drawn out of the memory array, and the control circuit 2
It is connected to the. In order to achieve the read method of the present invention, the control circuit 2 incorporates a predetermined voltage into one end of a channel of a transistor row and a unit element forming region (p-well W1 or W2 in this example) via a bit line. This is a circuit that is applied via a resistance element.

The A / D converter 4 is connected to each of the bit lines BL1 and BL2. The A / D converter 4 reads a voltage value appearing on the bit line BL1 or BL2 by applying a voltage by the control circuit 2, converts the voltage value into binary information, and outputs the binary information.

Next, an embodiment of a read method according to the present invention will be described by taking as an example a case where the present invention is applied to the NAND flash memory having the above configuration. This reading method reads data stored in a memory transistor by a source follower. Here, reading of the memory transistor M13 in FIG. 1 is taken as an example. FIGS. 6 and 7 are circuit diagrams showing the basic principle of the two reading methods according to the present example.
In FIG. 6, R indicates a resistance element built in the control circuit 2.

When reading the memory transistor M13, first, a bias voltage is set as shown in FIG. That is, the well selection line SWL and the selection signal line S
A high level voltage (for example, 5V) is applied to G1 and SG2.
Is applied, and the well selection transistor SWT1 and the selection transistors ST11 and ST12 are turned on. Also,
A low-level voltage (for example, 0
V) is applied, and the selection transistor M13 is turned off. Unselected word lines WL1, WL2 and WL4 to W
A high-level voltage (for example, 5 V) is applied to L16, and unselected memory transistors M11, M12 and M
14 to M116 are turned on. As a result, the memory transistor row including the select transistor is connected to the bit line BL.
1 and the channel of the memory transistor row and the p-well W1 are short-circuited.

In the read method shown in FIG. 6, when a predetermined voltage is applied by the control circuit 2 through the resistance element R after the bias setting, the channel of the memory transistor M13 is automatically controlled to a pinch-off state by the substrate bias effect. Is done. For example, in the case of an enhancement type in which the gate threshold voltage of an n-type channel memory transistor is positive, a negative trigger pulse having an amplitude Vin as a predetermined voltage is applied to the source and the p-well W1 through the resistance element R, and the source and the drain are discharged. During this time, a voltage is applied, and the gate threshold voltage Vth decreases due to the substrate bias effect, so that the drain current Id starts to flow. However, when the drain current Id increases, the voltage drop in the resistance element R also increases, so that a pulse having an amplitude Vs smaller than the pulse amplitude Vin input to the source appears at the connection node between the resistance element R and the memory transistor M13. The voltage between the source and the drain decreases, and the amplitude of the pulse voltage applied to the p-well W1 decreases, so that the gate threshold voltage Vth increases. As a result, the increase in the voltage drop in the resistance element R acts in a direction to turn off the memory transistor M13, and the amplitude Vs of the pulse appearing at the source finally determines whether or not a channel is formed in the memory transistor M13. It takes a constant value determined near the criticality. The pulse amplitude Vs of the self-stabilizing source takes a different value depending on the ease with which the channel of the memory transistor M13 is formed, as is apparent from the above measurement principle. Therefore, the gate threshold voltage Vth can be read by the A / D converter 4 to which the source potential is inputted,
The presence or absence of data storage from the D converter 4 (in the case of multi-value,
(Storage level) is output.

In this reading method, the current flowing through the non-selected memory transistors (M11 and M12 in this example) and the impurity diffusion layers is not read out as in the prior art, but is connected to the outside of the memory array 1. Since a voltage is applied to the node on the memory array side of the resistive element R and the voltage on the node on the memory array side of the resistive element R is read, there is almost no influence from the on-resistance of the unselected memory transistor and the resistance fluctuation due to the impurity diffusion layer. . This is because while the drain current Id is large, there is some resistance fluctuation, but almost no current flows near the self-stabilization of the source potential, so that the resistance fluctuation does not affect the source potential.

In the reading method shown in FIG. 7, after the same bias setting as in FIG. 6 is performed, a predetermined current I flows from the current source in the control circuit 2. The predetermined current I may be about the current value when the gate threshold voltage Vth of the memory transistor M13 is defined (for example, about 10 μA). Self-stabilization is performed as in the case of FIG.
Therefore, the self-stabilized source potential Vs is changed to A /
By reading with the D converter 4, the gate threshold voltage Vth can be read without being affected by the on-resistance of the non-selected memory transistors M11 and M12 and the resistance fluctuation due to the impurity diffusion layer.

The current source in FIG. 7 may be provided on the drain side of the memory transistor M13. Also, the value of the predetermined current I flowing from the current source is not limited to about 10 μA as described above, but is desirably set to a smaller current value.
For example, if the resistance value of an unselected cell in which the on-resistance of the unselected transistor is dominant is 10 kΩ, the total resistance value of the unselected cells is 150 kΩ because the number of unselected cells in the transistor row is 15, but in this case, The judgment current I is 1 nA
Then, the voltage variation due to the resistance value of all the unselected cells is Δ
Since V is extremely small, that is, ΔV = 150 kΩ × 1 nA = 0.15 mV, the influence of the resistance change due to the non-selected memory transistor can be extremely reduced.

The nonvolatile memory of this embodiment has a well selection transistor (short-circuit control transistor) for switching the connection between the memory transistor row and the p-well for each p-well, and applies a predetermined voltage to the short-circuit node. Alternatively, since it has a circuit (control circuit 2) for flowing a predetermined current through the memory transistor and means (A / D converter 4) for reading a voltage appearing at the short-circuit node, the gate threshold voltage Vth by the source follower is provided. Can be read.

In the method of reading the gate threshold voltage Vth by the source follower, the selected memory transistor is automatically controlled to a pinch-off state by the substrate bias effect, and the potential of the short-circuit node is determined stably. Therefore, the value of the current flowing through the impurity diffusion layer of the non-selected memory transistor or the like can be extremely small, and the influence of the resistance change of the impurity diffusion layer of the non-selected memory transistor or the like on the Vth read can be extremely reduced. Is significantly improved as compared with the prior art. Further, the potential difference between the channel formation region and the gate at the time of reading can be set to a small value at least such that the channel is inverted (about 2φF + φ). As a result, the read disturb can be effectively suppressed. Where φF is the Fermi potential,
φ is the work relationship difference with the gate. This read disturb suppression effect is, for example, MONOS type, MNOS
This is particularly effective in a non-volatile memory in which the charge storage means is discretized in a plane, such as a type, a nanocrystal type, or a finely divided FG type, and is likely to be disturbed.

Further, the p-well is separated so that a voltage can be individually applied to at least the row direction, that is, for each transistor column in the row direction. Therefore, the p-well is suitable for reading the gate threshold voltage Vth by the source follower. If the predetermined voltage is selectively applied by the control circuit 2, the p-well can be separated for each of the plurality of transistor rows.

The fact that the p-wells are separated at least in the row direction provides various advantages not only in data reading but also in writing or erasing. Less than,
An embodiment of the writing method according to the present invention, which is enabled by the setting of the bias voltage at the time of writing or erasing and the separation of wells, will be described in detail, taking the case of writing to the memory transistor M13 as an example.

FIG. 8 shows a bias voltage setting example 1 at the time of writing together with a bias voltage setting example at the time of erasing. Before writing, the selection signal lines SG1 and SG2, the well selection line SWL, all the word lines WL1 to WL16, and all the bit lines BL1 and BL
2, and the potentials of all the wells W1 and W2 are set to 0V.
For setting the well potential, a well voltage setting terminal may be separately provided, but here, the well potential is applied from the bit line by controlling connection / disconnection to the bit line. Therefore, in this initial state, the well selection line SWL is set to the high level, and the well potential is set to 0 V by connecting to the bit line (0 V).

First, an inhibit voltage Vinhibit (for example, 10 V) is applied to the unselected bit line BL2. Further, while turning on the select transistor ST11, ST21 by applying a power supply voltage V _CC (approximately 1V～3V) to the selection signal line SG1, turns off the select transistor ST12, ST22 and the voltage applied to the selection signal line SG2 to 0V hand,
Each memory transistor column is connected to a common line CL (bias voltage:
10V). Further, 0 is added to the selection well W1.
V, the inhibit voltage Vinhibit is applied to the unselected well W2.
(For example, 10 V), and the non-selected word lines WL1, WL1,
A pass voltage Vpass (for example, 10 V) is applied to WL2 and WL4 to WL16. In this state, the selected word line W
When a high voltage Vpp (for example, 20 V) is applied to L3, a high voltage of 20 V is applied between the channel of the selected memory transistor and a gate electrode (for example, a control gate), and electrons are transferred from the channel side to charge storage means (for example, a floating gate). FG) and the program is performed. In addition, for the non-selected memory transistor M11 and the like in the same transistor row, 1
Since only about half the voltage of 0 V is applied, writing is not performed. On the other hand, for the unselected transistor row, since 10 V is applied to the unselected well W2, the inhibit voltage of the unselected transistor M21 and the like is set from the well side. In this example, 10 is also applied to the unselected bit line BL2.
Although V is applied, since the same voltage is applied to the well side, even when the withstand voltage between the source / drain region of the non-selection transistor M21 and the like and the well is low due to the scaling of the memory transistor, this voltage is applied. It is possible to set a sufficiently high inhibit voltage Vinhibit of 10 V without breaking down the pn junction.

Next, embodiments of the writing method according to the present invention will be described in the following bias voltage setting examples 2 and 3.

FIG. 9 is a timing chart of each voltage showing a write operation in this example. As in the bias voltage setting example 1, all voltages are set to 0 V before writing. From this initial state, first, a predetermined positive voltage is applied to the selection signal line SG1, the unselected bit line BL2, and the common line CL. Is applied. For example, the power supply voltage V _CC is applied to SG1, the inhibit voltage Vinhibit is applied to BL2, and the voltage equal to or higher than the inhibit Vininhibit is applied to the common line CL (here, V _CC ≦ Vinhibit).
Is applied. Thereby, the selection transistors ST11,
ST21 is turned on.

Next, all the word lines WL1 to WL16
To, applying a higher positive pass voltage Vpass (> V _CC). Thus, the potential of the channel capacitively coupled to the word line tends to increase. The selected column, the source select transistor ST11 channel potential Vch1 while is turned ON but hardly rises from 0V, the non-selected column (applied gate voltage V _CC of the select transistor ST21) the channel potential Vch2 is - (selection transistor ST21 When the voltage rises above the gate threshold voltage Vth), the select transistor ST21 is cut off. Thereafter, the channel of the non-selected column enters a floating state, and is automatically boosted (self-boosted) to a predetermined voltage V1 higher than the inhibit voltage Vinhibit. You. The final voltage V1 due to the capacitance coupling at this time
Is the value of the pass voltage Vpass and the control electrode (word line W
L1 to WL16), the floating gate FG, the floating gate FG and the channel, the floating gate FG and the source / drain region, the source / drain region and the well, or the coupling capacitance between the channel and the well.

Next, the bit line potential is applied to each well by setting the well selection line SWL to a high level. Since the bit line in the selected column is originally 0 V, there is no effect of this voltage application. However, in the non-selected column, the potential of the well W2 is changed from 0 V to a positive voltage (for example, the inhibit voltage Vinhi).
), the channel potential Vch2 is raised to a higher predetermined voltage V2.

Finally, the highest program voltage V _PP (for example, about 20 V) is applied to the selected word line WL3. Since the channel potential Vch1 of the selected column is almost 0 V, the application of the program voltage V _PP causes the memory transistor M1 connected to the word line WL3 in the selected column to be applied.
The electric field applied to the tunnel insulating film of No. 3 increases, whereby electrons are injected into the floating gate FG from the substrate side, the gate threshold voltage of the selected memory transistor M13 shifts in the positive direction, and information is written. At this time,
Other word lines WL1, WL2 and WL4 to W in the same selected column
Unselected memory transistors M11, M connected to L16
In Nos. 12, M14 to M116, since the voltage applied to the insulating film is about the multiplication of the pass voltage Vpass by the ratio of the above-described various coupling capacitances, electrons are not injected into the floating gate FG, and no writing is performed. On the other hand, in an unselected column, the channel potential Vch2 is applied by application of the program voltage V _PP.
Further rises to the final predetermined voltage V3,
Writing to the non-selected column, particularly to the non-selected memory transistor M23 connected to the selected word line WL3 is prohibited.
That is, depending on the voltage difference obtained by subtracting the predetermined voltage V3 from the program voltage V _PP , the non-selected memory transistor M
23, the values of the voltage V2 and the final voltage V3 in the preceding stage are predetermined so that no charge injection occurs and no charge injection occurs during the final channel boosting.

FIG. 10 is a timing chart of each voltage indicating a write operation in this example. In the bias voltage setting example 3, the channel boosting (voltage V1 ′) of the first-stage non-selected columns and the channel boosting (voltage V2 ′) of the second stage are performed in the reverse order of the bias voltage setting example 2. That is, for example, at the same time or before or after the setting of the voltage (inhibit voltage Vinhibit) of the non-selected bit line BL2, first, the well selection line SWL is set to the high level to turn on the well selection transistor SWT2 (and SWT1). At this time,
The selection transistor ST21 is off, and the voltage V is applied to the well W2 via the well selection transistor SWT2.
1 ′ is applied (V1 ′ ≦ Vinhibit). At this point, no channel is formed in the memory cell of the non-selected column, but in FIG. 10, the channel potential Vch2
At this time is V1 '. Next, after the selection signal line SG1 is set to the high level (for example, the power supply voltage V _CC ), the pass voltage V is applied to all the word lines WL1 to WL16.
A pass is applied, thereby performing the second stage channel boosting (voltage V2 ′). In the control of setting the selection signal line SG1 to the power supply voltage V _CC , the voltage V
Since 1 'is applied, the selection transistor ST21 in the non-selected column remains off while the selection transistor ST11 in the selected column is turned on, whereby the potential (0 V) of the bit line BL1 is applied to the channel of the selected column. Reportedly. Subsequent bias voltage control (application of program voltage V _PP ),
The basic principle of setting the program and the write inhibit voltage is the same as that of the bias voltage setting example 2 described above. Therefore, by applying the program voltage V _PP , as in the previous bias voltage setting example 2, electrons are injected into the charge storage means (floating gate FG) of the memory transistor M13 to write information, while other non-selected memories Writing to the transistor is prohibited.

In a multi-valued memory in which the write information has three or more values, multi-value storage can be performed by changing the program voltage V _PP of the selected word line stepwise or changing the selected bit line stepwise. In the above-described multi-value conversion in the bias voltage setting examples 1 to 3 at the time of writing, the basic write cycle is changed to the program voltage V of the selected word line WL3.
Repeat by changing the _PP or the selected bit line BL1 stepwise. For example, in the example of FIG. 9 and FIG.
(J) is taken as one write cycle, and the selected bit line potential in each figure (b) is not fixed to 0 V but is changed stepwise in a positive direction, for example, in each write cycle, or each figure (e)
The value of the program voltage V _PP is changed stepwise in each write cycle. The program voltage V
_In multi-value storage in which _PP is changed stepwise, the selected word line W
In order to effectively prevent erroneous writing of the non-selected memory transistor connected to L3, in some cases, the non-selected bit line BL2 or the pass voltage Vpass according to the program voltage V _PP.
It is necessary to change the set value of the write prohibition voltage step by step. This control is based on the bias voltage setting example 1 described above.
3, the voltage values of the basic write cycle, that is, FIG.
The example of FIG. 10 can be dealt with by appropriately changing the voltage applied to the unselected bit line in each diagram (c) or the pass voltage value in each diagram (f).

In the multi-value storage in which the potential of the selected bit line BL1 is changed, the program voltage V _PP applied to the selected word line WL3 is constant, and it is not necessary to change the unselected bit line voltage to prevent erroneous writing. Alternatively, there is an advantage that the control is easy because the selected bit line voltage originally lower than the word line potential is changed. For example, now, the potential of the selected bit line BL1 is set to 0V, Va (for example, 1V),
Vb (for example, 2 V), Vinhibit (V1 ≧ Vinhibit ≧
It is assumed that the gate threshold voltages Vth of the write cells after writing are 3 V, 2 V, 1 V, and -3 V when V _CC and 0 V <Va <Vb <Vinhibit are satisfied. At this time, the channel potentials become 0 V, 1 V, 2 V, and V 3 (or V 3 ′), respectively, and take a stepwise value from 0 V to the write inhibit potential V 3 (or V 3 ′) according to the bit line potential. On the other hand, the unselected bit line BL2 is always set to the write inhibit voltage V3 (or V3 '), thereby preventing erroneous write. In such multi-value storage, the voltage applied to the bit line may be relatively low, and the booster plate (B
Since there is no need to apply a high voltage to the BP unlike the multivalued storage using P), there is an advantage that the load on the peripheral circuits and the power consumption can be reduced. That is, in the booster plate method, it is necessary to apply a voltage not only to the bit line but also to the BP. Since the voltage is as high as about 12 V to 17 V, a circuit such as a decoder is constituted by high voltage transistors having a high withstand voltage. However, there is a disadvantage that the peripheral circuit area increases and power consumption increases. In contrast,
The multi-value storage in which the bit line potential is changed in multiple stages has advantages such as high integration, low cost and low power consumption without such disadvantages.

In the above-described writing method, in addition to the advantage over the above-mentioned booster plate method, it should be noted that the memory cells are electrically separated so that a voltage can be set for each element formation region (for example, a well) for each memory cell column. The potential difference between the channel of the non-selected transistor row and the element formation region can be reduced by utilizing this. Therefore, an element formation region,
The reverse bias voltage applied to the pn junction formed by the channel or the source / drain region of the transistor row and the well can be reduced as compared with the conventional case. For this reason, the voltage range (degree of freedom) for setting the write inhibit voltage (drain, source, and channel potentials of the non-selected columns), which was conventionally set only in a narrow range so as not to break down the pn junction, is set in this embodiment. Therefore, the write inhibit voltage can be set without worrying about the withstand voltage between the source / drain region or the channel and the well where the withstand voltage tends to decrease more and more as the element becomes finer. Also, this p
By reducing the reverse voltage of the n-junction and expanding the range of the write-inhibit voltage setting, a single memory transistor stores a plurality of bits and writes the multi-valued memory that requires the write-inhibit voltage setting in fine voltage steps. Accuracy and reliability are improved. Furthermore, since the write inhibit voltage is boosted by applying a voltage to the unit element formation region (well), the write inhibit voltage is increased to obtain the same write inhibit voltage as compared with the case where the write inhibit voltage is boosted only by applying the voltage to the word line. The pass voltage applied to the selected word line can be reduced. As a result, it is possible to effectively prevent write disturbance (erroneous writing or the like) of a non-selected transistor formed in the same unit element formation region as the selected memory transistor.

On the other hand, as shown in FIG. 8, the bias setting at the time of erasing is such that both the bit lines BL1 and BL2 are applied with 0V and the selected word line WL3 is applied with 0V.
For example, 20 V is applied to the selection well W1. At this time,
Since 0 V is applied to the non-selected well W2, the retained charges (electrons) of the selected memory transistor M13 are drawn out to the substrate side, and between the channel of the non-selected memory transistor M23 connected to the same word line WL3 and the gate electrode. Indicates that no voltage is applied and the unselected memory transistor M
23 is not erased. In other words, conventionally, erasing could be performed only in units of word lines, but in this example, by performing well separation so that a voltage can be individually set, random erasing can be selectively performed for each memory transistor.

Second Embodiment This embodiment relates to an AND type nonvolatile memory. FIG. 11 is a schematic configuration diagram showing a circuit configuration of a memory array of an AND flash memory according to the present embodiment and a peripheral circuit of a main part. FIG. 12 is a plan view showing a part of the memory array, and FIG. 13 is a cross-sectional view taken along line DD of FIG.

This AND type flash memory has a control circuit 2 and an A / D converter 4 as a read control circuit in addition to the memory array 20, as in the first embodiment.

The AND type memory array 20 of the present embodiment is the first type.
The difference from the NAND type memory array 1 of the embodiment is that the memory transistor M11 is provided between the select transistors ST11 and ST21 and the select transistors ST12 and ST22.
To M116 or M21 to M216 are connected in parallel. In the AND type memory array 20 of this example, as shown in FIG. 12, a wiring layer connecting the memory transistors in parallel and a source impurity diffusion layer 22 also serving as a channel layer of the selection transistor and a drain impurity diffusion layer 24 are arranged in the column direction. Are located. Other configurations, that is, well select transistors SWT1 and SWT2, select transistors ST11, ST21, ST12, and ST22, p wells W1 and W2 separated for each transistor column, well contacts WC1 and WC2, and bit contacts BC1 and
The position of BC2, the connection relationship between the bit lines BL1 and BL2, the connection relationship with the common line CL, and the like are the same as in the first embodiment.

The source impurity diffusion layer 22 and the drain impurity diffusion layer 24 are spaced apart from each other at the surface of the p-well W1 sandwiched between the trenches 14, as shown in cross section in FIG. A source region 26 and a drain region 28 of the memory transistor are formed. Other cross-sectional configurations, that is, the p-type semiconductor substrate 10,
The n-well 12, p-well W1, trench 14, interlayer insulating layer 18, and bit line BL1 are the same as in the first embodiment.

The configurations of the control circuit 2 and the A / D converter 4 connected to each of the bit lines BL1 and BL2 are the same as those of the first embodiment, and the read operation is basically the same. Therefore, the diagrams showing the measurement principle of FIGS. 6 and 7 are also applied to the present embodiment.

However, the value of the bias voltage is slightly different from that of the first embodiment. When reading the memory transistor M13, first, as shown in FIG.
A high-level voltage (for example, 5 V) is applied to the selection signal lines SG1 and SG2, a high-level voltage (for example, 3 V) is applied to the selected word line WL3, and a low-level voltage (for example, is applied to unselected word lines WL1, WL2 and WL4 to WL16). -5
V). Thereby, the well selection transistor SWT1 and the selection transistors ST11, ST1
2 and the selected memory transistor M13 are turned on, and the unselected memory transistor M11 and the like are turned off.

Thereafter, the gate threshold voltage Vth can be read out according to the same principle as in the first embodiment, and the same effect as in the first embodiment can be obtained. That is, instead of reading out the current flowing through the impurity diffusion layers 22 and 24 as in the conventional AND type, the source impurity diffusion layer 22 and the p well W
1 is short-circuited, a predetermined voltage Vin is applied to this short-circuit node, or a predetermined current I
, The voltage Vs appearing at the short-circuit node is read, and the drain current Id when the voltage Vs is self-stabilized is extremely small.
In FIG. 4, it is possible to substantially eliminate the fluctuation factors caused by the flow of a relatively large current as in the conventional case, and it is possible to perform highly accurate reading. In particular, in the case of the AND type in which element isolation is achieved by LOCOS, since the element isolation region (LOCOS) is formed by oxidation after the formation of the impurity diffusion layers 22 and 24, the impurity diffusion layer 22 is heated by this oxidation. , 24 deviate from the design value, and the conventional reading method has a problem that accurate reading cannot be performed due to the resistance value fluctuation. However, in the present reading method, there is such a resistance fluctuation. However, since the current value at the time of reading is extremely small, it is not affected by resistance fluctuation. In addition, even if the resistance changes with time due to some factor, this does not hinder high-precision reading.

Further, the p-well is separated so that a voltage can be individually applied to at least each of the parallel transistor groups in the row direction, for example, in the row direction. The first
As in the embodiment, if the predetermined voltage application by the control circuit 2 is selectively performed, the p-well can be separated for each of the plurality of transistor rows.

The fact that the p-wells are separated at least in the row direction provides the same advantages as in the first embodiment not only in data reading but also in writing or erasing. That is, in writing, even if the withstand voltage between the source / drain or the channel and the well is reduced due to the scaling of the memory transistor, it is directly applied to the unselected well.
Since an inhibit voltage can be applied, a high inhibit voltage is ensured. In the erasure, random erasure becomes possible. FIG. 14 exemplifies bias setting values at the time of writing and at the time of erasing, with respect to the AND flash memory of the present embodiment.

Third Embodiment The present embodiment relates to a NOR type nonvolatile memory. FIG. 15 and FIG. 16 are schematic configuration diagrams showing a circuit configuration of a memory array of the NOR flash memory according to the present embodiment and a peripheral circuit of a main part. In particular, of the NOR type, FIG. 15 shows a source-isolated NOR type in which writing is performed by FN tunneling implantation over the entire channel, and FIG. 16 shows a so-called Hi type in which a source line is shared between cells in a row direction.
Indicates CR type. In addition, the so-called virtual grounding type, in which the source line and the bit line are shared, is also applicable to the present invention.
The description here is omitted. Although not shown, even in the NOR type, a control circuit and an A / D
Having a converter is the same as in the first and second embodiments.

The difference between the source-separated NOR type memory array 30 of FIG. 15 and the AND-type memory array 20 of the second embodiment is that the transistors M11 to M1n and M21 to M2n (n is, for example, Hundreds to several hundreds), the bit line BL
1 and BL2 and a source line (in this case, common lines CL1 and CB).
L2) are wired in the column direction and are drawn out of the memory array. Accordingly, the common lines CL1 and CBL2 are formed of the same upper wiring layer (Al layer) as the bit lines BL1 and BL2, and the bit contact and the source contact are formed. Is for each memory cell (or commonly for cells adjacent in the column direction)
That is, the selection transistors are omitted, and the bit lines BL1 and BL2 and the common lines CL1 and CL2 are selected by a column decoder (not shown). Further FIG.
In the sixth HiCR memory array 40, the well and the common line are shared between the transistors adjacent in the row direction.
In this case, the shared common line is connected to the source side of each memory transistor, and in this case, the bit line BL
1 and BL2 are connected to the drain side of each memory transistor. In the HiCR type, since the well and the common line are shared between two columns adjacent in the row direction, the shared columns cannot be selected at the same time. Therefore, at the time of writing, erasing, or reading, the even-numbered columns and the odd-numbered columns are controlled separately. Other configurations, ie, well selection transistors SWT1 and SWT2, well contact W
C1, WC2, etc. are the same as in the second embodiment.

The configurations of the control circuit and the A / D converter connected to each of the bit lines BL1 and BL2 are the same as in the first embodiment, and the read operation by this is basically the same. Therefore, the diagrams showing the measurement principle of FIGS. 6 and 7 are also applied to the present embodiment.

However, the value of the bias voltage is slightly different from that of the first embodiment. When reading the memory transistor M13 in the source-isolated NOR type, first, as shown in FIG. 15, a high-level voltage (for example, 5 V) is applied to the well selection line SWL, and a high-level voltage (for example, 3 V) is applied to the selected word line WL3. , Low-level voltage (for example, −5) to unselected word lines WL1, WL2 and WL4 to WL16.
V). As a result, the well selection transistor SWT1 and the selected memory transistor M13
Are turned on, and the unselected memory transistors M11 and the like are turned off.

Thereafter, the gate threshold voltage Vth can be read according to the same principle as in the first and second embodiments, and the same effect can be obtained. That is, instead of reading out the current flowing through the impurity diffusion layer as in the conventional AND type, the source line (in this case, the common line CL) and the p-well W1
Is short-circuited, a predetermined voltage Vin is applied to this short-circuit node, or when a predetermined current I flows through the memory transistor M13, a voltage Vs appearing at the short-circuit node is read, and this voltage Vs is self-stabilized. Since the drain current Id at the time of the reading is very small, it is possible to almost eliminate the fluctuation factor of the reading current due to the source line resistance and the like, and it is possible to perform the reading with high accuracy. Although not particularly shown,
In the NOR type, the source line can be formed of an impurity diffusion layer or the like. In this case, the conventional reading method has a problem that the resistivity of the impurity diffusion layer deviates from a design value during the LOCOS oxidation as in the AND type, and accurate reading cannot be performed due to this. In the method, even if there is such a resistance variation in the process, the current value at the time of reading is extremely small, so that the read voltage Vs is not affected by the resistance variation. In addition, even if the resistance changes with time due to some factor, high-precision reading is not hindered.

Further, since the p-well is separated so that a voltage can be individually applied to at least each row of parallel transistors in the row direction, that is, in the row direction, the p-well is suitable for reading the gate threshold voltage Vth by the source follower. Note that, similarly to the first and second embodiments, the p-well can be separated for each of the plurality of parallel transistor groups. The fact that the p-wells are separated at least in the row direction is similar to the first and second embodiments at the time of writing or erasing, that is, at the time of writing, the breakdown voltage between the source / drain or the channel of the memory transistor and the well and the wells. However, there is an advantage that a high inhibit voltage can be ensured even if the value decreases, and random erasing can be performed in erasing.

[0074]

According to the nonvolatile semiconductor memory device of the present invention, a well selection transistor for switching connection between a memory transistor row and an element formation region (for example, a p-well) is provided for each element formation region. A read control circuit that applies a predetermined voltage to the short-circuit node or applies a predetermined current to the memory transistor and reads the voltage appearing at the short-circuit node enables reading of the gate threshold voltage by the source follower. It is.

According to the reading method of the nonvolatile semiconductor memory device of the present invention, the selected memory transistor is automatically controlled to the pinch off state by the substrate bias effect,
The potential of the short-circuit node is determined stably. For this reason, the current value flowing through the unselected memory transistors and other diffusion layers can be extremely small, and the influence of the resistance variation of the unselected memory transistors and other diffusion layers on the reading of the gate threshold voltage can be extremely reduced. In addition, the reading accuracy can be remarkably improved as compared with the related art. In addition, the potential difference between the channel formation region and the gate at the time of reading can be made at least a small value at which the channel is inverted. As a result, read disturb can be effectively suppressed.

According to the writing method of the non-volatile semiconductor memory device according to the present invention, since the voltage is applied to the unit element formation regions separated in the row direction, the channel potential is set in the setting of the so-called self-boost write inhibit voltage. A high voltage can be reached, disturb resistance can be increased, and erroneous writing to unselected columns can be effectively prevented. At that time,
Even if the breakdown voltage between the unit element formation region and the source / drain impurity region or the channel is reduced due to the miniaturization of the memory transistor, the pn junction between the two regions is formed because the voltage is applied to the unit element formation region. Since no breakdown occurs, device reliability is high. Further, by applying a voltage to the unit element formation region, the pass voltage applied to the non-selected word line can be reduced, and the write disturbance (erroneous writing, etc.) of the non-selection transistor formed in the same unit element formation region as the selected memory transistor can be reduced. Can be effectively prevented.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing a circuit configuration of a memory array of a NAND flash memory and a main part peripheral circuit according to a first embodiment of the present invention.

FIG. 2 is a plan view showing an arrangement of a part of the memory array of FIG. 1;

FIG. 3 is a sectional view taken along line AA of FIG. 2;

FIG. 4 is a sectional view taken along line BB of FIG. 2;

FIG. 5 is a sectional view taken along the line CC of FIG. 2;

FIG. 6 is a circuit diagram showing a basic principle of a reading method according to the present invention.

FIG. 7 is a circuit diagram showing a basic principle of another reading method of the present invention.

FIG. 8 is a table showing a bias voltage setting example at the time of writing and erasing in the first embodiment.

FIG. 9 is a timing chart showing an operation of a bias voltage setting example 2 at the time of writing according to the first embodiment;

FIG. 10 is a timing chart showing an operation of a bias voltage setting example 3 at the time of writing in the first embodiment.

FIG. 11 is a schematic configuration diagram showing a circuit configuration of a memory array of an AND flash memory and a peripheral circuit of a main part according to a second embodiment of the present invention;

FIG. 12 is a plan view showing an arrangement of a part of the memory array of FIG. 11;

FIG. 13 is a sectional view taken along line DD of FIG. 12;

FIG. 14 is a table illustrating bias setting values during writing and erasing in the second embodiment.

FIG. 15 is a schematic configuration diagram showing a circuit configuration of a memory array of a source-separated NOR flash memory and a peripheral circuit of a main part of a NOR flash according to a third embodiment of the present invention.

FIG. 16 shows a HiC among NOR types according to the third embodiment.
FIG. 2 is a schematic configuration diagram illustrating a circuit configuration of a memory array of an R-type flash memory and a peripheral circuit of a main part.

FIG. 17 is a basic circuit diagram showing the principle of a reading method using a general current sense type amplifier.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... NAND type memory array, 2 ... Control circuit (read control circuit), 4 ... A / D converter (read control circuit), 10
... Semiconductor substrate, 12 ... N well, 13 ... Tunnel insulating film, 14 ... Trench (element isolation region), 15 ... Inter-gate insulating film, 16, 17 ... Source / drain region, 18 ... Interlayer insulating layer, 19 ... Well selection Source area, 20 ... AN
D-type memory array, 22 ... source impurity diffusion layer, 24 ...
Drain impurity diffusion layer, 26 source region, 28 drain region, 30 source-separated NOR memory array, 5
0 ... HiCR type memory array, M11 etc ... memory transistor, ST11 etc ... selection transistor, SWT1 etc ...
Well selection transistors, W1, W2... P-wells (unit element formation regions), which are individually settable in voltage, BL
1 etc. bit line, WL1 etc. word line, SG1, SG2
... selection signal line, CL ... common line (common bias line or common source line), SWL ... well selection line, BC1 etc .... bit contact, WC1 etc .... well contact, R ... resistance element, I ... current value by current source, Vin: applied voltage (or its amplitude); Vs: source potential (or its amplitude).

Claims (35)

[Claims] A source impurity region and a drain impurity region are formed in an element formation region formed on a main surface side of a semiconductor substrate, and at least an insulating film is provided on a channel formation region sandwiched between the impurity regions. A method for reading a nonvolatile semiconductor memory device in which a memory array is formed by arranging a plurality of memory transistors each having a stack of gate electrodes in a matrix, wherein the reading is performed using any one of the source impurity region and the drain impurity region. A bias voltage is applied to the other impurity region while the one impurity region and the element formation region where the selected memory transistor is formed are short-circuited,
When a predetermined voltage is applied to the one impurity region via a resistance element, a reading method of a nonvolatile semiconductor memory device which reads a voltage value appearing at a connection node between the resistance element and the one impurity region. 2. A source impurity region and a drain impurity region are formed in an element formation region formed on a main surface side of a semiconductor substrate, and at least an insulating film is formed on a channel formation region interposed between the impurity regions. A method for reading a nonvolatile semiconductor memory device in which a memory array is formed by arranging a plurality of memory transistors each having a stack of gate electrodes in a matrix, wherein the reading is performed using any one of the source impurity region and the drain impurity region. In a state where one of the impurity regions and the element forming region where the selected memory transistor is formed are short-circuited, a predetermined current is supplied between the two impurity regions by a current source provided on the one impurity region or the other impurity region. A non-volatile semiconductor device that reads a voltage value appearing at a connection node between the one impurity region and the element formation region when the current flows. A method for reading a conductor storage device. 3. The method according to claim 1, wherein the element formation region is composed of a plurality of unit element formation regions that are at least separated in a row direction and can individually set a potential. 4. The method according to claim 2, wherein said element formation region is constituted by a plurality of unit element formation regions which are at least separated in a row direction and each of which can individually set a potential. 5. The memory transistor according to claim 1, wherein at least three
2. The method according to claim 1, wherein the memory has a storage state equal to or greater than a value. 6. The memory transistor according to claim 1, wherein at least three
3. The method according to claim 2, wherein the storage state of the nonvolatile semiconductor memory device is equal to or more than a value. 7. The non-volatile memory transistor according to claim 1, wherein said memory transistor has a charge storage means in said insulating film, and writes and erases data by changing a gate threshold voltage in accordance with an amount of charge stored in said charge storage means. The memory array includes two select transistors connected to one or the other of the bit line and the common line, and a plurality of memory transistors serially connected in the column direction between the two select transistors. 2. The method according to claim 1, wherein a plurality of transistor rows are arranged in a matrix. 8. The nonvolatile memory according to claim 1, wherein said memory transistor has a charge storage means in said insulating film, and writes and erases data by changing a gate threshold voltage according to an amount of charge stored in said charge storage means. The memory array includes two select transistors connected to one or the other of the bit line and the common line, and a plurality of memory transistors serially connected in the column direction between the two select transistors. 3. The method for reading a nonvolatile semiconductor memory device according to claim 2, wherein a plurality of transistor rows are arranged in a matrix. 9. The nonvolatile memory according to claim 1, wherein said memory transistor has a charge storage means in said insulating film, and writes and erases data by changing a gate threshold voltage in accordance with an amount of charge stored in said charge storage means. 2. The method according to claim 1, wherein the charge storage unit is discrete at least on a surface facing the channel formation region. 3. 10. The nonvolatile memory according to claim 1, wherein said memory transistor has a charge storage means in said insulating film, and writes and erases data by changing a gate threshold voltage in accordance with an amount of charge stored in said charge storage means. 3. The method according to claim 2, wherein the charge storage unit is discrete at least in a surface facing the channel formation region. 4. 11. A source impurity region and a drain impurity region are formed in an element formation region formed on a main surface side of a semiconductor substrate, and at least an insulating film is provided on a channel formation region sandwiched between the impurity regions. A nonvolatile semiconductor memory device in which a memory array is configured by arranging a plurality of memory transistors each having a stack of gate electrodes in a matrix, wherein the element forming regions are separated at least in a row direction and individually set potentials. A plurality of possible unit element formation regions, and when reading the memory array, short-circuit the one of the source impurity region and the drain impurity region and the unit element formation region where the selected memory transistor is formed. In this state, a bias voltage is applied to the other impurity region, and a voltage is applied to the one impurity region via a resistance element. When a voltage is applied, the non-volatile semiconductor memory device having a read control circuit for reading a voltage value emerges to a connection node between the said resistor element and the one of the impurity regions. 12. A source impurity region and a drain impurity region are formed in an element formation region formed on a main surface side of a semiconductor substrate, and at least an insulating film is formed on a channel formation region sandwiched between the impurity regions. A nonvolatile semiconductor memory device in which a memory array is configured by arranging a plurality of memory transistors each having a stack of gate electrodes in a matrix, wherein the element forming regions are separated at least in a row direction and individually set potentials. A plurality of possible unit element formation regions, and when reading the memory array, short-circuit the impurity region of either the source impurity region or the drain impurity region and the unit element formation region where the selected memory transistor is formed. In this state, a predetermined current is supplied by a current source provided on the one impurity region or the other impurity region. When it flowed between pure object region, the non-volatile semiconductor memory device having a read control circuit for reading a voltage value revealing the connection node between the one impurity region and the element formation region. 13. A short-circuit control transistor that transitions from a non-conducting state to a conducting state in response to an input control signal, and transitions the one impurity region and the unit element formation region from a non-connected state to a connected state. 12. The non-volatile semiconductor memory device according to claim 11, wherein the device is provided for each unit element formation region. 14. A transistor for short-circuit control for transitioning from a non-conducting state to a conducting state in response to an input control signal and for transitioning said one impurity region and said unit element formation region from a non-connected state to a connected state. 13. The non-volatile semiconductor storage device according to claim 12, wherein the device is provided for each unit element formation region. 15. The device isolation region according to claim 11, wherein an element isolation region extending deeper in a deeper side direction of the semiconductor substrate than an adjacent unit element formation region is formed within an interval between the plurality of unit element formation regions. Non-volatile semiconductor storage device. 16. The element isolation region according to claim 12, wherein an element isolation region extending deeper in a direction toward a deeper side of the semiconductor substrate than an adjacent unit element formation region is formed within an interval between the plurality of unit element formation regions. Non-volatile semiconductor storage device. 17. The nonvolatile semiconductor memory device according to claim 11, wherein one of the impurity regions of the short-circuit control transistor and the unit element formation region are connected by a conductive material. 18. The nonvolatile semiconductor memory device according to claim 12, wherein one of the impurity regions of the short-circuit control transistor and the unit element formation region are connected by a conductive material. 19. The nonvolatile semiconductor memory device according to claim 11, wherein said memory transistor has a storage state of at least three values. 20. The nonvolatile semiconductor memory device according to claim 12, wherein said memory transistor has a storage state of at least three values. 21. The non-volatile memory transistor, wherein the memory transistor has charge storage means in the insulating film, and writes and erases data by changing a gate threshold voltage according to the amount of charge stored in the charge storage means. The memory array includes two select transistors connected to one or the other of the bit line and the common line, and a plurality of memory transistors serially connected in the column direction between the two select transistors. The nonvolatile semiconductor memory device according to claim 11, wherein a plurality of transistor rows are arranged in a matrix. 22. The non-volatile memory transistor, wherein the memory transistor has a charge storage means in the insulating film, and writes and erases data by changing a gate threshold voltage according to an amount of charge stored in the charge storage means. The memory array includes two select transistors connected to one or the other of the bit line and the common line, and a plurality of memory transistors serially connected in the column direction between the two select transistors. 13. The non-volatile semiconductor memory device according to claim 12, wherein a plurality of transistor rows are arranged in a matrix. 23. The non-volatile memory transistor, wherein the memory transistor has a charge storage means in the insulating film, and writes and erases data by changing a gate threshold voltage according to an amount of charge stored in the charge storage means. 12. The nonvolatile semiconductor memory device according to claim 11, wherein the charge storage means is discrete at least in a surface facing the channel formation region. 24. The non-volatile memory device, wherein the memory transistor has charge storage means in the insulating film, and writes and erases data by changing a gate threshold voltage according to the amount of charge stored in the charge storage means. 13. The non-volatile semiconductor memory device according to claim 12, wherein the charge storage means is discrete at least in a surface facing the channel formation region. 25. A source impurity region and a drain impurity region are formed in an element formation region formed on a main surface side of a semiconductor substrate, and at least an insulating film is formed on a channel formation region interposed between the impurity regions. A memory array is configured by arranging a plurality of memory transistors each having a stack of gate electrodes in a matrix, and the element forming region is configured by a plurality of unit element forming regions that are separated at least in a row direction and can be individually set a potential. A method of writing data in a nonvolatile semiconductor memory device, comprising: setting a predetermined voltage to at least one of the source impurity region and the drain impurity region of a non-selected transistor row during data writing; A writing method for a nonvolatile semiconductor memory device, wherein a voltage having the same polarity as the predetermined voltage is applied to the unit element formation region. 26. The non-volatile memory transistor, wherein the memory transistor has charge storage means in the insulating film, and writes and erases data by changing a gate threshold voltage according to the amount of charge stored in the charge storage means. The memory array is a transistor array including two select transistors connected to one or the other of a bit line and a common line, and a plurality of memory transistors connected between the two select transistors. 26. The writing method of the nonvolatile semiconductor memory device according to claim 25, wherein a plurality of are arranged in a matrix. 27. In the setting of the predetermined voltage, when the gate application voltage of the selection transistor on the bit line side is VSG1 and the threshold value is Vth, the source impurity region and the drain impurity region of the non-selected transistor row are set. (VSG1 -Vth) so that is not electrically connected to the bit line.
27. The above voltage is set in the source impurity region or the drain impurity region of the non-selected transistor row.
3. The writing method for a nonvolatile semiconductor memory device according to item 1. 28. At the time of data writing, a selection transistor on the common line side of a non-selected transistor column is turned off, and a selection transistor on the bit line side is turned on, and a gate electrode of the memory transistor is shared in a row direction. After applying a pass voltage to the plurality of connected word lines to boost the channel potential of the unselected transistor column, before applying a predetermined program voltage to the word line of the selected row, the voltage applied to the unit element formation region is reduced. The writing method of the nonvolatile semiconductor memory device according to claim 26, wherein a voltage is applied. 29. The memory transistor having at least 3
27. The nonvolatile semiconductor memory device according to claim 26, wherein when information is sequentially written in a storage state equal to or more than a value, a voltage is applied to the unit element formation region in a selected column by changing a voltage value for each write in each storage state. Writing method. 30. A source impurity region and a drain impurity region are formed in an element formation region formed on a main surface side of a semiconductor substrate, and at least an insulating film is formed on a channel formation region sandwiched between the impurity regions. A memory array is configured by arranging a plurality of memory transistors each having a stack of gate electrodes in a matrix, and the element forming region is configured by a plurality of unit element forming regions that are separated at least in a row direction and can be individually set a potential. The method for writing data in a nonvolatile semiconductor memory device according to claim 1, further comprising: setting a predetermined voltage to at least one of the source impurity region and the drain impurity region of the non-selected transistor row during data writing. A method of applying a voltage having the same polarity as the predetermined voltage to the unit element formation region. 31. A nonvolatile memory having a charge storage means in said insulating film, wherein a data is written and erased by changing a gate threshold voltage according to an amount of charge stored in said charge storage means. The memory array is a transistor array including two select transistors connected to one or the other of a bit line and a common line, and a plurality of memory transistors connected between the two select transistors. 31. The writing method for a nonvolatile semiconductor memory device according to claim 30, wherein a plurality of are arranged in a matrix. 32. In the setting of the predetermined voltage, when the gate applied voltage of the select transistor on the bit line side is VSG1 and the threshold value is Vth, the source impurity region and the drain impurity region of the non-selected transistor row are set. (VSG1 -Vth) so that is not electrically connected to the bit line.
32. The above voltage is set in the source impurity region or the drain impurity region of the unselected transistor row.
3. The writing method for a nonvolatile semiconductor memory device according to item 1. 33. At the time of data writing, after applying a voltage to the unit element formation region, a selection transistor on the common line side of a non-selected transistor row is turned off, and a selection transistor on the bit line side is turned on. 5. A method according to claim 1, wherein a pass voltage is applied to a plurality of word lines in which gate electrodes of said memory transistors are commonly connected in a row direction to raise a channel potential of said transistor column, and a predetermined program voltage is applied to a word line of a selected row. 32. The writing method of the nonvolatile semiconductor memory device according to item 31. 34. The voltage applied to the unselected bit line is set to (VSG
34. The method according to claim 33, wherein the applied voltage to the unit element formation region of the non-selected transistor row is set to be equal to or lower than the channel potential of the non-selected transistor row. . 35. The memory transistor having at least 3
31. The nonvolatile semiconductor memory device according to claim 30, wherein, when information is sequentially written in a storage state equal to or more than a value, a voltage is applied to the unit element formation region in a selected column by changing a voltage value for each write in each storage state. Writing method.