JPH02223097A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To attain electric write with high reliability by keeping a source, a drain and a base to a low level at erasure and write and applying a reverse high voltage to a control gate at the erasure and write. CONSTITUTION:Data in memory cells M1-M8 are erased by applying a negative high voltage to all word lines WL and connecting all other terminals to ground, electrons are emitted to the base board from a floating gate in all the memory cells to decrease the threshold level. The data write ('0' write) is implemented to a memory cell whose threshold level is decreased by applying electron injection to the floating gate selectively from the remote bit line BL to move the threshold level to a positive polarity. Since the data write and erasure is implemented by giving a positive and negative high voltage to the word line, the base current is less, the deterioration in this gate insulation films 3, 5 is suppressed and the reliability of a nonvolatile memory is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a nonvolatile semiconductor memory device using an electrically rewritable memory cell having a charge storage layer and a control gate.

(Prior Art) FETMOS (FloatlngGat
e -E 1ectron Tunneling
MOS) is known. This has a MOS transistor structure in which the entire channel region is covered with a thin gate insulating film (tunnel insulating film) through which a tunnel current easily flows, and a charge storage layer and a control gate are laminated thereon. n
Consider a channel FETMOS memory cell. In order to emit electrons from the charge storage layer to the substrate in this memory cell,
A high positive voltage is applied to the drain or source, and the control gate and substrate are grounded. Conversely, when electrons are injected from the substrate into the charge storage layer, the source, drain, and substrate are grounded and a high positive voltage is applied to the control gate. By applying such a voltage, charges are exchanged between the charge storage layer and the substrate by a tunnel current. A state in which the threshold value moves in the negative direction due to electron emission from the charge storage layer and a state in which the threshold value moves in the positive direction due to electron injection into the charge storage layer are obtained, one of which is 0° and the other is Information is stored as "1".

For example, the operation of emitting electrons from the charge storage layer to the substrate corresponds to data erasing, and the operation of injecting electrons from the substrate to the charge storage layer corresponds to data writing.

However, the following problem exists in the method of rewriting a FETMOS memory cell in which children are connected. In a FETMOS with a low surface breakdown voltage in which the boundary between the drain or source and the channel region is covered with a thin gate insulating film, the substrate current flowing from the drain to the substrate is large in the operation mode in which a high positive voltage is applied to the drain or source. , the current consumption during rewriting increases. If the current consumption during rewriting is large as described above, it becomes difficult to generate a high voltage inside the memory chip, and it becomes necessary to apply a high voltage from outside the chip.

This is very difficult for users to use. Also,
It has been reported that the flow of a large substrate current during rewriting can cause deterioration of the thin gate insulating film of memory cells (for example, 1987 IEDM Proceedings, p. 9).
544-547).

In E2 FROM, this deterioration of the gate insulating film is a major cause of reduced reliability, such as limiting the number of data rewrites and deteriorating data retention characteristics.

NAND by connecting multiple FETMOS memory cells in series
A similar problem exists in the E2 FROM, which has a cell structure. In the NAND cell system, data is erased all at once, and then data is selectively written. - In the batch erase operation, first, the first word line connected to the bit line is grounded, a positive high voltage is applied to the bit line, and the memory cells along the first word line are erased. ,
The operation of applying a high positive voltage to the first word line, setting the second word line to the ground potential, and similarly erasing the memory cells along the second word line is repeated.

At this time, electrons in the charge storage layer of the selected memory cell are emitted to the substrate, but at the same time, a substrate current flows from the drain to the substrate. In a NAND cell, such a batch erase operation is always performed when data is rewritten, so a large substrate current flows, which deteriorates the thin gate insulating film. This deterioration of the gate insulating film affects data retention characteristics. For example, if the gate insulating film deteriorates and the leakage current in a low electric field increases, electrons may be injected from the drain or substrate into the charge storage layer in the memory cell during read operations, leading to data reversal. becomes larger.

(Problems to be Solved by the Invention) As described above, in the conventionally proposed data rewriting method for FETMOS memory cells, the substrate current is large, which makes it difficult to configure the internal booster circuit, and also reduces the reliability of the memory cell. There was a problem of deterioration.

The present invention has solved these problems. An object of the present invention is to provide a highly reliable electrically rewritable nonvolatile semiconductor memory device.

[Means for solving the problem] The present invention has a structure in which a charge storage layer and a control gate are stacked on a semiconductor substrate, and utilizes transfer of charge between the charge storage layer and the substrate by a tunnel current. In a nonvolatile semiconductor memory device using a memory cell that performs electrical rewriting, the source, drain, and substrate are kept at a low potential during both erasing and writing, and the control gate is set to have opposite polarity during erasing and writing. It is characterized by applying a high voltage.

(Function) According to the present invention, the drain, source, and substrate of a memory cell are kept at a low potential during both erasing and writing, so that a large substrate current as in the conventional case does not flow. Therefore, there is no deterioration of the thin gate insulating film, and a highly reliable nonvolatile memory can be obtained.

Furthermore, since a large substrate current does not flow, it becomes easy to obtain a boosted potential inside the chip.

(Example) Embodiments of the present invention will be described with reference to the drawings.

The following example shows the NA using n-channel FET MO8.
This is an ND cell type E2 FROM. Whether the operation of injecting electrons into the charge storage layer of a memory cell or the operation of emitting electrons from the charge storage layer to the substrate corresponds to data writing or data erasing depends on the “write” and “write” operations.
Depends on how "erasing" is defined. Here, the operation of emitting electrons from the charge storage layer and moving the threshold value in the negative direction corresponds to data erasing, and selectively injecting electrons from the substrate into the charge storage layer. Match the case to data writing.

FIG. 1 is an equivalent circuit diagram showing a memory cell array of one embodiment, FIG. 2 is a plan view showing one NAND cell, and FIGS. -B- sectional view, FIG. 4 is a timing diagram for explaining the operation, FIG. 5 is a diagram showing the potential relationship of each part during a write operation, and FIG. 6 is a diagram showing the potential relationship of each part during a read operation. .

First, focusing on one NAND cell, its configuration will be explained. In this embodiment, eight memory cells M1 to M are provided in a region separated by an element isolation insulating film 2 on a p-type silicon substrate 1.
8 and two selection transistors sl, s are formed. Each memory cell has a first layer made of a thermal oxide film on the substrate 1.
A floating gate 4 (4, to 48) made of a first layer polycrystalline silicon film is formed via a gate insulating film 3, and a control gate made of a second layer polycrystalline silicon film is formed on this via a second gate insulating film 5. 6 (6, to 68) are formed and configured. The floating gate 4 of each memory cell is a charge storage layer. The control gate 6 of each memory cell is connected to the word line W
L (WLl-WL8). Eight memory cells are connected in series so that the n◆ type layer 9, which serves as the source and drain of the memory cell, is shared by adjacent cells. In this embodiment, selection transistors S1+S3 are connected to the drain side and the source side to form one NAND
Cell is configured. The gate electrodes 49, 69 and 411, 610 of the selection transistor S1+83 are obtained by simultaneously patterning the first and second layer polycrystalline silicon films that constitute the floating gate and control gate of the memory cell, and are formed between the electrodes 49 and 69. The electrodes 4 and 610 are in contact with each other at a predetermined interval in the word line direction. The whole is C
An Al wiring 8 is provided as a bit line BL which is covered with a VD insulating film 7 and contacts the n+ type layer which is the drain of the selection transistor Sl for the memory cell. This contact portion is doped with n-type impurities.

Coupling capacitance c between floating gate 4 and substrate 1 in each memory cell
1 is set smaller than the coupling capacitance C2 between the floating gate 4 and the control gate 6. To explain the specific dimensions, both the floating gate 4 and the control gate 6 have a channel width of 1 μm1, so the channel length of the memory cell is 1 μm, and the floating gate 4 is located above the field region as shown in FIG. 3(b). It extends 1 μm on each side.

The first gate insulating film 3 is a thermal oxide film of 110 people, and the second
The gate insulating film 5 is a 350-layer thermal oxide film.

Regarding the selection transistor S1.82, the channel length of the selection transistor S1 on the drain side, that is, on the bit line side, is set longer than that of the selection transistor S3 on the source side.

This is to prevent punch-through of the selection transistor S1. A source diffusion layer to which a ground potential is applied is commonly formed in the word line direction.

The operation of the E2 FROM thus configured will be described next. FIG. 4 shows a NAN consisting of memory cells M1 to M8.
FIG. 4 is a timing diagram of data erasing and writing when focusing on a D cell.

First, data in memory cells M to M8 is erased. This data erasure is performed by applying a negative high voltage, in this embodiment, -20V to all word lines WL, and grounding all other terminals. At this time, electrons are emitted from the floating gates of all memory cells to the substrate, and the threshold value becomes, for example, -2■. The data in the memory cell in this erased state is assumed to be "11." In this erase operation, the substrate current is only a tunnel current, which is significantly smaller than when a high voltage is applied to the drain.

Data writing (“0” writing) is performed by selectively injecting electrons into the floating gates of memory cells whose threshold values have become smaller, starting from the side farthest from the bit line BL, thereby moving the threshold values in the positive direction. This is done by letting FIG. 5 shows the potential relationship of each part during the write operation of memory cells M8 to M6. First, to write to the memory cell M8, an intermediate potential (-9V) is applied to the word lines WL, ~WL7, and the gate control line SD1 of the selection transistor SI on the bit line side is applied.
and a word line WL connected to the control gate of memory cell M8.
A positive high voltage (-18V) is applied to the source-side selection transistor S3, and the control line SS1 of the source-side selection transistor S3 is set to a low potential (-0V). At this time, when a low potential (-0V) is applied to the bit line BL, a high electric field is applied between the substrate and drain of the memory cell M8 and the floating gate, and electrons are injected into the floating gate by a tunnel current. As a result, memory cell M8 is
The threshold value moves in the positive direction, for example, threshold value 2■ becomes “0”.
“Write state is entered.At this time, other memory cells Ml-M
In No. 7, only a weak electric field due to an intermediate potential is applied between the control gate and the substrate, and the erased state is maintained. Next, to write "0" to memory cell M7, a high voltage is applied to word line WL7, word lines WL1 to WL6 on the bit line side are set to an intermediate potential, and the control gate of memory cell M8, which has already been written, is The connected word line WL8 is at a low potential (-0V) or an intermediate potential. This causes the bit line BL to have a low potential of -
0V), electrons are similarly injected into the floating gate of memory cell M7, and 0" writing is performed. Thereafter, writing is sequentially performed in memory cells M6, M5, . . . in the same manner.

Writing "1" data is performed by applying an intermediate potential to the bit line BL to prevent electron injection into the floating gate, that is, by maintaining the erased state. In addition, the bit line BL,
During data writing to memory cells M1 to M8 connected to the word lines WL1 to WL, data is written to memory cells of other bit lines controlled by the same word lines WL1 to WL by similarly applying a bit line potential according to the data. Writing can be performed.

FIG. 6 shows the potential relationship during a read operation for one NAND cell. This example is a case where data is read from memory cell M3.

A low potential (-0V) is applied to the word line WL3 connected to the selected memory cell M3, and a read voltage (-5V) is applied to the control line of the selection transistors S1 to S3 and all remaining word lines. As a result, no current flows when the memory cell M3 is in the "0" state where the threshold is high, and current flows when the memory cell M3 is in the "1°" state where the threshold is low.

As described above, in this embodiment, by using high positive and negative voltages, the source, drain, and substrate of the memory cell are
prevents high voltage from being applied. Therefore, the substrate current becomes only a tunnel current, and deterioration of the thin gate insulating film is prevented. Further, since the voltage applied to the drain is only an intermediate potential during data writing, the gate length of the selection transistor provided on the drain side can be made shorter than in the conventional case. This is advantageous for high integration of memory cells.

By the way, in order to apply positive and negative high voltages to the word line, not only a p-channel MOS transistor is required around the cell array, but also a positive and negative voltage.

It is also necessary to devise a circuit to switch the supply of negative voltage. This peripheral circuit section will be explained with reference to FIG.

As shown in FIG. 1, an n-type well 121 is formed on the right side of the word line arrangement of the NAND cell array 11, and a first p-channel MOS transistor group 131 connected to each word line WL is formed in this well. Ru. An n-type well 122 is similarly formed on the left side of the NAND cell array 11, and second p-channel MOS transistors 132 connected to each word line WL are arranged therein. first p
The channel MOS transistor group 131 is for applying a negative high voltage to the word line of at least one block in the NAND cell array 11 during data erasing, and the source (or drain) is connected to each word line, and the drain (or source) and gate of at least one NAND cell block (8X1
A common signal line C is connected to each block of 024 bits.
Connected to GE and 5CC1. n-type well 12
1 is connected to a well potential control signal line HW1. The second p-channel MOS transistor group 132 is connected to the NA from the first p-channel MOS transistor group 131 side.
When a negative high voltage is applied to the ND cell array 11, the decoder circuit 1 consisting of n-channel MOS transistors
This is provided to prevent the signal from being transmitted to the 4th side. The positive voltage from decoder circuit 14 is applied to this first p-channel MO
NAND cell array 1 through S transistor group 132
It is transmitted to In order to exhibit such a switching function, the n-type well 122 and the second p-channel MO
The gates of the S transistor group 132 are connected to control signal lines HW2 and 5CG2, respectively, so that necessary control signals are applied to these lines.

The operation of the peripheral circuit section configured in this manner will be described next.

First, when erasing data, CGE” 20V, 5CG
I--25V, HWt.

Vcc"5V is applied to HW2 and 5CG2. At this time, the p-channel MOS transistor group 121 of il is on, and the second p-channel MOS transistor group 122 is off.SCG.

The negative voltage applied to -25V is applied to CGE--
This is to transfer 20V to the word line without dropping by the threshold voltage. As a result, -20V is transferred to the word line WL of the NAND cell array 11, and as described above, all the memory cells, in this example, 8192-bit memory cells are erased.

When writing data, for example, when writing to memory cell M8 along word line WL8, CGE-5V, 5V,
CGl, HWl and HW2 are set to 18V, 5CG2-
OV. Then, the decoder output to word lines WL1 to WL7 is 9V, and the decoder output to word line WL8 is 18V.
Let it be V.

At this time, the first p-channel MoS transistor group 12
1 is off, second p-channel MOS transistor group 12
2 is turned on, and the word lines W L 1 to W L 7 L are turned on through the second p-channel MOS transistor group 122.
9V, 7-domain line WLsl: 18V is applied. Necessary potentials are applied to the bit line and other control lines, respectively, as in the data writing described above.

As a result, data writing is performed.

When reading, SCG, HW, nw2 and CGE are set to 5V, and 5CG2-5V. This allows the first
The p-channel MOS transistor group 121 is off, and the second p-channel MOS transistor group 121 is off.
The p-channel MOS transistor group 122 is turned on. The output of the word line A from the decoder is Ov2 corresponding to the selected word line as described above, and the other outputs are 5V. As a result, data from memory cells along the selected word line is read. What makes 5CG2 -5v is
This is to transfer 0■ to the word line without threshold voltage drop.

By arranging the p-channel MOS transistor groups on both sides of the NAND cell array in this manner, positive and negative high voltages can be supplied to the word line without any problem.

[Effects of the Invention] As described above, according to the present invention, since data is written and erased by applying positive and negative high voltages to word lines,
Compared to the conventional method, the substrate current is reduced, the deterioration of the thin gate insulating film is suppressed, and the reliability of the nonvolatile memory is improved. Furthermore, since the substrate current is small, it becomes easy to construct a booster circuit inside the chip.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit diagram showing the main part configuration of an E2 FROM according to an embodiment of the present invention, FIG. 2 is a plan view showing the configuration of one of the NAND cell parts, and FIGS. 3(a) and 3(b) are A in Figure 2
-A- and B-B- cross-sectional views, Fig. 4 is E of this embodiment.
2 is a timing diagram for explaining the operation of FROM. FIG. 5 is a diagram showing the potential relationship of each part during data writing, and FIG. 6 is a diagram showing the potential relationship of each part during data reading. 11...NAND cell array, 12. ．． 122...
n-type well, 131... first p-channel MOS transistor group, 132... second p-channel MOS transistor group, 14... decoder circuit, M1 to M8...
・Memory cell, WL, ~WL8...Word line, BL・
... Bit line, 1... P-type silicon substrate, 2... Element isolation insulating film, 3... First gate insulating film, 4... Floating gate, 5... Second gate insulating film, 6...Control gate. Applicant's representative Patent attorney Takehiko Suzue Diagram Diagram (a) (b) Fuzuzu v O■ 0■ Hemp Diagram

Claims (4)

[Claims] (1) In a nonvolatile semiconductor memory device configured by stacking a charge storage layer and a control gate on a semiconductor substrate, and arranging memory cells that perform data rewriting by transferring charge between the charge storage layer and the substrate, There is an erase mode in which a high negative voltage is applied to the control gate of the selected memory cell, and the source, drain, and substrate are set at a low potential and electrons in the charge storage layer are released to the substrate. 1. A nonvolatile semiconductor memory device having a write mode in which electrons are injected from the substrate into a charge storage layer by applying a voltage to the source, drain, and substrate at a low potential. (2) A charge storage layer and a control gate are stacked on a semiconductor substrate, and a plurality of memory cells that perform data rewriting by transferring and receiving charge between the charge storage layer and the substrate are connected in series to form a NAND cell. Arranged in matrix, each NAN
In a nonvolatile semiconductor memory device in which the drain of one end of a D cell is connected to a bit line and the control gate of each memory cell is connected to a word line, a selected NA
There is an erase mode in which a high negative voltage is applied to all word lines in the ND cell, the bit line is set at a low potential, and electrons in the charge storage layer are released to the substrate, and a high positive voltage is applied to the selected word line. , the selected bit line is set to a low potential, the unselected word line and the unselected bit line are set to a positive intermediate potential,
1. A nonvolatile semiconductor memory device having a write mode in which electrons are injected from a substrate into a charge storage layer in a selected memory cell. (3) A first p-channel MOS transistor group connected to each word line is arranged at one end of the word line arrangement of the NAND cell array, and a second p-channel MOS transistor group connected to each word line is arranged at the other end. A group of p-channel MOS transistors is arranged, and the first group of p-channel MOS transistors is turned on.
Turning off the second p-channel MOS transistor group,
A negative high voltage is applied to the word line via the first p-channel MOS transistor group, the first p-channel MOS transistor group is turned off, the second p-channel MOS transistor group is selectively turned on, and the second p-channel MOS transistor group is turned off. p-channel MOS
3. The nonvolatile semiconductor memory device according to claim 2, wherein a positive voltage or a ground potential is applied to the word line via the transistor group. (4) The nonvolatile semiconductor memory device according to claim 1, wherein in the memory cell, the gate insulating film between the charge storage layer and the substrate is a thin tunnel insulating film over the entire channel region.