JPH0373497A - Non-volatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To optimize a word line boosting circuit part by providing the non- volatile semiconductor memory device with the 1st boosting circuits for supplying a high voltage to a selection gate line and the 2nd boosting circuits for supplying a high voltage to a word line controlled and selected by the 1st boosting circuit. CONSTITUTION:In a row decoder 12, output lines for selecting word lines WL are connected to word lines WL corresponding to plural cell blocks 111, 112 in common and the cell blocks 111, 112 are selected by output lines for selecting selection gate lines SG. Since a selection signal is supplied also to the other word line WL 112 or 111 when one block line 111 or 112 is selected, the output of the 1st boosting circuit 15 for supplying the high voltage to the selection gate line SG is executed with priority and the 2nd boosting circuit 16 for supply ing the high voltage to the word line WL is controlled by the output of the circuit 15. Thereby, even when the word line WL is selected, the word line WL in the non-selected cell block 111 or 112 can be prevented from being boosted.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to an electrically rewritable nonvolatile memory cell configured using a MOS transistor structure memory cell having a floating gate and a control gate. Semiconductor processing equipment (EEFROM)
Regarding.

(Prior Art) In the field of EEFROM, memory cells having a MOS (MOS) transistor structure having a floating gate and a control gate are widely known. The EEFROM memory array is constructed by arranging memory cells at each intersection of row lines and column lines that intersect with each other. In the actual pattern, the drains of the two memory cells are made common and the column line is connected thereto.

However, even in this case, a contact with a column line is required for each common drain of two memory cells, and this contact portion occupies a large portion of the cell occupation area.

As a promising solution to this problem, the applicant has previously proposed NA
We are proposing an EEPROM that uses ND cells (Special application 1986).
2-233944). This NAND cell is constructed by connecting a plurality of memory cells having a gate and a control gate in series so that they share a source and a drain. Erasing and writing data in this NAND cell utilizes electron tunneling between the floating gate and the drain layer or substrate. The write and erase operations will be specifically explained. To erase data, apply a "H" level potential of about 17V to all the word lines of the memory cells that make up the NAND cell, and give a "L" level potential of 0 to the bit line.This makes all memory cells conductive. , electrons are injected from the substrate into the floating gate by tunneling, resulting in an erased state in which the threshold voltage moves in the positive direction (eg, threshold voltage 2V).

Data writing is performed in order from the memory cell farthest from the bit line among the NAND cells. At this time, a "H" level potential of about 22V, for example, is applied to the bit line, OV is applied to the word line of the selected memory cell, and 22V is applied to the unselected word line.

A word line connected to a memory cell to which writing has already been performed is assumed to be Ov. As a result, the potential of the bit line is transmitted to the drain of the selected memory cell, and in this selected memory cell, electrons from the floating gate are emitted to the drain, resulting in a "1" write state (for example, At this time, no voltage is applied between the control gate and the substrate in the memory cell located on the bit lI side from the selected memory cell, and no writing is performed. Apply an intermediate potential to the wire, for example 11■.

At this time, unselected memory cells on the bit line side of the selected memory cell enter a weak erase mode, but because the electric field is weak, over-erasing does not occur. To read data, change the selected word line to “
This is performed by setting the remaining word lines to an intermediate level (for example, mi voltage Vcc) and determining whether or not current flows through the NAND cell.

Such a NAND cell type EEFROM is attracting attention as a device that can be integrated at an extremely high density, but peripheral circuits have not yet been optimized.

(Problems to be Solved by the Invention) As described above, in the new NAND cell type EEPROM, optimization of the peripheral circuits still remains.

The present invention has been made in view of these points, and an object of the present invention is to provide a NAND cell type EEFROM with an improved word line booster circuit section.

[Structure of the Invention] (Means for Solving the Problem)' The NAND cell type EEFROM according to the present invention has a first booster circuit that supplies a high voltage to the selection gate line as a structure of the word gland booster circuit section. , a second booster circuit is provided which is controlled by the first booster circuit and supplies a high voltage to the selected word line.

(Function) In a NAND cell type EEPROM, the row decoder has a 1-bit (or 2-bit) decoder output for selecting a selection gate line in addition to an output for selecting a word line. An output line for selecting a word line is commonly provided for corresponding word lines of a plurality of cell blocks, and selection of a cell block is performed by an output line for selecting a selection gate line. Therefore, when a cell block is selected, the decoder output selection signal is also supplied to the word lines of other cell blocks at the same time, so priority is given to the output of the first booster circuit that supplies the selection gate line. By controlling the output of the second booster circuit and the second booster circuit that supplies a high voltage to the word line by its output, the word line of the cell block whose word line is selected by the row decoder but not selected can prevent pressure increase.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

Figure 1 shows an example of a NAND cell type This is an equivalent circuit showing the configuration of the slave part of an EEPROM.

11 is a memory cell array, and here two adjacent cell blocks 111 and 112 are shown. The memory cell array includes a plurality of memory cells M, , M2 . ..., NAN where Ms are connected in series
D cells are arranged in a matrix, one end of each NAND cell is connected to bit 1iBL via selection gate Sl,
The control gate CG is commonly connected to the word line WL for NAND cells in one direction. 12 is a row decoder that selects the word line WL and selection gate line SG that commonly connect the control gates CG of memory cells; 14 is a column decoder that selects the bit line BL; 13 is a sense amplifier that amplifies the data on the bit line. It is. A first booster circuit 1 for supplying a high voltage to the selection gate IsG and word line WL during rewriting for each cell block.
5 (15,, 15□) and the second booster circuit 16 (16,
, 162). The second booster circuit 16 is configured to output a high voltage under the control of the output of the first booster circuit 15, as will be described in detail later.

FIG. 5 is a plan view specifically showing one NAND cell of the memory cell array 11, and FIGS. 6(a) and 6(b) are cross-sectional views taken along lines AA' and BB'. This one NA
Focusing on the ND cell and explaining its structure, the device isolation insulation J! In this embodiment, eight memory cells M, .about.M8 and two selection gates S, . . . S2 are formed in the region divided by 12. Each memory cell has a first gate insulator II! made of a thermal oxide film on the substrate 1!
Floating gates 4 (41 to 48) made of a first layer polycrystalline silicon film are formed via I3, and control gates 6 (61 to 48) made of a second layer polycrystalline silicon film are formed thereon via a second gate insulating film 5. 611) is formed. The control gate 6 of each memory cell is connected to the word li [WL (WL,
~WL8>. Eight memory cells are connected in series so that the n+ type layer 9 serving as the source and drain of the memory cell is shared by adjacent cells. In this embodiment, a selection gate SL is provided on the drain side and the source side.
S2 are connected to form one NAND cell.

Gate electrodes 49, 69 and 4 of selection gates Sl, S2
+o+6+o is obtained by simultaneously patterning the first and second layer polycrystalline silicon films that constitute the floating gate and control gate of the memory cell, and electrodes 4 and 6. Questions and 4
8. and 6+o are in contact at a predetermined interval in the word line direction. The entire structure is covered with a CVD insulating film 7, and an AfI wiring 8 is provided as a bit line BL which contacts the n+ type layer which is the drain of the selection gate Sl for the memory cell. This contact portion is doped with n-type impurities (as shown by the broken line in FIG. 6(a)).

Floating gate 4 and substrate 1 in each memory cell [:1 II!
i total capacitance Cr is floating gate 4 and control gate 61H1
The coupling capacitance of L and X is set smaller than C2.

To explain the specific dimensions, both the floating gate 4 and the control gate 6 have a turn width of 1 μm1, so the channel length of the memory cell is 1 μm, and the floating gate 4 has a field width as shown in FIG. 6(b). 1 on each side of the area
The length is extended by μm. The first gate insulating film 3 is 11
The second gate insulator @5 is a thermal oxide film of 350.

For selection game) Sl and S2, drain 0111 (
That is, the channel length of the selection gate S1 on the bit line side is set longer than that of the selection gate S2 on the source side. This is to prevent the selection gate Sl from being punched through. Further, one source diffusion layer to which a ground potential force is applied is formed in common in the word line direction.

Such a NAND cell has a bit line contact.

A memory array is constructed by folding the memory array in the bit line direction while sharing a source diffusion layer.

FIG. 2 shows the configuration of the main parts of FIG. 1 more specifically. First booster circuit 15 and second booster circuit 16
are both connected to a capacitor C and a MOS transistor Q1. It is based on a charge pump circuit composed of G2.

First booster circuit 1 for supplying high voltage to selection gate
A gate circuit G1 is provided at the front stage of the charge pump circuit 5. The gate circuit G1 sends a repetitive clock φ8 from a ring oscillator (not shown) to the charge pump circuit only when the write control signal φW reaches the "H" level.・In the preceding stage of the second promotion circuit 16 for supplying high voltage to the hood line, a signal from a ring oscillator (not shown) is provided only when the write control signal φ1 or the erase control signal φ8 reaches “H” level. A gate circuit G2 is provided that repeatedly sends the clock -2 to the charge pump circuit.Also, on the second booster 10 circuit 16 side, the clock is output only when the output of the first booster circuit 15 outputs a high voltage. A NAND gate (G3) for sending φR to the charge pump circuit is provided.That is, this NAND gate G3 is provided only when the output of the gate G2 (4, the output of the first booster circuit 15 becomes a high voltage). , and is sent to the word line boosting charge pump circuit 1.: as a control signal.

The reason why the first booster circuit 15 for the selection gate is given priority and the second booster circuit 16 for boosting the word line is activated is as follows. The toothpick row decoder 12 shown in FIG. 1 outputs an output for selecting a word line and at the same time outputs an output for selecting a selection gate control line. In other words, in the example of FIG. 1, the row decoder 12 has eight words 1! The part that selects WL, -WL8 and the adjacent cell ◆Block 11. ．． It includes a 2-bit decoder that selects the selection gate lines SG, , SG2 of II□. Then, the output for selecting eight word lines WL, -WL is from these adjacent cell blocks lli, l12.
is commonly supplied to each corresponding word line. That is, when rewriting data, when an "H° level output is supplied to a certain selected word line, an "H level output is simultaneously supplied to the corresponding word lines in cell blocks 11., 112. In this case, the selection gate line S of either cell block 11+ or l12
The "H2 level" is supplied only to G+ so that the cell block is selected. However, the output of the row decoder 12 causes the word line, which is also an unselected cell block, to go "H" level. Then, if
The second booster circuit 16 for +4 voltage on the +4 voltage line can be
If ε boosts the word line that has reached the t'' level, data will be rewritten in unselected cell blocks at the same time.Therefore, the first booster circuit 15 that boosts the selection gate line S G + is connected. , the output of the first booster circuit 15 is separated from the second booster circuit 16 that boosts the word line.
The purpose is to prevent such malfunctions by making the second booster circuit 16 work only when the level is H°, that is, only for the selected cell block.

Furthermore, since the negative word lines are arranged in two cell blocks 111 and 112 in different ways, for example, the voltage boosted by the second booster circuit 16□ is applied to the selected cell block 11□. If this simultaneously supplies unselected cell block 11. It is necessary to prevent it from being supplied to Therefore, a D type MOS transistor is interposed on the word line between the row decoder 12 and the cell block. Further, the first booster circuit 1.5. ．． In order to prevent the boosted voltage of 15□ from being directly input to the row deco-l12, the selection gate line SG+.

Similarly, S02 also has a D type MO on the row decoder 12 side.
It is desirable to include an S transistor, and FIG. 1 shows such a configuration.

Next, the specific operation of the EEPROM of this embodiment will be explained.

First, when erasing data, the row decoder 121. : outputs "H" level to all eight word lines WL to WL8, and outputs, for example, 5V. The output section that controls the selection gate in the row decoder 12 is, for example, SGI, SG2.
is 'H' level (5v), sG,,SG2 is 'L'
level (OV). At this time, two cell blocks 1]l.

In the cell block 111 of the cell blocks 112, the selection gate (isG) is at the "H" level, so the first booster circuit 15. MOS) transistor Q.

turns on. And this first promotion circuit X5. Since the ring oscillator output clock φR (a square wave with an amplitude of 5 V) is input to the capacitor C via the gate circuit G,
Due to the action of the charge pump, the selection gate 1il
SG is boosted to a boosted potential VpII (for example, 17V). This boosted output is applied to one side of the NAND gate GS via the MOS transistor Q to which Vcc-5V is applied to Vce-Vth (for example, 4V).
Since the ring oscillator output section 8 is input to the other input of the NAND gate G1, the second booster circuit 16 also has a charge pump circuit for each word line to which the °H level is applied. The eight word lines WL, -WL8, namely the control gates CG, ~CG, also have vpp
The pressure is increased to This state is shown in FIG. 4(a), where data is erased from all memory cells in the cell block 111.

At this time, regarding the other cell block 112, the selection gate line SG is at the "L" level. Therefore, the first promotion circuit 15 on this cell block 112 side. teeth,
MOS) transistor connected to boosted potential Vl)I)
Since the MOS transistor Q1 (corresponding to the MOS transistor Q1 in FIG. 2) is off, it does not perform a charge pump action even if the ring oscillator output φR is input. If this first booster circuit 152 does not output a high voltage, the ring oscillator output φR will not be supplied to the second booster circuit 62, so even if the word line is at the H1 level, the word line boost voltage will be reduced. There isn't.

Therefore, data erasure does not occur in this cell block 11□.

When writing data, for example, when writing to the memory cell of the word line WL in the cell block 111, if you add 4,
The output of the row decoder 12 is CG, up to CG.
High level CG? .

CG is set to "L" level, and selection gate line SG is set to "L" level.

is set to "H" level and SC2 is set to 'L# level.

Unselected cell block 11. side selection gate output SG
1. Both SGi are set at the 'Lm level. At this time, the first booster circuit 15 on the cell block 111 side has data lr1.
It acts as a charge pump in the same way as in the previous case, and Vl)I)
For example, if you switch to 22V, the selection gate line SG,
A boosted potential of 22V is applied to. Then, under the control of this output, the second booster circuit 16. also works, and a 22V boosted potential of 22V is applied to the part where the word line is at “H” level.
is given. The state of this boosting is shown in FIG. 3, and the state at the time of writing is shown for one NAND cell as shown in FIG. 4(b). As a result, data is written in accordance with the data applied to the bit line only in the memory cells along the word l1WL.

In the unselected cell block 11□, the selection gate SG is at the "L" level, as in the case of data erasure, so the first booster circuit 152 does not work, and therefore the second booster circuit 16□ also does not work. I don't work. As a result, word lines are commonly selected in adjacent cell blocks, but data is written only in one cell block depending on the selection of the selection gate.

Thus, according to this embodiment, by giving priority to the first booster circuit for the selection gate and using its output to control the second booster circuit for the word line, In a NAND cell type EEPROM in which a row decoder output line is connected to a cell block, data can be easily rewritten in units of cell blocks.

The present invention is not limited to the above embodiments.

For example, in the embodiment, the NAND cell is configured with 8 gi memory cells, but this number may be arbitrary, and may be set to 4, for example. Other aspects of the invention can be implemented with various modifications without departing from the spirit thereof.

[Effects of the Invention] As described above, according to the present invention, the NAND cell type E in which the row decoder output line is shared between cell blocks
It is possible to provide an EEPROM which is an EFROM and has an optimized booster circuit section for data rewriting.

[Brief explanation of drawings]

Fig. 1 is an equivalent circuit diagram showing the main part configuration of an EEFROM according to an embodiment of the present invention, Fig. 2 is an equivalent circuit diagram showing the main part in detail, and Fig. 3 is a state of boosting during data writing. Figures 4(a) and 4(b) show the NAND during data rewriting.
Figure 5 shows the potential state of the cell. Figure 5 is a plan view showing the configuration of one NAND cell. Figure 6 (a) and (b) are AA' and B-B in Figure 5.
'It is a sectional view. 11 (11+, 1lz)...Cell block, 1
2...Row decoder, 13...Sense amplifier, 1
4...Column decoder, 15 (15152)...
First booster circuit, 16 (16162)...Second booster circuit,! )41-M8...Memory cell, Sr, S2
...Selection gate, CGl~CG, ...$ control gate, WL, ~WLB ...Word line, BL,
~BL,. 24... Bit line, 1... Si substrate, 2
... Field insulating film, 3.5... Gate insulating film, 4... Floating gate, 6.
...Control gate, 7...CVD insulation film, 8...AI
! Wiring (bit!! i, 9...n+ type layer.

Claims (2)

[Claims] (1) A floating gate and a control gate are stacked on a semiconductor substrate, and a plurality of rewritable memory cells are connected in series, which perform writing and erasing by exchanging charges using tunnel current between the floating gate and the substrate. A memory array comprising NAND cells arranged in a matrix, one end of each NAND cell connected to a bit line via a selection gate, and a control gate of each memory cell connected to a word line; A row decoder selects a word line of this memory array, a column decoder selects a bit line, a sense amplifier detects data on the bit line, and a high voltage is applied to the selected gate and word line selected during rewriting. a first booster circuit that supplies a high voltage to a selected selection gate; and a booster circuit that applies a high voltage to a selected word line under the control of the output of the first booster circuit. A nonvolatile semiconductor memory device comprising: a second booster circuit that supplies voltage. (2) The row decoder has an output line commonly connected to a plurality of corresponding word lines in at least two cell array blocks, and separate output lines to the selection gate control lines of the two cell array blocks. 2. The nonvolatile semiconductor memory device according to claim 1, wherein: