JPH05174588A - Erasing method for data of nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To perform a high speed operation without adverse influence to a periphery at the time of erasing data by applying a predetermined positive potential to a drain, a source, a channel of a selective memory cell and applying a predetermined negative potential to a control gate. CONSTITUTION:Data of a memory cell is electrically selectively erased by a predetermined sector. In this case, a ground potential or a higher positive potential than the ground potential is applied to a drain, a source and a channel of a selective memory cell so as to extract charges stored in a floating gate 6 of the selective memory cell in a predetermined sector to be erased. Further, a lower negative potential than the ground potential is applied to a control gate 8 of the selective memory cell. According to this method, it is not necessary to apply a relatively high voltage to the drain, the source, thereby preventing a decrease in the reliability of a peripheral transistor. In addition, a time for raising voltage to a high voltage is eliminated, and a high speed operation can be performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for erasing data in a non-volatile semiconductor memory device, and more particularly to a method for selectively erasing data in an electrically writable and erasable flash memory.

[0002]

2. Description of the Related Art A non-volatile semiconductor memory device is a memory device in which written data does not disappear even when the power is turned off.
Various researches and developments have been made in the past. In such a non-volatile semiconductor memory device, the flash memory is electrically writable and erasable, and thus is very useful for replacement with a magnetic medium, which allows the density of memory cells to be increased.

When writing data to the flash memory, an EPROM (Electrical Programmable Read O
Electrons are injected into the floating gate by a hot electron injection method represented by nly memory). On the other hand, when erasing data, electricity is extracted from the floating gate toward the source due to an FN (Fowler-Nordhein) tunneling phenomenon between the source and the floating gate. But,
In this erasing method, it is difficult to reduce the cell size because a high breakdown voltage structure is required on the source side. So now,
Substrate erasing method (eg IED
M 1990 P111-114 S.Aritome, R.Shirota, T.Endoh,
R. Nakayama, K. Sakai and F. Masuoka "A RELIABLE BI
POLARITY WRITE / ERASE TECHNOLOGY IN FLASH EEPROMs "
) Is being developed.

FIG. 4 shows the structure of a memory cell used for erasing a substrate. The structure will be described below along the manufacturing process. The N well 2 is formed on the P-type semiconductor silicon substrate 1, and the P well 3 is formed on the substrate surface of the N well 2. A first gate oxide film 5 of silicon oxide having a thickness of about 100 to 150 Å is formed on the surface of the semiconductor substrate of the P well 3, and a thickness of 10 is formed on the first gate oxide film 5.
The floating gate 6 made of a polycrystalline silicon layer of about 00 to 1500 Å is formed by the CVD method (chemical vapor deposition method).

Next, a thickness of 1 is formed on the floating gate 6.
A second gate insulating film 7 made of silicon oxide having a thickness of 50 to 250 Å is formed, and a thickness of 1000 to 2000 is formed thereon.
A control gate 8 having a polycrystal silicon layer of about Å or a laminated structure of polycrystal silicon and high melting point silicide is formed. Next, the control gate 8, the second gate insulating film 7, the floating gate 6, and the first gate insulating film 5 are etched in a self-aligned manner to form a stacked memory cell. After that, in a self-aligned manner with respect to the control gate 8, N corresponding to the drain and source portions is formed.
The type impurity diffusion layer 4 is introduced by an ion implantation method or the like.

Next, the write, erase, and read operations of the memory cell formed as described above will be described using the operation modes in Table 1. In Table 1, the drain voltage is Vd, the voltage of the control gate 8 (gate voltage)
Is Vg, the source voltage is Vs, the voltage of the P well 3 is Vsp,
The voltage of the N well 2 is Vsn, and the voltage of the P-type semiconductor silicon substrate 1 is Vsub.

[0007]

[Table 1]

At the time of writing, the drain voltage Vd is 5V,
The gate voltage Vg is set to about 12 V, and charges are injected into the floating gate 6 by hot electron injection to raise the threshold voltage of the memory cell. As a result, data can be written. Also, when erasing,
The gate voltage Vg is set to the ground potential, and the drain, source, P
A voltage of 18V is applied to each well 3. As a result, FN tunneling occurs between the floating gate and the channel, the charge accumulated in the floating gate 6 is extracted, and the threshold voltage of the memory cell is lowered. At this time, the potential Vsn of the N well 2 is equal to that of the P well 3
In order to prevent the potential Vsp from falling, the potential is set to 18V, which is equal to the potential Vsp of the P well 3. At the time of reading, the drain voltage Vd is set to 1V and the gate voltage Vg is set to 5V.

FIG. 5 shows a schematic configuration of a conventional memory cell array in the case of erasing data in word line units. When erasing data in such a memory cell array, the voltage of the word line XK1 (gate) to be selectively erased is set to 0 V (ground voltage) as in the above, and the other non-selected word lines XK2 to XKZ are set to 7 to. Keep at an intermediate potential of about 10V.

[0010]

However, in the conventional nonvolatile semiconductor memory device as described above, at the time of erasing data, the P well 3 (Vsp) and the N well 2 (Vs) are erased.
Since it is necessary to apply a high voltage to each of n), the drain (Vd) and the source (Vs), there is a problem that the reliability of the peripheral transistor is lowered. Further, since it takes time to boost the voltage to a high voltage, there is an inconvenience that the operation speed (erasing speed) is reduced. Further, as shown in FIG. 5, when data is erased in word line units, word lines that are not erased (non-selected word lines XK2 to XK
Since an intermediate potential of about 7 to 10 V is applied to Z), there is also a problem that the load on the peripheral open circuit becomes large.

[0011]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a non-volatile semiconductor memory device which does not adversely affect peripheral transistors at the time of erasing data and has a high operation speed.

[0012]

In order to achieve the above object, the present invention provides a drain and a source separated by a channel on a semiconductor substrate and at least a part of the channel, the drain and the source via an insulating layer. In a nonvolatile semiconductor memory device including a memory cell having a formed floating gate and a control gate formed on the floating gate via an insulating layer, data of the memory cell is electrically selected in a predetermined sector unit. At the time of erasing, the drain, the source and the channel of the selected memory cell are at the ground potential or higher than the ground potential so that the charge accumulated in the floating gate of the selected memory cell in the predetermined sector to be erased is extracted. Apply a positive potential to the control gate of the selected memory cell There has given a negative potential.

[0013]

According to the data erasing method of the present invention, since a negative potential lower than the ground potential is applied to the control gate of the memory cell to be erased, the drain,
There is no need to apply a high voltage to the source. Similarly, when performing selective erasure in sectors such as word line units and well units, sectors that are not erased (word lines, wells)
There is no need to apply an intermediate potential to.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the accompanying drawings. The structure of the memory cell according to the present embodiment is the same as that shown in FIG. 4, and thus the duplicated description will be omitted. Table 2 shows operation modes of the memory cell array of the nonvolatile semiconductor memory device according to the present invention. In the table, drain voltage is Vd, control gate voltage (gate voltage, word line voltage) is Vg
, The source voltage is Vs, the voltage of the P well 3 is Vsp, the voltage of the N well 2 is Vsn, and the voltage of the P-type semiconductor silicon substrate 1 is Vsub. Since the write and read operations are the same as those of the above-mentioned conventional technique, the description thereof will be omitted and only the data erase will be described in detail.

[0015]

[Table 2]

First, the operation (voltage setting) for erasing data in cell units will be described. Drain (Vd
), Source (Vs), P-well 3 (Vsp) 5V each
A voltage of about -12V is applied to the gate 8 (Vg). With such a voltage setting,
By the F-N tunneling between the channel (P well 3) and the floating gate 8, the floating gate 8
The charges stored in the memory cell are discharged in the channel direction, and the threshold voltage of the memory cell is lowered. As a result, the data in the memory cell is erased. Here, the potential Vsn of the N well 2 is set to 5V, which is equal to the potential Vsp of the P well 3 in order to prevent the potential Vsp of the P well 3 from dropping. If the above memory cells are assembled in a matrix array, selective erasing can be performed in sector units without using an intermediate voltage.

FIG. 1 is a schematic diagram of a memory cell array according to a first embodiment of the present invention, that is, a memory cell array for executing selective erase in sectors of word line units. In the figure, the well 10 surrounded by a broken line
Is a P-well 3 and all memory cell portions are formed in the well 10. A large number of lines X1 to Xz extending in the horizontal direction from the X decoder 100 indicate word lines.

In the memory cell array as described above,
For example, in the case of selectively erasing only the memory cell group existing on the word line X1, as shown in Table 3, a negative voltage of -12 V is applied only to the selected word line X1 (Vg) and other non-selected words are selected. A ground voltage or a voltage of about 5 V is applied to the lines X2 to Xz (Vg). At this time, the drain voltage Vd, source voltage Vs, P in all memory cells
The same voltage of about 5V is applied to the well voltage Vsp and the N well voltage Vsn.

[0019]

[Table 3]

FIG. 2 is a schematic diagram of a memory cell array according to a second embodiment of the present invention in which selective erasing is performed in well-unit sectors, and is divided in the word line direction by well units. In the figure, a large number of lines X11 to X1Z extending in the horizontal direction from the X decoder 100 indicate word lines.

In the memory cell array as described above,
For example, when the well 11 is selectively erased, as shown in Table 4, the selected word lines X11 to X1z (Vg) have-
A voltage of 12 V is applied to the drain (Vd), source (Vs) and well 11 (Vs) existing on the selected well 11.
A voltage of 5V is applied to p). At this time, all drains (V
d) and the source (Vs) are set to the ground potential or open potential, and the wells 12 to 1z (Vsp) are set to the ground potential.

[0022]

[Table 4]

FIG. 3 is a schematic diagram of a memory cell array according to a third embodiment of the present invention in which selective erasing is performed in cell-based sectors on a predetermined word line. That is, in this memory cell array, the P well is divided into Z units in units of Z word lines. In the figure, a number of lines X21 to X extending from the X decoder 100 in the horizontal direction.
2z, X31 to X3z, and Xz1 to Xzz each represent a word line.

In the memory cell array as described above,
For example, when selectively erasing the word line X21 in the well 21, as shown in Table 5, a voltage of -12 V is applied to the selected word line X21 (Vg) in the selected well 21 to select the well. Non-selected word lines X21 to X2z in 21
A ground potential or a voltage of 5V is applied to (Vg).
Further, a voltage of 5V is applied to the drains (Vd) and sources (Vs) of all the memory cell groups existing in the selected well 21, and a voltage of 5V is also applied to the selected well 21 (Vsp).

[0025]

[Table 5]

On the other hand, the unselected wells 21 to 2z (Vsp) are supplied with the ground potential, and the unselected word lines X31 to Xzz (Vg) existing in the unselected wells 21 to 2z are supplied with the ground potential or 5V. The drain of the memory cell group (V
d) and the source (Vs) are ground potential or open potential. This prevents erasing of unselected word lines. According to the third embodiment, compared with the first and second embodiments, selective erasing can be performed in finer sector units, which is advantageous for expanding product applications and further increasing integration.

[0027]

As described above, in the data erasing method of the non-volatile semiconductor memory device according to the present invention, the charge accumulated in the floating gate of the selected memory cell in the predetermined sector to be erased is extracted. , A drain potential, a source potential, and a channel potential of the selected memory cell are respectively applied with a ground potential or a positive potential higher than the ground potential, and a control gate of the selected memory cell is applied with a negative potential lower than the ground potential. At times, there is an effect that the peripheral transistors are not adversely affected and high speed operation can be performed.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a memory cell array for explaining a data erasing method according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram of a memory cell array for explaining a data erasing method according to a second embodiment of the present invention.

FIG. 3 is a schematic diagram of a memory cell array for explaining a data erasing method according to a third embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a general structure of a memory cell.

FIG. 5 is a schematic diagram of a memory cell array for explaining a conventional data erasing method.

[Explanation of symbols]

 1 P-type semiconductor silicon substrate 2 N well 3 P well 4 N type impurity diffusion layer 5 First gate insulating film 6 Floating gate 7 Second insulating film 8 Control gate 100 X decoder

Claims (4)

[Claims] 1. A drain and a source separated by a channel on a semiconductor substrate, the channel, the drain,
A nonvolatile semiconductor memory device including a memory cell having a floating gate formed on at least a part of a source via an insulating layer, and a control gate formed on the floating gate via an insulating layer, When electrically selectively erasing the data of the memory cell in units of a predetermined sector, the selected memory is configured so as to extract charges accumulated in the floating gate of the selected memory cell in the predetermined sector to be erased. Non-volatile semiconductor memory characterized in that a ground potential or a positive potential higher than the ground potential is applied to the drain, source and channel of the cell, respectively, and a negative potential lower than the ground potential is applied to the control gate of the selected memory cell. Method of erasing device data. 2. A non-selected memory cell other than the selected memory cell is protected from erasing by applying a ground potential or a positive potential higher than the ground potential to the control gate of the non-selected memory cell. The method for erasing data in a nonvolatile semiconductor memory device according to claim 1. 3. The method of erasing data in a nonvolatile semiconductor memory device according to claim 1, wherein the predetermined sector is a word line unit. 4. The method of erasing data in a nonvolatile semiconductor memory device according to claim 1, wherein the predetermined sector is in units of wells.